JP2007235525A - Variable gain amplifier circuit, semiconductor integrated circuit, output power adjustment circuit, output power adjustment method, transmitter, receiver, and transceiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a variable gain amplifier without changes in noise performance by gain switching. <P>SOLUTION: As for a source grounded NMOS transistor M1 101, its gate electrode is connected to a high frequency input terminal 112, and its source electrode is connected to ground potential. As for a gate grounded NMOS transistor M2 102, its gate electrode is connected to a VCC 109, and its source electrode is connected to a drain electrode of the M1 101. A drain electrode of the M2 102 is connected to a load 104, and to an output terminal 105 to take out output power. A drain electrode of the M1 101 is connected to a MOS capacitor element 106 from a node 116, and the other end of the MOS capacitor element 106 is connected to a drain electrode of a PMOS transistor M3 107. Each of a gate electrode and a source electrode of the M3 107 is connected to a control circuit 108 and the VCC 109. The M3 107 is appropriately biased so that its resistance value may change with an output voltage of the control circuit 108. The other end of the load 104 is connected to the VCC 109. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an amplifier circuit that performs variable gain, a semiconductor integrated circuit using the same, an output power adjustment method using the circuit, and a receiver, transmitter, and transceiver including the circuit.

  A conventional first variable gain method will be described with reference to FIG.

  The first conventional example is based on a structure 2703 in which a first NMOS transistor 2701 and a second NMOS transistor 2702 are cascode-connected, and a plurality of the same structures 2704-2705 as 2703 are arranged in parallel to form a second NMOS The output 2706 is taken out from the node where the drain electrodes of the transistors 2702, 2710, and 2711 are coupled, and a load 2709 is connected between the power source 2707 and the output 2706. Structures 2703 to 2705 each have the role of a current source and determine the current flowing through load 2709. In gain switching, the gate potential of the second NMOS transistors 2702, 2710, and 2711 is switched between power supply / ground and the current flowing from the structure 2703 to 2705 is turned on / off, thereby changing the current flowing through the load and switching the gain. It is. The gain increases as the current flowing through the load increases.

  Further, a conventional second variable gain method will be described with reference to FIG.

  In the second conventional example, the source electrodes of the three transistors of the second NMOS transistor 2802, the third NMOS transistor 2803, and the fourth NMOS transistor 2804 are connected to the drain electrode of the first NMOS transistor 2801. Has a structure. Since the drain electrode of the fourth NMOS transistor 2804 is connected to VDD, the high-frequency current flowing through the fourth NMOS transistor is short-circuited and does not appear on the output 2811. On the other hand, the third NMOS transistor 2803 and the fourth NMOS transistor 2804 operate in a complementary manner. For example, when the Cont. Circuit 2807 has a Hi output, the third NMOS transistor 2803 is turned on, and the load 2805 has All of the current determined by one transistor 2801 flows, and the amplifier enters a high gain state. Conversely, when the Cont. Circuit 2807 is at the Lo output, the fourth MOS transistor 2804 is turned on, and the current distributed by the WL ratio of the second NMOS transistor 2802 and the fourth NMOS transistor 2804 flows to the load 2805. The current flowing through the load 2805 decreases. That is, the amplifier is in a low gain state.

For example, Patent Document 1, Patent Document 2, and Patent Document 3 are known as prior art document information relating to the invention of this application.
US Pat. No. 6,888,411 US Pat. No. 6,657,498 US Pat. No. 6,710,657

  However, in the first conventional gain switching method, the gm of the NMOS transistors 2701, 2712, and 2713 that determine the current flowing through the load 2709 is set according to the gain, respectively. Therefore, when the gain is switched, the following equation (18) The input equivalent noise power expressed by

Here, V _nM1 ² is the input conversion noise power of the amplifier, gm is the sum of gm of structures 2703 to 2705 connected to the load, RD is the value of the load 2709, k is the Boltzmann constant, and T is the absolute temperature. The input conversion noise power is obtained by converting the noise power added by the amplifier into the noise power input to the amplifier so that the assumption is satisfied, and the S / N ratio of the amplifier output is the amplifier. This can be obtained by adding the input converted noise power to the noise power input to. Therefore, the S / N ratio is directly compressed as the noise power increase due to the input converted noise power by the gain switching. In Conventional Example 1, since a small gm transistor is turned on in the low gain mode, the input conversion noise power is increased and SN is deteriorated.

Also, in the second conventional example, if the input equivalent noise voltages of M2 2802 and M3 2803 are V _nM2 and V _nM3 due to the total parasitic capacitance Cx 2809 connected to the node X 2808, it is derived from M2 2802 and M3 2803. The output noise voltages Vnout2 and Vnout3 are each expressed by equation (19).

As a result of gain switching, Vnout3 does not appear in the low gain mode, but Vnout3 appears in the high gain mode. Therefore, as in the gain switching method of Conventional Example 1, the output noise changes due to gain switching. Here, gm ₂ and gm ₃ are the transconductances of M2 2802 and M3 2803, respectively, and RD is the impedance of the load 2805. Considering the SN of HighGain and LowGain in the circuit of FIG.

Thus, similar to the first conventional example, the SN is deteriorated in the LowGain mode.

As in these conventional examples 1 and 2, when SN deteriorates particularly in the low gain mode, a problem occurs in the transmission block. In general, when a radio system is constructed, an unnecessary radiation level that can be output from an antenna is established by the Radio Law or a radio standard, and a transmitter is designed to comply with these regulations. That is, the output SN level (SN _OUT ) is defined. The input SN of the analog transmitter block is determined by the DAC output SN _DAC , and if the noise power added by the analog transmission block is N _ADD , SN _OUT is

G is the gain of the analog transmission block. In order to obtain a sufficient SN for the DAC, a large amplitude level should be used in the DAC. For example, if this amplitude level is set to -10 dBm in terms of 50Ω, the RFIC output level (excluding PA) is typically about 0 dBm, so the Tx gain is at most 10 dB in the high gain mode and the transmission power is high. Since control is typically required on the order of 20 dB, a gain of -10 dB is required in the low gain mode. As apparent from the equation (4), the contribution of N _ADD increases as the gain decreases. Therefore, if N _ADD deteriorates by switching the gain, SN _OUT is greatly affected. Therefore, it is not allowed in the transmitter that N _ADD increases due to gain switching.

In order to achieve the above object, the solution taken by the invention of claim 1 is:
A source electrode of the second transistor is connected to a drain electrode of the first transistor having an AC amplitude input to the gate electrode and the drain electrode of the first transistor;
A ground potential for the AC amplitude is connected to the source electrode of the first transistor,
A ground potential for the AC amplitude is connected to the gate electrode of the second transistor,
A load is connected to the drain electrode of the second transistor;
In the cascode-connected amplifier from which the output related to the AC amplitude is extracted,
And a first impedance element, a second impedance element, and an impedance control circuit;
A first terminal of the first impedance element is connected to a drain of the first transistor;
A second terminal of the first impedance element is connected to a first terminal of the second impedance element;
A second terminal of the second impedance element is connected to a ground potential with respect to the AC amplitude;
A third terminal constituted by at least one terminal of the second impedance element is connected to the impedance control circuit;
The impedance control circuit has an external input terminal,
A control signal created based on information input from the external input terminal is supplied to the third terminal.
With the configuration of the first aspect of the invention, the input conversion noise power due to gain switching does not change, so that the degradation of SN can be minimized.

In order to achieve the above object, the solution taken by the invention of claim 2 is:
The transistor of claim 1 is an NMOS transistor,
The load consists of an inductor and a capacitor connected in parallel.
According to the configuration of the second invention, it can be formed using a versatile and inexpensive CMOS process.

In order to achieve the above object, the solution taken by the invention of claim 3 is:
An emitter electrode of a second transistor is connected to a collector electrode of the first transistor in which an AC amplitude is input to a base electrode and the collector of the first transistor;
An emitter electrode of the first transistor is connected to a ground potential with respect to the AC amplitude;
A base electrode of the second transistor is connected to a ground potential with respect to the AC amplitude;
A load is connected to the collector electrode of the second transistor;
In the cascode-connected amplifier from which the output related to the AC amplitude is extracted,
And a first impedance element, a second impedance element, and an impedance control circuit;
A first terminal of the first impedance element is connected to a collector of the first transistor;
A second terminal of the first impedance element is connected to a first terminal of the second impedance element;
A second terminal of the second impedance element is connected to a ground potential with respect to the AC amplitude;
A third terminal constituted by at least one terminal of the second impedance element is connected to the impedance control circuit;
The impedance control circuit has an external input terminal,
A control signal created based on information input from the external input terminal is supplied to the third terminal.
By using the bipolar transistor according to the configuration of the third aspect of the invention, it is advantageous for reducing the power consumption and the noise compared to the configuration of the first aspect.

In order to achieve the above object, the solution taken by the invention of claim 4 is:
The transistor according to claim 3 is an NPN transistor,
The load consists of an inductor and a capacitor connected in parallel.
With the configuration of the fourth aspect of the invention, the NPN transistor has excellent performance in reducing power consumption and noise, so that improvement in these performances can be expected.

In order to achieve the above object, the solution taken by the invention of claim 5 is:
The variable gain amplifier circuit according to claim 1,
Using the first impedance element and the second impedance element connected in series as unit impedance elements,
The unit impedance element has a configuration in which a plurality of unit impedance elements are connected in parallel.
According to the configuration of the fifth invention, each unit impedance element can be configured independently, so that the degree of freedom in design is increased.

In order to achieve the above object, the solution taken by the invention of claim 6 is:
The variable gain amplifier circuit according to claim 1, wherein the second impedance element is a MOS transistor,
The first terminal is a drain electrode;
The second terminal is a source electrode;
The variable gain amplifier circuit, wherein the third terminal is a gate electrode.
According to the configuration of the sixth aspect of the invention, an arbitrary resistance value can be realized by controlling the gate electrode, so that an impedance element can be realized with a simple configuration.

In order to achieve the above object, the solution taken by the invention of claim 7 is:
The variable gain amplifier circuit according to claim 6, wherein at least two MOS transistors are connected in parallel.
Each gate electrode of the MOS transistors connected in parallel corresponds to a third terminal.
According to the structure of the seventh invention, the gain can be switched by digitally turning on and off the gate electrode of each MOS transistor, and the impedance control circuit can be simplified because it is not necessary to create a new voltage.

In order to achieve the above object, the solution taken by the invention of claim 8 is:
8. The variable gain amplifier circuit according to claim 6, wherein the MOS transistor is an NMOS transistor.
According to the configuration of the eighth invention, since the NMOS transistor gm is larger than the PMOS, a smaller resistance value can be obtained.

In order to achieve the above object, the solution taken by the invention of claim 9 is:
9. The variable gain amplifier circuit according to claim 1, wherein the first impedance element is a fixed capacitance element.
By adopting the configuration of the ninth claim, it is possible to prevent the DC current of the amplifier from leaking to the second impedance element, and to efficiently convert the DC power into the RF power.

In order to achieve the above object, the solution taken by the invention of claim 10 is:
The variable gain amplifier circuit according to claim 1, wherein the first impedance element is a variable capacitance element,
The variable capacitance element has a third terminal composed of at least one terminal,
The third terminal is connected to the impedance control circuit;
The impedance control circuit is configured by supplying a control voltage corresponding to a necessary gain to the first impedance element together with the second impedance element.
According to the configuration of the tenth invention, not only the impedance of the second impedance element but also the impedance of the first impedance element can be varied, so that the impedance variable width is increased.

In order to achieve the above object, the solution taken by the invention of claim 11 is:
The variable capacitance element according to claim 10 includes a voltage controlled variable capacitance element that realizes a variable capacitance by controlling at least a potential difference between both ends of the PN junction, and one electrode of the voltage controlled variable capacitance element is connected to the third terminal. Consists of equivalents.
According to the configuration of the eleventh aspect of the invention, the voltage controlled variable capacitance element can be configured by a bipolar process.

In order to achieve the above object, the solution taken by the invention of claim 12 is:
The variable capacitance element according to claim 10 includes a voltage control variable capacitance element that realizes a variable capacitance by controlling at least a potential difference between both ends of the MOS junction, and one electrode of the voltage control variable capacitance element is connected to the third terminal. Consists of equivalents.
According to the configuration of the twelfth aspect of the present invention, the voltage controlled variable capacitance element can be configured by a CMOS process, and the capacitance variable range can be increased.

In order to achieve the above object, the solution provided by the invention of claim 13 is:
The variable capacitance element according to claims 11 and 12 is configured by connecting a first fixed capacitance element to at least one of the electrodes of the voltage variable capacitance element.
According to the configuration of the thirteenth aspect, the amplifier and the variable capacitance element can be separated in a DC manner, and a voltage can be independently applied to the variable capacitance element.

In order to achieve the above object, the solution taken by the invention of claim 14 is:
The voltage variable capacitive element according to claim 13, wherein a second fixed capacitive element is connected to the other electrode of the electrode to which the first fixed capacitive element is connected,
Furthermore, the fourth terminal is connected to the other electrode of the electrode to which the third terminal of the voltage variable capacitance element is connected,
The fourth terminal is configured by applying a direct current potential.
According to the configuration of the fourteenth aspect of the invention, the current source of the amplifier and the variable capacitance element, and the variable capacitance element and the second impedance element can be separated in a DC manner, and the voltage range applied to the variable capacitance element is from the invention of claim 12. Is even bigger.

In order to achieve the above object, the solution taken by the invention of claim 15 is:
The variable capacitance element according to claim 10, wherein at least two sets of binary capacitance elements configured by connecting a fixed capacitance element and a switch element in series are connected in parallel,
The switch element has a control terminal corresponding to the third terminal.
According to the configuration of the fifteenth invention, since the capacitance value is digitally switched by the switching element, it is not necessary to create a new voltage by the impedance control circuit, the configuration is simplified, and the Q value of the fixed capacitance element is variable by voltage control. Since it is larger than the capacitive element, it is advantageous for noise characteristics.

In order to achieve the above object, the solution taken by the invention of claim 16 is:
The switch element according to claim 15 is
NMOS transistor,
The control terminal is constituted by a gate electrode.
According to the configuration of the sixteenth aspect of the invention, a switch can be configured with a simple configuration.

In order to achieve the above object, the solution provided by the invention of claim 17 is:
The fixed capacitance element according to the first to 16th aspects is constituted by a MOS capacitor.
According to the configuration of the seventeenth aspect of the present invention, the MOS capacitance element has a large capacitance value per unit area in a capacitance element that can be integrated in another semiconductor integrated circuit, so that the circuit area can be reduced.

In order to achieve the above object, the solution taken by the invention of claim 18 is:
The fixed capacitance element according to claim 1-16 is constituted by a MIM capacitor.
According to the configuration of the eighteenth aspect of the invention, since the MIM capacitor element has a large Q value in a capacitor element that can be integrated in another semiconductor integrated circuit, it is advantageous for reducing the noise of the circuit.

In order to achieve the above object, the solution taken by the invention of claim 19 is:
The variable gain amplifier circuit according to the first to 18th aspects is constituted by a semiconductor integrated circuit which is integrated on the same semiconductor substrate.
According to the nineteenth aspect of the invention, the variable gain amplifier circuit can be efficiently realized on a small scale.

In order to achieve the above object, the solution taken by the invention of claim 20 is:
At least the variable gain amplifier circuit according to claim 1-19;
A power detection circuit;
Means for having a set voltage value and outputting information according to the set voltage value to the variable gain amplifier;
Means for comparing the output voltage value of the power detection circuit with the set voltage value to generate a new set voltage value;
Means for outputting information according to the new set voltage value to the variable gain amplifier;
Consists of.
According to the configuration of the twentieth invention, the output power can be adjusted even with a test signal having a small power.

In order to achieve the above object, the solution taken by the invention of claim 21 is:
Step 1 for determining an output power setting value;
Step 2 of outputting information according to the output power setting value to the variable gain amplifier circuit according to claim 1-19;
Outputting a test signal to the variable gain amplifier circuit;
Detecting an output voltage related to the output power of the variable gain amplifier circuit; and
Determining whether the difference between the output power set value and the detected output voltage is within a preset allowable range;
A step 6 of changing information according to an output power setting value to be output to the variable gain amplifier when false in the step 5 of determining the authenticity;
Outputting information according to the changed output power setting value to the variable gain amplifier circuit; and
And repeating step 3-7 until step 5 becomes true.
According to the structure of the twenty-first aspect, the output power can be adjusted even with a test signal having a small power.

In order to achieve the above object, the solution provided by the invention of claim 22 is:
Comprising at least the variable gain amplifier circuit according to claim 1-19 and a power amplifier circuit having the output of the variable gain amplifier circuit as input.
The transmitter is composed of a transmitter and a transmitter / receiver.
According to the configuration of the twenty-second invention, the SN characteristics at the time of low gain of the transmitter and the transceiver can be improved.

In order to achieve the above object, the solution taken by the invention of claim 23 is:
It comprises at least a variable gain amplifying circuit according to claim 1-19 and a frequency converter circuit having the output of the variable gain amplifying circuit as an input, and a receiver and a transceiver.
According to the structure of the twenty-third aspect, the SN characteristics at the time of low gain of the receiver and the transceiver can be improved.

  The variable gain amplifier of the present invention can be used particularly as a part of a transmission / reception circuit of a wireless system.

(First embodiment)
A first embodiment of the present invention will be described below with reference to FIG. In FIG. 1, reference numeral 101 denotes a common source NMOS transistor M1, the gate electrode of M1 101 is connected from a node 115 to a high frequency input terminal 112 via a capacitor 111 (for example, MIM capacitor), and the source electrode is connected to a high frequency via a node 117. Connected to ground potential. Reference numeral 102 denotes a common-gate NMOS transistor M2. The gate electrode is connected to a VCC 109 corresponding to, for example, a high-frequency ground electrode, and the source electrode is connected to the drain electrode of the M1 101. That is, M1 101 and M2 102 constitute a cascode connection 103. The drain electrode of M2 102 is connected to, for example, a load 104 (whose value is RL) constituted by a parallel connection of an inductor and a capacitor, and is connected to an output terminal 105 to extract output power. The gate electrode of M1 101 is appropriately biased by the bias circuit 110 to operate in the saturation region. Further, the drain electrode of M1 101 is connected from the node 116 to, for example, the MOS capacitor 106, and the other end of the MOS capacitor 106 is connected to the drain electrode of the PMOS transistor M3 107. The gate electrode and the source electrode of the M3 107 are connected to the control circuit 108 corresponding to the impedance control circuit and the VCC 109 corresponding to the high frequency ground electrode, respectively. The M3 107 is appropriately biased so that the resistance value varies depending on the output voltage of the control circuit 108. Is done. The MOS capacitor 106 and the PMOS transistor 107 correspond to a first impedance element and a second impedance element, respectively. A circuit composed of the MOS capacitor 106, the PMOS transistor 107, and the control circuit 108 is referred to as a variable impedance circuit 118. The other end of the load 104 is connected to a VCC 109 corresponding to a high frequency ground electrode, for example.

  ro1 113 and ro2 114 represent the output resistances of M1 101 and M2 102, respectively, and are used in the description of the operation described later.

  The operation will be described below.

The high-frequency voltage vi constituting the high-frequency power input to the high-frequency input terminal 112 is input to the gate electrode of M1 101 via, for example, the MIM capacitor 111 and the node 115, and is converted into a high-frequency current gm1vi by the transconductance gm1 of M1 101. . The high-frequency current is voltage-converted by the output impedance Rout including the load 104 viewed from the output terminal 105 and is taken out as the output voltage gmviRout (in this embodiment, the inductor and the capacitor constituting the load 104 resonate at the target frequency. , Assuming no reactance component). The MIM capacitor 111 is a capacitor that performs direct current separation between the high frequency input terminal 112 and the input (gate) of M1 101, and is configured to have an impedance of, for example, several tens of Ω or less with respect to the frequency of the high frequency voltage vi. Since the MIM capacitor 111 has a high Q value and does not depend on the voltage at both ends of the capacitor value and is excellent in linearity, a nonlinear response can be prevented particularly by using it in the signal path. The bias circuit 110 applies a DC voltage to the gate electrode of the M1 101, and appropriately biases the M1 101 so as to obtain a gain (gm) required for the amplifier. The MOS capacitor 106 is configured to have an impedance of, for example, several tens of Ω or less with respect to the frequency of the high frequency voltage vi. MOS capacitors generally have a large capacitance value per unit area, which is advantageous for reducing the chip area when the circuit of the present invention is integrated on a semiconductor substrate. M3 107 intended to be used as a variable impedance element, the output voltage of the control circuit 108 changes the resistance value r _PMOS source-drain. r _PMOS 202 is known to obey the following equation:

Here, μp is the mobility of the low electric field of the hole, Cox is the gate oxide film thickness, W is the gate width, L is the gate length, Vsg is the source-gate voltage, and the difference between the output voltage of the control circuit and the power supply voltage 109 Voltage. Vthp represents the threshold voltage of the PMOS transistor. In this embodiment, for example, the control circuit 108 buffers a 1-bit ON / OFF control signal from a baseband LSI and generates an output voltage. The output voltage may be switched to VCC / 0V as in the present embodiment, or the voltage may be generated internally to give a voltage between VCC-0V. The r _PMOS 202 has a resistance value according to the equation (1) according to the voltage output from the control circuit 108.

  FIG. 2 explains the gain switching method of the present invention and represents an equivalent circuit of the circuit of FIG. Since the MOS capacitor 106 of FIG. 1 is several tens of ohms with respect to the target frequency, it is omitted in the equivalent circuit of FIG.

In the present invention, the output impedance of the cascode connection 103 is changed by a variable resistor ( _rPMOS 202) constituted by M3 107, and the gain is made variable. Since iout 203 flows to the parallel resistance of the output resistance ro1 113 and r _PMOS 202 of M1 101, Vx 205 is

  In addition, Iout 203 uses a current source 201 with a transconductance gm2 of M2 102,

Since the output impedance not including RL is represented by the ratio of Vout204 and Iout203,

  Since the total output impedance Rout206 is a parallel impedance of RL and the impedance represented by the equation (4),

  Therefore, the voltage gain Av is

From equation (6), it can be seen that Av (voltage gain) varies depending on the value of the r _PMOS 202.

The noise analysis of the present invention is performed using FIG. Here, noise at low gain is analyzed. Each 301, 302, noise current I _NM1 of M1 101 occurs, M2 102 occurs noise current I _nM2, r _PMOS 202 is caused noise current I _NPMOS, the noise current I _NRL generated by the load RL. Noise current generated in the transistor

Assuming (long channel approximation), output noise power at low gain

Is as follows.

The first term is the noise power appearing at the output due to the noise current of M1 101, the second term is the noise power appearing at the output due to the noise current of M2 102, the third term is the noise power appearing at the output by the load 104, and the fourth term is r _This is the noise power that appears at the output by the _PMOS 202.

  The power gain at low gain is the square of equation (6)

Therefore, the input equivalent noise power is

(9) from the equation, so that gm _1,2 r _PMOS >> 1, choose the Gm1,2, when high gain, each voltage gain at low gain, input referred noise power, when (high gain (Noise and gain are obtained in the limit of r _PMOS → ∞ in equation (9).)

Thus, according to the configuration of the present invention, it is understood that the input conversion noise power does not change by the gain switching.

  As described above, according to the variable gain amplifier according to the first embodiment, there is no change in input conversion noise power due to gain switching.

  The MOS capacitor 106 may be a MIM capacitor. Since the capacitance value of the MIM capacitor changes linearly with respect to the voltage at both ends, excellent distortion performance can be realized.

(Embodiment 2)
Hereinafter, a second embodiment of the present invention will be described with reference to FIG. This embodiment will explain a different configuration of the variable impedance circuit 118 in the first embodiment. In addition, what has the same function as Embodiment 1 attaches | subjects the same symbol, and abbreviate | omits description.

  In the variable impedance circuit 118 according to the present embodiment, the drain electrode of the NMOS transistor M4 401 is connected to the other end of the MOS capacitor 106. The gate electrode and the source electrode of the M4 401 are connected to the control circuit 402 corresponding to the impedance control circuit and the GND corresponding to the high frequency ground electrode, respectively, and the M4 401 is appropriately biased so that the resistance value changes depending on the output voltage of the control circuit 108. Is done. The MOS capacitor 106 and the NMOS transistor M4 401 correspond to a first impedance element and a second impedance element, respectively.

The output voltage of the control circuit 402, the resistance value r _NMOS between the source and the drain of M4 401 changes. r _NMOS is known to follow:

Here, μn is the mobility of the low electric field of electrons, Cox is the gate oxide film thickness, W is the gate width, L is the gate length, Vgs is the gate-source voltage, and the voltage between the output voltage of the control circuit 402 and GND It is. Vthn represents the threshold voltage of the NMOS transistor. The control circuit 402 is different from the control circuit 108 in that r voltage is set to Hi voltage when r _{NMOS is set} to low impedance, and Lo voltage is set to set high impedance.

Since the derivation of the equations (2) to (10) can be similarly performed by replacing the _rPMOS 202 with the _rNMOS , there is no change in input conversion noise power due to gain switching.

  Hereinafter, additional effects by using the NMOS transistor M4 401 will be described. The low field mobility μn of an NMOS transistor is generally assumed to be four times larger than that of a PMOS transistor μp. Since the maximum value of the gate-source voltage is the power supply voltage, when comparing (1) and (11) with the same W / L ratio, the resistance value can be realized by the equation (11). In other words, in order to obtain the same resistance value, the resistance constituted by the NMOS transistor can make W 1/4, and when the circuit of this embodiment is integrated, the area efficiency becomes high. Further, since the dynamic range of the resistance value is increased, it is advantageous when it is desired to greatly change the attenuation.

(Embodiment 3)
The third embodiment of the present invention will be described below with reference to FIG. This embodiment will explain a different configuration of the variable impedance circuit 118 in the first embodiment. In addition, what has the same function as Embodiment 1 attaches | subjects the same symbol, and abbreviate | omits description.

  In the variable impedance circuit 118 according to this embodiment, the drain electrodes of the PMOS transistor M5 501, the PMOS transistor M6 502, and the PMOS transistor M7 503 are connected to the other end of the MOS capacitor 106. The gate electrodes and source electrodes of M5 501, M6 502, and M7 503 are connected to a control circuit 504 corresponding to an impedance control circuit and a VCC 109 corresponding to a high-frequency ground electrode, respectively, and the resistance value changes depending on the output voltage of the control circuit 504. M5 501, M6 502, and M7 503 are appropriately biased. The MOS capacitor 106, the PMOS transistor group M5 501, M6 502, and M7 503 correspond to a first impedance element and a second impedance element, respectively.

  Since the fact that the input conversion noise power does not change due to the gain change has been described in the first embodiment, it will be omitted.

  In the present embodiment, it is assumed that the control circuit 504 buffers, for example, a 3-bit ON / OFF control signal from a baseband LSI and generates an output voltage. The output voltage may be a binary signal that turns on M5 501, M6 502, and M7 503, a thermometer code that turns on sequentially, or a plurality of transistors that turn on in random order.

  Hereinafter, the operation of the present embodiment will be described.

  The WL ratio of the PMOS transistor group M5 501, M6 502, M7 503 is, for example,

And change it. The control circuit 504 has a function of buffering, for example, a 3-bit parallel signal, and supplies a Hi / Lo control signal to the gate electrodes of the PMOS transistor groups M5 501, M6 502, and M7 503 according to a necessary gain level.

When the PMOS transistor groups M5 501, M6 502, and M7 503 are turned on one by one, in the case of the present embodiment, the gain changes in 6 dB steps. However, it is assumed that the impedance at the time of Hi in this embodiment is sufficiently large and can be ignored. If the value is changed two by two, the gain value can be further changed finely. The following table shows the value of voltage gain in each state when the r _{PMOS in} equation (13) is equal to the r _PMOS of 501 and the gain when only 501 is ON is 0 dB.

  As described above, in the first embodiment, since the gain change is realized by one PMOS transistor M1 107, fine gate voltage control is necessary to realize a multi-stage gain step, and various control circuits are available. Since the output voltage needs to be created, the circuit becomes complicated. However, the M5 501, M6 502, and M7 503 can have different WL values due to the configuration of this embodiment. Can be changed depending on the WL ratio. For example, even in a circuit that only buffers the ON / OFF signal as in this embodiment, a multi-step gain step can be realized, and the control circuit 504 can be simplified.

  In this embodiment, three PMOS transistors are used, but the number can be freely set. The WL ratio may be changed by W or may be changed by L. The variation characteristic is better when W is changed.

(Embodiment 4)
The fourth embodiment of the present invention will be described below with reference to FIG. This embodiment will explain a different configuration of the variable impedance circuit 118 in the first embodiment. In addition, what has the same function as Embodiment 1 attaches | subjects the same symbol, and abbreviate | omits description.

  In the variable impedance circuit 118 according to the present embodiment, the drain electrodes of the NMOS transistor M8 601, the NMOS transistor M9 602, and the NMOS transistor M10 603 are connected to the other end of the MOS capacitor 106. The gate electrode and source electrode of M8 601, M9 602, and M10 603 are connected to a control circuit 604 corresponding to an impedance control circuit and GND corresponding to a high-frequency ground electrode, respectively, so that the resistance value changes depending on the output voltage of the control circuit 604. M8 601, M9 602, M10 603 are appropriately biased. The MOS capacitor 106, the NMOS transistor groups M8 601, M9 602, and M10 603 correspond to a first impedance element and a second impedance element, respectively.

  Since the fact that the input conversion noise power does not change due to the gain change has been described in the second embodiment, it will be omitted.

Also, the control circuit 604 differs from the control circuit 504 in that r voltage is set to Hi voltage when the low _{NMOS is set} to low impedance, and Lo voltage is set to high impedance.

  Hereinafter, the additional effects of the present embodiment on the third embodiment are the same as the additional effects of the second embodiment on the first embodiment, and are therefore omitted.

(Embodiment 5)
The fifth embodiment of the present invention will be described below with reference to FIG. This embodiment will explain a different configuration of the variable impedance circuit 118 in the first embodiment. In addition, what has the same function as Embodiment 1, Embodiment 3, and Embodiment 4 attaches | subjects the same symbol, and abbreviate | omits description.

  In the variable impedance circuit 118 according to the present embodiment, the drain electrodes of the PMOS transistor M5 501, the PMOS transistor M6 502, and the PMOS transistor M7 503 are connected to the other end of the MOS capacitor 106, and the first MOS capacitor 106 is connected to the first MOS capacitor 106 from the node 116. The drain electrodes of the NMOS transistor M8 601, NMOS transistor M9 602, and NMOS transistor M10 603 are connected to the other end of the second MOS capacitor 702 connected in parallel. The gate electrodes of M5 501, M6 502, M7 503, M8 601, M9 602, and M10 603 are connected to a control circuit 701 corresponding to an impedance control circuit, and the source electrodes of M5 501, M6 502, and M7 503 are high-frequency ground electrodes. M5 501, M6 502, M7 are connected to the corresponding VCC 109, and the source electrodes of M8 601, M9 602, M10 603 are connected to GND corresponding to the high-frequency ground electrode, and the resistance value changes according to the output voltage of the control circuit 701. 503, M8 601, M9 602, and M10 603 are appropriately biased. The first MOS capacitor 106 and the second MOS capacitor 702 are the first impedance elements, and the PMOS transistor groups M5 501, M6 502, M7 503, the NMOS transistor groups M8 601, M9 602, and M10 603 are the second impedance elements. It corresponds to.

The drive voltage output from the control circuit 701 is such that r _PMOS is high impedance and high voltage, and low impedance is low voltage and NMOS transistor groups M8 601, M9 602, and M10 with respect to PMOS transistor groups M5 501, M6 502, and M7 503. In contrast to 603, r _NMOS outputs LO voltage at high impedance, HI voltage at low impedance, and reverse logic to NMOS and PMOS. In this embodiment, the control circuit 701 receives a 6-bit ON / OFF signal from the baseband, and outputs a buffered voltage to the M5 501, M6 502, M7 503, M8 601, M9 602, and M10 603.

  Since the MOS capacitor 702 is composed of several tens of Ω with respect to the target frequency like the MOS capacitor 106, the MOS capacitor 702 can be ignored, and the discussion in the first embodiment can be applied as it is, and the input converted noise power does not change by changing the gain.

  The effect additionally obtained by this Embodiment is demonstrated. As described in the second embodiment, the variable resistor constituted by the NMOS transistor can realize a smaller resistance value because the mobility of a low electric field of electrons is large. Conversely, in order to realize a large resistance, Vgs−Vthn. Is too sensitive to control. By combining with a PMOS transistor as in the present embodiment, an NMOS having a low resistance value and a PMOS having a high resistance value have a resistance to variations in Vgs−Vthn and Vthn.

(Embodiment 6)
The sixth embodiment of the present invention will be described below with reference to FIGS. The variable impedance circuit of FIGS. 8 to 12 is different from the variable impedance circuit of FIGS. 1 and 4 to 1 in place of the fixed capacitance element MOS capacitors 106 and 702 corresponding to the first impedance element, the variable impedance element. The points 801 and 901 are used and the control circuits 802, 902, 1001, 1101 and 1202 output not only the voltage for controlling the gate of the transistor but also the voltage for controlling the variable impedance element.

  The effect obtained by using the first impedance element as a variable impedance element will be described below.

  FIG. 13 is an equivalent circuit diagram when the MOS capacitor 106 has a variable impedance 801 in the circuit of FIG. Cv 1303 represents the impedance value of the variable impedance 801. Since the value of Vx is different from that of FIG. 2, Vx, −gm2Vx, Iout, and Vout are given different symbols from those of FIG. In FIG. 2, Rout 206 is used, but in FIG. 13, Zout 1308 is used because there is a reactance component due to Cv 1303. Following the derivation of equation (6), the total output impedance Zout 1308 is expressed as follows.

For the sake of simplicity, the 1 / jwCv + r _PMOS and Z _V thereafter. After all, voltage gain Av is

That is, the voltage gain varies not only with the _rPMOS 202 but also with the impedance Cv 1303 due to the variable impedance element 801. Further, if Z _V is substituted for r _PMOS in the input equivalent noise power expression of (9), the input equivalent noise power in FIG. 13 is derived.

Thus, well in this configuration, it is possible to adjust the gain by the variable impedance _{Cv (Zv), gm 1,2 Re} (Z V) >> so that 1, Cv, if you choose two values of r _PMOS, gm _The range that ₁ and ₂ can take is increased, the current can be reduced, and the current can be reduced.

  A typical configuration of variable impedance will be described below with reference to FIGS.

14 and 15 show variable impedance elements in which a varactor diode 1403 is connected in series with a MOS capacitor 106 which is a fixed capacitor. The varactor diode 1403 includes a PN type varactor diode using a PN junction capacitance and a MOS type varactor diode using a MOS depletion layer capacitance. A PN varactor diode is used in the bipolar process. However, if a PN varactor diode is made in the standard CMOS process, the low concentration side can only have a substantially uniform concentration, and the capacitance variable width is limited, but in the MOS type varactor diode, By using an ion implantation process for adjusting the threshold value of the nMOS transistor, it is possible to form a high-concentration p-type layer directly under the MOS insulating film. By introducing this ion implantation layer, the capacitance variable width can be increased. Thus greater flexibility in the capacitance value _{selected, gm 1,2 Re (Z V)} >> 1 become Cv, spreads combination of two values of r _PMOS. It is good to use properly depending on the process to be used. The operation when such a varactor diode is used will be described. Since the control voltage is connected to the anode side in the configuration of FIG.
If the voltage outputted from the control circuits 802, 902, 1001, 1101, 1202 to the variable impedance element is Vc, the voltage of the cathode 1402 is VCC in the case of FIG. 14, and the voltage of the anode 1401 is 0V in the case of FIG. The cathode-anode voltage VF is VCC-Vc and Vc, respectively. In the case of FIG. 14 where VF = VCC−VC, it is appropriate when the PMOS transistor is used as the second impedance element, and in the case of FIG. 15 where VF = VC, the NMOS transistor is used as the second impedance element. Appropriate if At this time, the varactor diode 1403 realizes a junction capacitance according to the following expression with respect to VF.

C _j0 is the depletion layer capacity per unit area. φ is the built-in potential

  k is a Boltzmann constant, q is an elementary charge, T is an absolute temperature, NA and ND are acceptor and donor concentrations, and ni is an intrinsic semiconductor carrier concentration.

  Therefore, by changing the control voltage, VF changes and the junction capacitance can be changed. If Cv = Cj, it can be seen that Av changes according to equation (14).

  16 and 17 show another configuration of the variable impedance element. 14 and 15 is different from FIG. 14 and FIG. 15 in that a fixed capacitor element, for example, a MOS capacitor 1601 is connected to a node different from a node to which the MOS capacitor 106 is connected (when the MOS capacitor 106 is connected to the anode 1401). . With this configuration, the voltage of a node that is not a node to which the control voltage of the control circuit is connected can be set freely. For example, this is effective when the variable capacity range cannot be obtained with the power supply voltage -GND. is there. In FIG. 16, a control voltage is connected to the anode 1401 and the cathode is set to 2 VCC. In FIG. 17, a control voltage is connected to the cathode 1402 and the anode 1401 is set to −VCC. In any example, when the control voltage range is VCC-GND, a control voltage difference of 2 VCC can be obtained. The configurations of FIGS. 16 and 17 can be applied regardless of whether the second impedance element is PMOS or NMOS.

  Furthermore, in the variable impedance circuit configured as shown in FIG. 12, the variable impedance unit 1203 can be configured as shown in FIGS. 18 and 19 differ from FIGS. 16 and 17 in that the MOS capacitor 106 is shared by the varactor diodes 1403 and 1801. 18 and 19, the MOS capacitor 106 can be reduced by one element. Therefore, when the configuration of the present invention is integrated in a semiconductor integrated circuit, the area can be reduced. Furthermore, since the number of control terminals can be reduced to one, the circuit configuration of the control circuit 1202 can be simplified.

  FIG. 20 shows still another configuration of the variable impedance element.

  A unit unit in which a switch element SW1 2002 composed of an NMOS transistor is connected in series with a fixed capacitor element, for example, an MIM capacitor 2001 is defined as a first binary capacitance variable element 2003, which is connected in parallel to the first binary capacitance variable element 2003. Four elements up to the fourth binary capacity variable element 2006 are connected. 14 to 19, it is desirable that the control voltages of the control circuits 802, 902, 1001, 1101 and 1202 to be output to the variable impedance element can be varied in an analog manner. However, in this embodiment, SW1 2003 to SW4 2006 is ON / OFF control can be performed. Therefore, the control circuits 802, 902, 1001, 1101, 1202 need only buffer the ON / OFF control signal from the baseband LSI, and the circuit configuration can be simplified. Furthermore, since 2001 can be a MIM capacitor having a high Q value, noise characteristics are superior to those of a MOS capacitor. Further, if the ON resistance of the NMOS switch 2003-2006 is included in the resistance value of the second impedance element, an error in the resistance value can be reduced.

(Embodiment 7)
The seventh embodiment of the present invention will be described below with reference to FIGS. 21 and FIG. 22 are different from Embodiment 1-7 in that the cascode connection 103 of FIG. 1 is composed of NMOS transistors 101 and 102, but uses NPN bipolar transistors 2101 and 2102. In FIG. 21, the cascode connection 103 is connected to the base electrode of the NPN bipolar transistor B1 2101 to the node 115, the emitter electrode of B1 2101 is connected to the node 117, the collector electrode of B1 2101 is connected to the emitter electrode of B2 2102 and the node , The base electrode of B2 2102 is connected to VCC 109, and the collector electrode of B2 2102 is connected to the output terminal 105. ro1 2103 ro2 2104 corresponds to ro1 113 ro2 114, respectively. The equivalent circuit when the cascode connection 103 in this embodiment is replaced with the cascode connection in FIG. 1 is the same as that in FIG. 2, and therefore the relationship of the expression (10) derived in the first embodiment is the same in this embodiment. To establish. That is, even if the cascode connection of the present embodiment is used, there is no change in input conversion noise power at the time of gain switching.

  Further, additional effects according to the present embodiment will be described.

  Since the NPN transistor has a transconductance that changes exponentially with respect to a change in input voltage, generally a larger gm can be realized than an NMOS transistor that changes with a linear function with respect to a change in input voltage. In other words, the same gain as that of the first embodiment can be obtained with a small amount of current, which is advantageous for reducing power consumption. Also, since a large gm can be realized, the input equivalent noise power shown in the equation (10) can be reduced, and the NF characteristics are excellent. Moreover, since the input impedance is low, it is easy to realize input power matching.

  In the embodiment, the transistors constituting the cascode connection 103 are both NPN transistors. However, even if only B1 2101 is an NPN transistor as shown in FIG. An effect is obtained.

(Embodiment 8)
The eighth embodiment of the present invention will be described below with reference to FIGS. FIG. 24 shows a block diagram of an output power adjustment circuit of a wireless system transmitter including the variable gain amplifier circuit of the present invention. A digital signal processor (DSP) 2401 has a function of outputting both a test signal for adjusting output power and a modulation signal, and a digital to analog converter (DAC) 2402 is digital data of any one of the signals output from the DSP 2401. Is converted to an analog signal. A low pass filter (LPF) 2403 attenuates the image signal output from the DAC 2402 and extracts only a necessary signal. The frequency converter 2404 performs frequency conversion in order to efficiently output the signal as power to space, and converts the signal to a frequency of approximately several GHz. For example, the variable gain amplifier 2405 switches the gain so that the output power level of the signal approaches the value set by the DSP 2401. The high frequency power amplifier 2406 amplifies the output level of the variable gain amplifier 2405 to a desired power level, and serves as a buffer between the output 2407 and the variable gain amplifier 2405. The detection circuit 2408 detects the output power of the output 2407 of the high frequency power amplifier 2406 and outputs the RMS voltage of the signal. An analog to digital converter (ADC) 2409 quantizes and digitizes the RMS voltage of the signal detected by the detector 2408. The digitized RMS value is input to the DSP 2401 and processed.

  Next, the processing flow will be described with reference to FIG.

  The DSP 2401 calibrates the output power level according to an instruction from the MAC layer, for example, when the power is turned on. First, the output power level Pset is determined. Since the DSP 2401 has a table of the relationship between bits and gains given to the control circuit 108 corresponding to the impedance control circuit of the variable gain amplifier 2405 and the output power of the transmitter at the maximum gain, the variable gain amplifier according to Pset. The optimum control bit to be given to 2405 is determined. With this as an initial value, a setting bit is transmitted to the variable gain amplifier. After the setting of the variable gain amplifier 2405 is completed, the DSP 2401 outputs a test signal, for example, a single tone of 1 MHz. A single tone is amplified from the transmitter output to obtain a frequency-converted signal, and the detector 2408 outputs the RMS voltage. The RMS voltage is converted into digital data by the ADC 2409. The DSP 2401 has an input / output relationship of the detector 2408 in advance as a table, and the digital data of the RMS voltage is converted into a corresponding output power value (Pdet). The DSP 2401 takes the difference between the obtained Pdet and (set value Pset), and determines whether the error value is equal to or smaller than the allowable value ε.

  When the determination result is YES, the DSP 2401 outputs a modulation signal and data transmission is started. On the other hand, in the case of NO, based on the difference result, the DSP 2401 changes the control bit given to the variable gain amplifier 2405 and transmits it. Thereafter, the adjustment is repeated so that Pset-Pdet <ε.

  The effect will be described below.

  The transmission output of the test signal at the output 2407 needs to be sufficiently small so as not to affect other wireless systems. However, if this is attenuated by a conventional variable gain amplifier, the input equivalent noise power increases, and the signal and noise The ratio, that is, the SN ratio was not sufficiently obtained. In the variable gain amplifier of the present invention, the input converted noise power does not deteriorate by gain switching, so that even if the signal is attenuated, the SN can be increased, and the output power adjustment system can be operated normally.

(Embodiment 9)
The ninth embodiment of the present invention will be described below with reference to FIG. FIG. 25 is a layout diagram in which the circuit of the first embodiment is integrated on the same semiconductor substrate. Components having the same functions as those in FIG. 1 are denoted by the same reference numerals. Realization as a semiconductor integrated circuit is effective in terms of area efficiency and economy.

(Embodiment 10)
The tenth embodiment of the present invention will be described below with reference to FIG. FIG. 26 shows a block diagram of a transceiver including a transmitter 2613 and a receiver 2614 including the variable gain amplifier circuit of the present invention.

  A configuration of the transmitter 2613 constituting the transceiver will be described.

  The DSP 2601 generates a modulation signal, and the DAC 2602 analogizes the modulation signal, which is a digital signal. LPF 2603 attenuates the image of the DAC 2602 output signal and selects only the desired signal. The frequency converter 2604 converts the desired signal of the baseband frequency using the carrier wave signal generated by the voltage controlled oscillator 2607. The desired signal is converted to a radio frequency. The variable gain amplifier 2605 has the configuration of the present invention, and the variable gain amplifier 2605 is supplied with a gain control signal from the DSP 2601. The high frequency power amplifier 2606 buffers between the output of the variable gain amplifier 2605 and the antenna and amplifies the output power of the variable gain amplifier 2605 to a necessary level. With this configuration, since the input equivalent noise power does not change even when the gain is switched, for example, the SN specification defined in the wireless standard can be satisfied.

  A configuration of the receiver 2614 constituting the transceiver will be described.

  Variable gain amplifier 2608 receives a radio signal and is provided with a gain control signal from DSP 2601 to amplify it with a gain determined by DSP 2601. The frequency converter 2609 converts the frequency of the radio signal using the carrier wave signal generated by the voltage controlled oscillator 2607. The radio signal is frequency converted to a baseband frequency. The LPF 2610 attenuates a frequency component twice the carrier frequency generated by frequency conversion and an interference signal other than the desired signal, and transmits only the desired frequency. A variable gain amplifier (VGA) 2611 forms a feedback loop with the DSP 2601 and adjusts the gain so that the level of the desired signal becomes the full scale of the ADC 2612. The ADC 2612 digitally converts the desired signal. The DSP 2601 filters the digitized desired signal, further eliminates unnecessary signals, performs synchronization, performs processing such as frequency coarse adjustment, fine adjustment, and waveform equalization, and demodulates signal information. According to the configuration of the present invention, since there is no change in input conversion noise power due to gain switching, an SN ratio can be ensured even in a low gain mode, so that a high quality received signal can be realized.

  The variable gain amplifier of the present invention can be used particularly as a part of a transmission / reception circuit of a wireless system.

1 is a circuit configuration diagram of a variable gain amplifier according to a first embodiment. The equivalent circuit diagram for demonstrating the gain performance in 1st Embodiment The equivalent circuit diagram for demonstrating the noise performance in 1st Embodiment Circuit diagram of variable impedance circuit in second embodiment Circuit diagram of variable impedance circuit in third embodiment Circuit diagram of variable impedance circuit in fourth embodiment Circuit diagram of variable impedance circuit in fifth embodiment Circuit diagram of variable impedance circuit in sixth embodiment Circuit diagram of variable impedance circuit in sixth embodiment Circuit diagram of variable impedance circuit in sixth embodiment Circuit diagram of variable impedance circuit in sixth embodiment Circuit diagram of variable impedance circuit in sixth embodiment Equivalent circuit diagram for explaining the operation of the sixth embodiment Circuit diagram of variable capacitance element in sixth embodiment Circuit diagram of variable capacitance element in sixth embodiment Circuit diagram of variable capacitance element in sixth embodiment Circuit diagram of variable capacitance element in sixth embodiment Circuit diagram of variable capacitance element in sixth embodiment Circuit diagram of variable capacitance element in sixth embodiment Circuit diagram of variable capacitance element in sixth embodiment Cascode connection circuit in the seventh embodiment Cascode connection circuit in the seventh embodiment Flow chart of output power adjustment method in eighth embodiment The block diagram of the output power adjustment circuit in 8th Embodiment Layout diagram of semiconductor integrated circuit according to ninth embodiment Block diagram of a transceiver according to the tenth embodiment Circuit diagram of first conventional variable gain amplifier Circuit diagram of second conventional variable gain amplifier

Explanation of symbols

101 NMOS transistor M1
102 NMOS transistor M2
103 Cascode connection structure 104 Load 105 Output terminal 106 MOS capacity 107 PMOS transistor M3
108 Control circuit 109 Power supply terminal VCC
110 Bias circuit 111 MIM capacitor 112 High frequency input terminal 113 Output resistance ro1 of M1
114 M2 output resistance ro2
115 node 116 node 117 node 118 variable impedance circuit 201 current source by transconductance of M2 -gm ₂ Vx
202 PMOS resistance r _PMOS
203 Output current Iout
204 Output voltage Vout
205 M2 source potential Vx
206 Output impedance Rout
301 M1 Noise Current Source 302 M2 Noise Current Source 303 PMOS Resistance Noise Current Source 304 Load Noise Current Source 401 NMOS Transistor M4
402 Control circuit 501 PMOS transistor M5
502 PMOS transistor M6
503 PMOS transistor M7
504 Control circuit 601 NMOS transistor M8
602 NMOS transistor M9
603 NMOS transistor M10
604 control circuit 701 control circuit 702 MOS capacitor 801 variable impedance element 802 control circuit 803 node 901 variable impedance element 902 control circuit 903 node 1001 control circuit 1101 control circuit 1202 control circuit 1203 variable impedance unit 1301 current source by transconductance of M2 -gm ₂ Vx
1303 Capacitance value of the first variable impedance element Cv
1304 Output current Iout
1305 Output voltage Vout
1302 M2 source potential Vx
1308 Output impedance Zout
1401 Anode 1402 Cathode 1403 Varactor diode 1601 MOS capacity 1602 Fixed potential 2VCC
1701 Fixed potential -VCC
1801 Varactor diode 1802 MOS capacity 1803 Cathode 2001 MIM capacity 2002 NMOS transistor SW1
2003 first binary capacitance variable element 2004 second binary capacitance variable element 2005 third binary capacitance variable element 2006 fourth binary capacitance variable element 2101 NPN bipolar transistor 2102 NPN bipolar transistor 2103 B1 output resistance ro1
2104 B2 output resistance ro2
2401 DSP
2402 DAC
2403 LPF
2404 Frequency Converter 2405 Variable Gain Amplifier 2406 High Frequency Power Amplifier 2407 Output Terminal 2408 Detection Circuit 2409 ADC
2601 DSP
2602 DAC
2603 LPF
2604 Frequency Converter 2605 Variable Gain Amplifier 2606 High Frequency Power Amplifier 2607 Voltage Controlled Oscillator 2608 Variable Gain Amplifier 2609 Frequency Converter 2610 LPF
2611 VGA
2612 ADC
2701 1st NMOS transistor 2702 2nd NMOS transistor 2703 1st cascode connection structure 2704 2nd cascode connection structure 2705 3rd cascode connection structure 2706 1st output 2707 VCC
2709 Load 2710 Second cascode-structure second NMOS transistor 2711 Third cascode-structure second NMOS transistor 2712 Second cascode-structure first NMOS transistor 2713 Third cascode-structure first NMOS transistor 2801 First NMOS transistor M1
2802 Second NMOS transistor M2
2803 Third NMOS transistor M3
2804 Fourth NMOS transistor M4
2805 Load 2806 Inverter 2807 Control circuit 2808 Node X
2809 Total parasitic capacitance Cx of node X
2810 VCC
2811 output terminal

Claims (23)

A source electrode of the second transistor is connected to a drain electrode of the first transistor having an AC amplitude input to the gate electrode and the drain electrode of the first transistor;
A ground potential for the AC amplitude is connected to the source electrode of the first transistor,
A ground potential for the AC amplitude is connected to the gate electrode of the second transistor,
A load is connected to the drain electrode of the second transistor;
In the cascode-connected amplifier from which the output related to the AC amplitude is extracted,
And a first impedance element, a second impedance element, and an impedance control circuit;
A first terminal of the first impedance element is connected to a drain of the first transistor;
A second terminal of the first impedance element is connected to a first terminal of the second impedance element;
A second terminal of the second impedance element is connected to a ground potential with respect to the AC amplitude;
A third terminal constituted by at least one terminal of the second impedance element is connected to the impedance control circuit;
The impedance control circuit has an external input terminal,
A variable gain amplifier circuit, wherein a control signal created based on information inputted from the external input terminal is supplied to the third terminal. The transistor of claim 1 is an NMOS transistor,
A variable gain amplifier circuit characterized in that the load is composed of an inductor and a capacitor connected in parallel. An emitter electrode of a second transistor is connected to a collector electrode of the first transistor in which an AC amplitude is input to a base electrode and the collector of the first transistor;
An emitter electrode of the first transistor is connected to a ground potential with respect to the AC amplitude;
A base electrode of the second transistor is connected to a ground potential with respect to the AC amplitude;
A load is connected to the collector electrode of the second transistor;
In the cascode-connected amplifier from which the output related to the AC amplitude is extracted,
And a first impedance element, a second impedance element, and an impedance control circuit;
A first terminal of the first impedance element is connected to a collector of the first transistor;
A second terminal of the first impedance element is connected to a first terminal of the second impedance element;
A second terminal of the second impedance element is connected to a ground potential with respect to the AC amplitude;
A third terminal constituted by at least one terminal of the second impedance element is connected to the impedance control circuit;
The impedance control circuit has an external input terminal,
A variable gain amplifier circuit, wherein a control signal created based on information inputted from the external input terminal is supplied to the third terminal. The transistor according to claim 3 is an NPN transistor,
A variable gain amplifier circuit characterized in that the load is composed of an inductor and a capacitor connected in parallel. The variable gain amplifier circuit according to claim 1,
Using the first impedance element and the second impedance element connected in series as unit impedance elements,
A variable gain amplifier circuit comprising a plurality of unit impedance elements connected in parallel. The variable gain amplifier circuit according to claim 1, wherein the second impedance element is a MOS transistor,
The first terminal is a drain electrode;
The second terminal is a source electrode;
The variable gain amplifier circuit, wherein the third terminal is a gate electrode. The variable gain amplifier circuit according to claim 6, wherein at least two MOS transistors are connected in parallel.
A variable gain amplifier circuit, wherein each gate electrode of the MOS transistors connected in parallel corresponds to a third terminal. 8. The variable gain amplifier circuit according to claim 6, wherein the MOS transistor is an NMOS transistor. 9. The variable gain amplifier circuit according to claim 1, wherein the first impedance element is a fixed capacitance element. The variable gain amplifier circuit according to claim 1, wherein the first impedance element is a variable capacitance element,
The variable capacitance element has a third terminal composed of at least one terminal,
The third terminal is connected to the impedance control circuit;
The impedance control circuit supplies a control voltage corresponding to a required gain to the first impedance element together with the second impedance element. The variable capacitance element according to claim 10 includes a voltage controlled variable capacitance element that realizes a variable capacitance by controlling at least a potential difference between both ends of the PN junction, and one electrode of the voltage controlled variable capacitance element is connected to the third terminal. A variable gain amplifier circuit corresponding to the above. The variable capacitance element according to claim 10 includes a voltage control variable capacitance element that realizes a variable capacitance by controlling at least a potential difference between both ends of the MOS junction, and one electrode of the voltage control variable capacitance element is connected to the third terminal. A variable gain amplifier circuit corresponding to the above. 13. The variable gain amplifier circuit according to claim 11, wherein a first fixed capacitor is connected to at least one of the electrodes of the voltage variable capacitor. The voltage variable capacitive element according to claim 13, wherein a second fixed capacitive element is connected to the other electrode of the electrode to which the first fixed capacitive element is connected,
Furthermore, the fourth terminal is connected to the other electrode of the electrode to which the third terminal of the voltage variable capacitance element is connected,
A variable gain amplifier circuit, wherein a DC potential is applied to the fourth terminal. The variable capacitance element according to claim 10, wherein at least two sets of binary capacitance elements configured by connecting a fixed capacitance element and a switch element in series are connected in parallel,
The variable gain amplifier circuit, wherein a control terminal of the switch element corresponds to the third terminal. The switch element according to claim 15 is
NMOS transistor,
The variable gain amplifier circuit, wherein the control terminal is a gate electrode. 17. The variable gain amplifier circuit according to claim 1, wherein the fixed capacitor element is a MOS capacitor. 17. The variable gain amplifier circuit according to claim 1, wherein the fixed capacitor element is a MIM capacitor. 19. A semiconductor integrated circuit, wherein the variable gain amplifier circuit according to claim 1 is integrated on the same semiconductor substrate. At least the variable gain amplifier circuit according to claim 1-19;
A power detection circuit;
Means for having a set voltage value and outputting information according to the set voltage value to the variable gain amplifier;
Means for comparing the output voltage value of the power detection circuit with the set voltage value to generate a new set voltage value;
Means for outputting information according to the new set voltage value to the variable gain amplifier;
An output power adjustment circuit. Step 1 for determining an output power setting value;
Step 2 of outputting information according to the output power setting value to the variable gain amplifier circuit according to claim 1-19;
Outputting a test signal to the variable gain amplifier circuit;
Detecting an output voltage related to the output power of the variable gain amplifier circuit; and
Determining whether the difference between the output power set value and the detected output voltage is within a preset allowable range;
A step 6 of changing information according to an output power setting value to be output to the variable gain amplifier when false in the step 5 of determining the authenticity;
Outputting information according to the changed output power setting value to the variable gain amplifier circuit; and
And repeating step 3-7 until step 5 becomes true. Comprising at least the variable gain amplifier circuit according to claim 1-19 and a power amplifier circuit having the output of the variable gain amplifier circuit as input.
Transmitter and transceiver characterized by the above. 20. A receiver and a transceiver comprising: at least the variable gain amplifier circuit according to claim 1-19; and a frequency conversion circuit having the output of the variable gain amplifier circuit as an input.

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