JP4704293B2 - Bias circuit, amplifier, and portable terminal - Google Patents

Description

  The present invention relates to a bias circuit, an amplifier, and a portable terminal used in an amplifier circuit.

  Conventionally, wireless communication systems and broadcasting systems have been widely used for mobile phones and television broadcasts, and linear modulation systems have been adopted for the wireless communication systems and broadcasting systems. A high-frequency signal is used as a communication signal that connects the transmission side and the reception side.

  At the time of communication, since communication is performed wirelessly, a high-frequency signal may be lost. Therefore, by providing an amplifier (high frequency amplifier) that amplifies the high frequency signal, for example, when transmitting, the high frequency signal is amplified in order to transmit a large transmission signal. On the other hand, when receiving, a high frequency signal is amplified in order to process a small received signal on its own circuit. As a result, high-frequency amplifiers are indispensable in wireless communication.

  However, it is known that in a high-frequency amplifier, signal distortion appears in an amplified signal when it is affected by a nonlinear operation during signal amplification. For this reason, a high frequency amplifier used in a radio communication system is required to have higher linearity.

  For example, an amplifier (small signal high frequency amplifier) for amplifying a small signal high frequency signal is used for a receiver of a portable radio terminal. In order for the small-signal high-frequency amplifier to amplify the received signal without distortion, it is required to have high linearity. However, in general, in order to achieve high linearity, it is essential that the current consumption be increased, and since the power consumption is increased, the battery driving time is shortened.

  In addition, an amplifier (high frequency power amplifier) that amplifies the power of a high frequency signal is used in a portable wireless terminal driven by a battery. Since the high frequency power amplifier consumes relatively large power, the battery driving time tends to be shortened. Therefore, in the portable radio terminal, it is necessary to increase the power consumption efficiency of the high-frequency power amplifier as much as possible in order to make the battery driving time as long as possible.

  Furthermore, it is generally known that when a strong (large) signal is input to the high-frequency amplifier, the gain is reduced and the linearity is deteriorated. Therefore, in order to maintain high linearity, it is necessary to suppress a decrease in gain when this strong signal is input.

  As described above, high-frequency amplifiers that require higher linearity are required to have high linearity with low power consumption. Here, the configuration and operation of the high-frequency amplifier circuit constituting the high-frequency amplifier will be described.

  A conventional basic high-frequency amplifier circuit includes a transistor, and amplifies a high-frequency signal input to the transistor, thereby outputting an amplified high-frequency signal. Further, a bias circuit is connected to the transistor in order to give a bias.

  Specifically, in the transistor, the base is connected to the input unit and the bias circuit, the collector is connected to the output unit, and the emitter is grounded. As a result, the high-frequency signal input to the base and the bias current supplied from the bias circuit are input to the base of the transistor, so that a high-frequency signal amplified to the collector of the transistor according to the amplification factor of the transistor is output. . Then, the amplified high frequency signal is output to the output unit.

  Here, the base current always flows through the base of the transistor due to the bias current supplied from the bias circuit. This is a bias condition called a class A bias generally used in analog circuits, and power consumption is large because a base current is always flowing.

  Therefore, the power consumption of the high-frequency amplifier can be reduced by using a class B bias or class B bias close to class B, in which the base current increases as the output power increases instead of the class A bias.

  However, since the base current increases as the output power of the class AB bias and the class B bias increases, it is desirable that the bias circuit has an output impedance as low as possible. In addition, it is not desirable that the bias condition fluctuates due to element variations and changes in environmental temperature.

  Here, with respect to each of the above demands, conventionally, the following configuration has been disclosed as a bias circuit provided in a high-frequency power amplifier.

  Patent Document 1 discloses a bias circuit in which the bias condition does not change even if the current amplification factor of each transistor fluctuates only by pairing the current amplification factor of the bias setting transistor and the current amplification factor of the amplification transistor. Has been. Further, Patent Document 2 discloses a bias circuit aimed at miniaturization by removing a choke coil that blocks an input high-frequency signal from flowing into the bias circuit. Further, Patent Document 3 proposes a bias circuit that suppresses the influence of a high-frequency signal on the bias circuit.

  Further, Patent Documents 4 and 5 disclose a bias circuit that is resistant to variations in transistor characteristics and temperature variations because it forms a current mirror circuit. Furthermore, Patent Document 6 discloses a bias circuit that increases the saturation output power and efficiency of a high-frequency amplifier and a current mirror circuit even when the power of a high-frequency input signal is increased. A bias circuit that is resistant to temperature fluctuations is disclosed.

On the other hand, Patent Document 7 discloses a bias current control circuit that improves the power added efficiency by providing a bias current control circuit that adjusts the bias current of the bias circuit according to the output power of the power amplifier. . Patent Document 8 discloses an adaptive bias circuit that improves power added efficiency of a power amplifier by adjusting a bias current according to an input high-frequency signal.
JP 63-54809 A (published March 9, 1988) JP 2002-9559 A (published on January 11, 2002) JP 2005-101733 A (published April 14, 2005) JP 11-68473 A (published March 9, 1999) Japanese Patent Laying-Open No. 2005-501458 (published on January 13, 2005) JP 2003-229730 A (released on August 15, 2003) JP 2004-40769 A (published February 5, 2004) JP 2004-343707 A (released on December 2, 2004)

  However, the above-described conventional bias circuit solves each request individually, and the bias conditions do not vary due to variations in element characteristics such as transistors and environmental temperature, improving the characteristics of the high-frequency amplifier, and reducing power consumption The linearity cannot be improved by satisfying all the functions.

  In Patent Document 1, since the bias circuit operates as a current source and has high output impedance, it cannot be used for a class AB or class B bias circuit in which the base current increases according to the output power as described above. Therefore, there is a problem that it is difficult to reduce power consumption.

  In Patent Documents 2 and 3, since the transistors on the circuit are not completely symmetric, the bias conditions vary due to transistor characteristic fluctuations, resistance characteristic fluctuations, environmental temperature changes, and the like. Therefore, there is a problem that a stable bias condition cannot be supplied.

  Further, in Patent Documents 4 and 6, since they are composed of two current mirror circuits and a transistor that compensates the base current of the amplification transistor, they are not composed entirely of one current mirror circuit. Therefore, it is necessary to further suppress variations in bias conditions due to variations in transistor characteristics and temperature variations.

  Furthermore, in Patent Document 5, the bias circuit is configured by a current mirror circuit, but the amplification transistor is not configured by a current mirror circuit. Therefore, it is necessary to further suppress variations in bias conditions due to variations in transistor characteristics and temperature variations.

  Further, the above-mentioned Patent Documents 4 and 5 have a problem that the characteristics (for example, power consumption efficiency) of the high frequency power amplifier cannot be improved because they operate only as a bias circuit. Furthermore, in the above-mentioned Patent Document 6, there is no disclosure or suggestion about suppressing a decrease in gain when a strong signal is input to the high-frequency amplifier.

  In Patent Documents 7 and 8, a bias circuit using a large number of resistors and active elements is configured, and the bias point varies due to variations in transistor characteristics and environmental temperature changes. Therefore, there is a problem that a stable bias condition cannot be supplied.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a bias capable of improving linearity with low power consumption while maintaining a stable optimum bias condition according to an input signal. It is to provide a circuit.

  In order to solve the above-described problem, the bias circuit of the present invention is configured such that in the bias circuit connected to the grounded emitter amplifier circuit using the first bipolar transistor, the current output from the current source is supplied to the base, A second bipolar transistor connected to the base of the first bipolar transistor and having a collector connected to the power source, and a third connected to the base of the second bipolar transistor and connected to the power source. A bipolar transistor, a fourth bipolar transistor having a base connected to the emitter of the third bipolar transistor, an emitter grounded, and a collector connected to the current source; and one electrode of the second bipolar transistor A first capacitor connected to the base and having the other electrode grounded; It is characterized in that it comprises.

  According to the above configuration, since the base of the second bipolar transistor is grounded in high frequency by the first capacitor, the input high frequency voltage is directly applied between the base / emitter of the second bipolar transistor. Will be. When the input high-frequency voltage increases, the voltage amplitude applied between the base / emitter of the second bipolar transistor increases, and the diode characteristics between the base / emitter of the second bipolar transistor cause the second bipolar transistor to The equivalent resistance between the base / emitter is reduced.

  As a result, the ratio at which the current supplied from the current source is divided into the base of the second bipolar transistor and the base of the third bipolar transistor changes, and more current is supplied to the base of the second bipolar transistor. Will come to be. Therefore, the bias current can be increased according to the input level.

  In the grounded emitter amplifier circuit, when a large signal is input, the output is saturated and the gain is lowered as the output level increases. On the other hand, in the grounded emitter amplifier circuit, the gain is proportional to the bias current. Thus, the gain is originally suppressed as the output level increases. However, in the bias circuit of the present invention, as the input level increases, the bias current increases. Therefore, the increase in gain caused by the increase in the bias current cancels the suppression of gain that occurs as the output level increases. Therefore, it is possible to improve linearity under an optimal bias condition corresponding to the input level.

  In addition, since the first bipolar transistor, the second bipolar transistor, the third bipolar transistor, and the fourth bipolar transistor constitute a mirror circuit, the bias condition is such that the characteristic variation of the bipolar transistor element and the ambient temperature More restrained from being affected by changes. Therefore, stable bias conditions can be maintained.

  Further, the bias circuit of the present invention does not include a resistor or the like at the output portion of the bias circuit so that a high-frequency signal does not flow into the bias circuit. Therefore, since the bias circuit of the present invention sets a voltage by a mirror circuit, that is, is configured as a voltage source, it can be used for a class AB bias or a class B bias grounded amplifier circuit. Therefore, the bias circuit of this embodiment can reduce power consumption by using a class AB bias or a class B bias.

  As described above, the bias circuit of the present invention can improve linearity with low power consumption while maintaining a stable optimum bias condition according to the input signal. In addition, since it is a simple configuration including the second to fourth bipolar transistors and the first capacitor, it is possible to reduce the size.

  In order to solve the above-described problem, a bias circuit according to the present invention includes a bias circuit connected to a grounded emitter amplifier circuit using a first bipolar transistor, the emitter being connected to the base of the first bipolar transistor, and a collector. Is connected to the power source, the base is connected to the base of the second bipolar transistor, the collector is connected to the power source, and the base is the third bipolar transistor. A fourth bipolar transistor connected to the emitter, the emitter grounded, and a collector connected to the current source; a base connected to the current source; an emitter connected to the base of the second bipolar transistor; Fifth bipolar transistor connected to power supply One electrode connected to the base of said second bipolar transistor and the other electrode is characterized by comprising a first capacitor is grounded.

  According to the above configuration, since the base of the second bipolar transistor is grounded in high frequency by the first capacitor, the input high frequency voltage is directly applied between the base / emitter of the second bipolar transistor. Will be. When the input high-frequency voltage increases, the voltage amplitude applied between the base / emitter of the second bipolar transistor increases, and the diode characteristics between the base / emitter of the second bipolar transistor cause the second bipolar transistor to The equivalent resistance between the base / emitter is reduced.

  As a result, the ratio at which the current output from the emitter of the fifth bipolar transistor is divided into the base of the second bipolar transistor and the base of the third bipolar transistor changes. A lot of current is output. Therefore, the bias current can be increased according to the input level.

  In the grounded emitter amplifier circuit, when a large signal is input, the output is saturated and the gain is lowered as the output level increases. On the other hand, in the grounded emitter amplifier circuit, the gain is proportional to the bias current. Thus, the gain is originally suppressed as the output level increases. However, in the bias circuit of the present invention, as the input level increases, the bias current increases. Therefore, the increase in gain caused by the increase in the bias current cancels the suppression of gain that occurs as the output level increases. Therefore, it is possible to improve linearity under an optimal bias condition corresponding to the input level.

  In addition, since the first bipolar transistor, the second bipolar transistor, the third bipolar transistor, and the fourth bipolar transistor constitute a mirror circuit, the bias condition is such that the characteristic variation of the bipolar transistor element and the ambient temperature More restrained from being affected by changes. Therefore, stable bias conditions can be maintained.

  In addition, since the bias circuit of the present invention constitutes the above mirror circuit, the current supplied from the current source to the collector of the fourth bipolar transistor determines the collector current of the first bipolar transistor. Become.

  However, the current source also supplies current to the base of the second bipolar transistor and the base of the third bipolar transistor, and the base current changes greatly when the current fluctuation rate of each bipolar transistor changes. The collector current of one bipolar transistor will also change.

  Therefore, the bias circuit of the present invention includes a fifth bipolar transistor having a base connected to the current source, an emitter connected to the base of the second bipolar transistor, and a collector connected to the power supply. Since the current supplied to the base of the second bipolar transistor and the base of the third bipolar transistor is the current divided by the current amplification factor of the fifth bipolar transistor, it becomes extremely small. Therefore, it is possible to greatly suppress fluctuations in the collector current of the first bipolar transistor.

  Further, the bias circuit of the present invention does not include a resistor or the like at the output portion of the bias circuit so that a high-frequency signal does not flow into the bias circuit. Therefore, since the bias circuit of the present invention sets a voltage by a mirror circuit, that is, is configured as a voltage source, it can be used for a class AB bias or a class B bias grounded amplifier circuit. Therefore, the bias circuit of this embodiment can reduce power consumption by using a class AB bias or a class B bias.

  As described above, the bias circuit of the present invention can improve linearity with low power consumption while maintaining a stable optimum bias condition according to the input signal. Moreover, since it is a simple structure comprised from the 2nd-5th bipolar transistor and 1st capacity | capacitance, it becomes possible to reduce in size.

  In the bias circuit of the present invention, it is preferable that a first resistor is provided on at least one of both sides of the first capacitor. Thus, since the first resistor is provided on at least one of the both sides of the first capacitor, it is possible to adjust the degree of the amount of charge accumulated in the first capacitor.

  Note that there is a method of adjusting the capacitance value of the first capacitor in order to adjust the amount of charge accumulated in the first capacitor. However, although the capacitance value actually used varies depending on the frequency and the form of the amplifier circuit, it is a very small value, and it is difficult to stably produce a small capacitance value. In addition, since the gain suppression amount due to the increase in the output level and the gain increase amount due to the increase in the bias current must be adjusted by this capacitance value, high setting accuracy is required.

  Therefore, by adding the first resistor while keeping the capacitance value of the first capacitor at a size that can be created with sufficient accuracy, the degree of the amount of charge accumulated in the first capacitor can be increased with higher accuracy. It becomes possible to adjust with.

  In order to solve the above problems, an amplifier according to the present invention includes the bias circuit and the first bipolar transistor to which a bias current is supplied from the bias circuit, and amplifies an input signal to generate an output signal. And a grounded-emitter amplifier circuit.

  According to the above configuration, since the bias circuit that maintains a stable bias condition is provided, the first bipolar transistor is operated without adverse effects. In addition, since the bias circuit capable of improving linearity with low power consumption is provided, an amplifier with improved linearity with low power consumption can be realized. Furthermore, since it is a simple configuration including the bias circuit and the first bipolar transistor, it is possible to reduce the size.

  In order to solve the above-described problems, a mobile terminal according to the present invention includes the amplifier.

  According to the above configuration, the portable terminal is small and includes the amplifier capable of improving the linearity, thereby improving the linearity during amplification and reducing the size.

  In addition, since the portable terminal includes an amplifier with low power consumption, the power consumption occupied by the amplifier is made efficient, so that the power consumption of the portable terminal can be reduced. Therefore, since the battery driving time is increased due to the low power consumption, it is possible to extend the continuous communication time or drive with a small battery. Therefore, a mobile terminal having a function that can be used for a long time can be realized.

  Furthermore, it is assumed that the portable terminal is used in various environments having different temperatures. However, by providing the above amplifier, it is possible to sufficiently suppress the fluctuation of the amplifier characteristics due to the environmental temperature, so that stable amplifier characteristics can be realized even in the temperature range required for the portable terminal. It becomes.

  In the bias circuit of the present invention, as described above, the base is supplied with the current output from the current source, the emitter is connected to the base of the first bipolar transistor, and the collector is connected to the power source. A transistor, a base connected to the base of the second bipolar transistor, a collector connected to a power source, a base connected to the emitter of the third bipolar transistor, an emitter grounded, The fourth bipolar transistor has a collector connected to the current source, and a first capacitor having one electrode connected to the base of the second bipolar transistor and the other electrode grounded.

  Therefore, by providing the first capacitor, the linearity is improved, the power consumption is low, the circuit including the first bipolar transistor and the second bipolar transistor, and the third bipolar transistor. And the fourth bipolar transistor constitute a mirror circuit, so that the bias condition is not affected by variations in the element or the environmental temperature, so that the optimum bias condition that is stable according to the input signal can be obtained. Thus, there is an effect of providing a bias circuit capable of improving linearity with low power consumption while maintaining the above.

[Embodiment 1]
An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a circuit diagram showing a basic configuration of an amplifier circuit 10 of the present embodiment. The amplifier circuit 10 is a basic circuit configured as an example for suitably explaining the bias circuit of the present invention.

  First, the basic configuration and basic operation of the amplifier circuit 10 having the bias circuit of the present embodiment will be described, and then detailed examples will be described.

  The amplifier circuit 10 (grounded emitter amplifier circuit) of the present embodiment includes a signal amplifying grounded bipolar transistor Q1 (first transistor) for amplifying a signal and a biasing bipolar transistor Q2 (first transistor) for supplying a bias. 2), a reference voltage generating bipolar transistor Q3 (third transistor) for generating a reference voltage, a reference voltage generating bipolar transistor Q4 (fourth transistor) for generating a reference voltage, and a capacitor C1 (fourth transistor). A first capacitor), a load resistor R1, a capacitor Cin for separating the DC voltage of the input or matching circuit and the base voltage of the amplifying transistor Q2, an input unit 11, an output unit 12, an input matching circuit (MNin) 13, An output matching circuit (MNout) 14 and an electric power for generating a current Iref And it includes a source 15.

  Note that the capacitor Cin is not necessary when the DC voltage is separated by the input matching circuit (MNin) or an external circuit. Further, if the output matching circuit (MNout) does not separate the DC voltage of the output unit 12 and the load resistor R1 and a problem occurs, a DC separation capacitor may be attached to the output unit.

  For convenience of explanation, in the following description, the signal amplifying grounded bipolar transistor Q1 is the amplifying transistor Q1, the biasing bipolar transistor Q2 is the biasing transistor Q2, and the reference voltage generating bipolar transistors Q3 and 4 are the reference voltage generating transistors. Let Q3,4.

  The bias circuit of the present embodiment is a part constituted by a bias transistor Q2, reference voltage generating transistors Q3 and Q4, a capacitor C1, and a current source 15, and using the emitter current Ie2 of the bias transistor Q2 as a bias current. , And supplied to the base of the amplifying transistor Q1.

  In the amplifier circuit 10, as shown in FIG. 1, the high-frequency input signal input from the input unit 11 passes through the input matching circuit 13 and the capacitor Cin and is input to the amplifier transistor Q1. The high-frequency input signal is amplified by the amplifying transistor Q1, passes through the output matching circuit 14, and is output from the output unit 12 as a high-frequency output signal.

  The input matching circuit 13 and the output matching circuit 14 are circuits provided on the input / output unit side in order to prevent reflection of signals at the input / output. The load resistor R1 is provided as a load on the collector of the amplifying transistor Q1.

  The amplifying transistor Q1 has a base connected to the input unit 11 side, specifically, the capacitor Cin, and a collector connected to the output unit 12 side and the power source side, specifically, the output matching circuit 14 and the load resistor R1. And the emitter is grounded.

  Here, a bias circuit, specifically, an emitter of the bias transistor Q2 is also connected to the base of the amplifying transistor Q1.

  The bias transistor Q2 has a base connected to the base of the reference voltage generating transistor Q3, the capacitor C1, and the current source 15, and a collector connected to the power source. Further, since the emitter is connected to the base of the amplifying transistor Q1, the emitter current Ie2 is supplied to the base of the amplifying transistor Q1. Therefore, it can be said that the biasing transistor Q2 is a base driving transistor for driving the base of the amplifying transistor Q1.

  The reference voltage generating transistor Q3 has a base connected to the base of the biasing transistor Q2, a capacitor C1, and a current source 15, a collector connected to the power supply, and an emitter connected to the base of the reference voltage generating transistor Q4. It is connected.

  The base of the reference voltage generating transistor Q4 is connected to the emitter of the reference voltage generating transistor Q3, the collector is connected to the biasing transistor Q2 and the current source 15, and the emitter is grounded.

  A two-stage transistor circuit composed of the amplifying transistor Q1 and the bias transistor Q2 and a two-stage transistor circuit composed of the reference voltage generating transistors Q3 and Q4 form a mirror circuit. Further, the reference voltage generating transistor Q4, together with the reference voltage generating transistor Q3, is a portion that generates a reference voltage by the current Iref supplied from the current source 15.

  One electrode of the capacitor C1 is connected to the base of the biasing transistor Q2, the base of the reference voltage generating transistor Q3, and the current source 15, and the other electrode is grounded.

  The current source 15 must supply current to the biasing transistor Q2. In order to set a stable bias current, it is preferable to use a band gap and a current source capable of flowing a current.

  Since the base potential of the biasing transistor Q2 is the sum of the base / emitter voltage of the amplifying transistor Q1 and the base / emitter voltage of the biasing transistor Q2, when the silicon bipolar transistor is used, 1. It becomes about 6V.

  When it is difficult to create a bandgap reference power supply that can handle an output voltage of 1.6 V when the power supply voltage is about 3 V, a bandgap reference power supply that draws current is created and a current using a P-type field effect transistor is used. It is desirable to change the direction of current using a mirror circuit or the like. In the case where accuracy is not so required, a simple resistor may be connected between the power supply and the base of the bias transistor Q2.

  With the above configuration, the high-frequency input signal input to the base of the amplifying transistor Q1 is amplified in a state where a bias condition included in the bias circuit is given, and is output as a high-frequency output signal.

  Specifically, when the input high frequency signal is small, the high frequency input signal input to the base of the amplifying transistor Q1 is supplied to the base of the amplifying transistor Q1 using the emitter current Ie2 of the biasing transistor Q2 as a bias current. (That is, the collector current of the amplifying transistor Q1 is determined by the current supplied to the collector of the reference voltage generating transistor Q4 due to the configuration of the mirror circuit) and the high frequency Output as an output signal.

  On the other hand, when the input high-frequency current increases, as will be described later, the equivalent resistance between the base and the emitter of the biasing transistor Q2 decreases, and the collector current of the amplifying transistor Q1 increases.

  In FIG. 1, all power terminals are connected to a common power source. A common power supply system simplifies the circuit. In addition, since a large high-frequency current flows from the power source to which the load resistor R1 is connected, the voltage varies according to the high-frequency current unless the power source impedance is sufficiently low. In such a case, if all the power supply terminals are shared, a high frequency signal leaks via the power supply terminals, which may adversely affect the circuit.

  In the above case, the power supply terminal may be separated. In particular, it is desirable to separate the power supply terminal to which the load resistor is connected from the other power supply terminals for the bias circuit. Even if the voltage at the power supply terminal to which the collectors of the bias transistor Q2 and the reference voltage generating transistor Q3 are connected varies slightly, there is no significant effect.

  However, depending on various characteristics such as the frequency response of the reference current source and the allowable output voltage range, a high-frequency signal leaking to the power supply terminal to which the reference current source is connected may have an adverse effect. It is desirable to connect. If only the power supply for the bias circuit is shared and the power supply terminal to which the load is connected is separated, it is less susceptible to noise and the circuit is not so complicated.

  Next, an embodiment of an amplifying circuit (small signal amplifying circuit) 20 that amplifies a small signal high-frequency signal having the configuration and function of the amplifying circuit 10 having the bias circuit will be described with reference to FIGS. To do. For convenience of explanation, members having the same functions as those shown in the drawing of the amplifier circuit 10 (FIG. 1) are denoted by the same reference numerals and description thereof is omitted.

  First, the configuration of the small signal amplifier circuit 20 will be described, and then the measurement results for the characteristics of the small signal amplifier circuit 20 will be described. FIG. 2 is a circuit diagram showing a configuration example of the small signal amplifying circuit 20 of the present embodiment.

  As shown in FIG. 2, the small signal amplifier circuit 20 (grounded emitter amplifier circuit) includes a resistor R21 and a resistor R22 (first resistor) in addition to the configuration of the amplifier circuit 10 excluding the input matching circuit 13 and the output matching circuit 14. ), A field effect transistor Q23, a reference power supply 24 for generating a voltage Vref, and a capacitor C25, and has a configuration designed for mounting on a receiver for receiving small signals.

The transistors Q1 to Q4 are SiGe NPN bipolar transistors and have a current amplification factor of about 100. The total emitter area of the amplifying transistor Q1 and the bias transistor Q2 is 30 (μm ² ), and the total emitter area of the reference voltage generating transistors Q3 and Q4 is 1 (μm ² ).

  Here, in the small signal amplifier circuit 20, the emitter areas of the reference voltage generating transistors Q3 and Q4 are set to 1/30 emitter areas of the amplifying transistor Q1 and the biasing transistor Q2, and the resistor R21 is used for generating the reference voltage. By connecting to the emitter of the transistor Q4, power consumption is reduced as much as possible. The resistor R21 is a resistor for reference voltage offset, and its resistance value is 105 (Ω).

  In this embodiment, in order to reduce the current consumption of the reference voltage generation unit, the transistor size is reduced and the resistor R21 is added to the emitter of the reference voltage generating transistor Q4. However, only one of them is used. Various methods can be used to reduce the current of the reference voltage generator with a typical current mirror.

  Further, as the high frequency power input increases, the base current supplied to the amplifying transistor Q1 increases. That is, it is necessary to increase the base current of the biasing transistor Q2 for driving it. For this purpose, the base current flowing through the biasing transistor Q2 needs to be about 1/10 or less of the reference current supplied to the reference voltage generation circuit, and is preferably 1/100 if possible. In the circuit configuration of this embodiment, 60 μA is supplied as the reference current, and a current of 0.2 μA is input to the base of the biasing transistor Q2 when a small signal is input. This current is 1/300 or less of the reference current.

  The capacitor C1 is a capacitor provided for distortion compensation. The capacity is 8 (pF) in order to make it an appropriate size that does not impair reproducibility. However, since 8 (pF) has a slightly large capacity for obtaining optimum distortion compensation, a resistor R22 is connected in series between the distortion compensation capacitor C1 and the ground in order to suppress the degree of distortion compensation. ing. The resistor R22 may be connected in series between the distortion compensating capacitor C1 and the biasing transistor Q2. The resistance value of the resistor R22 is 400 (Ω).

  In order to adjust the amount of charge accumulated in the capacitor C1 (adjustment of impedance by the capacitor C1), it is also possible to adjust the capacitance value of the capacitor C1. However, although the capacitance value actually used varies depending on the frequency and the form of the amplifier circuit, it is a very small value such as 2 (pF). It is difficult to stably produce such a small capacitance value.

  As will be described later, this capacitance value cancels out the gain suppression amount due to the increase in output level and the gain increase amount due to the increase in bias current caused by the diode characteristics between the base and emitter of the bias transistor Q2. Therefore, a high setting accuracy is required.

  Therefore, it is possible to adjust the degree of the amount of charge accumulated in the capacitor C1 with higher accuracy by adding the resistor R22 while keeping the capacitance value of the capacitor C1 at a size that can be created with sufficient accuracy. It becomes.

  In order to adjust the degree of distortion compensation, in addition to adjusting the capacitor C1 and inserting a resistor R22 in series with the capacitor C1, a resistor is provided between the emitter of the biasing transistor Q2 and the base of the amplifying transistor Q1. Or a resistor is inserted in an appropriate place in the high-frequency path (path through which the high-frequency signal flows) from the base of the amplifying transistor Q1 to the emitter of the biasing transistor Q2, the base of the biasing transistor Q2, the capacitor C1, and the ground. For example, various methods can be suitably used.

  A circuit composed of the base of the biasing transistor Q2, the capacitor C1, the resistor R22, and the ground is referred to as a distortion compensation circuit. However, the resistor R22 may be suitably provided or may not be provided.

  The current source 15 is a current source whose current increases in proportion to the temperature so that deterioration of the forward transfer characteristic (gm) due to an increase in environmental temperature can be suppressed, and serves as a reference for the current flowing through the amplifying transistor Q1. A current Iref is generated. The current Iref is designed to flow 60 (μA) under standard conditions. As a result, the collector current Ic1 of the amplifying transistor Q1 is about 2.3 (mA).

  The field effect transistor Q23 is an N-channel field effect transistor, the gate is grounded via the reference power supply 24, the drain is the output unit 12 side and the power supply side, specifically, the DC component is separated and output. Therefore, the capacitor C25, which is an output capacitor for separation, and a load resistor R1 are connected, and the source is connected to the collector of the amplifying transistor Q1, thereby forming a cascode connection.

  In addition, the field effect transistor Q23 is connected to the collector of the amplifying transistor Q1 to improve the high frequency characteristics, and is connected to the cascode, whereby the effect of gain suppression due to the capacitance between the base and the collector of the amplifying transistor Q1 is increased. It is possible to suppress an increase due to the mirror effect.

  Note that the cascode-connected transistor may be a base-grounded bipolar transistor. However, the field effect transistor has a simpler bias circuit because no current flows to the gate, and the field-effect transistor has a lower gate-drain voltage. Even so, there is an advantage that the adverse effect on the characteristics of the amplifier circuit is lower than that of the bipolar transistor.

  Here, in the small signal amplifying circuit 20, in the circuit excluding the capacitor C1, the amplifying transistor Q1, the biasing transistor Q2, and the reference voltage generating transistors Q3 and Q4 are mirror circuits for two-stage stacked bipolar transistors. ing.

  Specifically, in a situation where a high-level high-frequency signal is not input to the input unit 11, a two-stage stacked bipolar transistor circuit composed of an amplifying transistor Q1 and a biasing transistor Q2 and reference voltage generating transistors Q3 and Q4 The two-stage stacked bipolar transistor circuit constitutes a mirror circuit.

  Thus, the sum of the base / emitter voltage of the amplifying transistor Q1 and the base / emitter voltage of the biasing transistor Q2, the base / emitter voltage of the reference voltage generating transistor Q4, and the base of the reference voltage generating transistor Q3. / The sum with the emitter voltage becomes equal.

  Therefore, the base currents Ib2 and Ib3 flowing through the base of the bias transistor Q2 and the base of the reference voltage generating transistor Q3 are the same. Here, if all the transistor sizes are the same, a current obtained by subtracting the base currents Ib2 and Ib3 from the current Iref flowing from the current source 15 for current setting flows to the amplifying transistor Q1.

  Therefore, when the base currents Ib2 and Ib3 are sufficiently small compared to the current value of the current Iref, the current of the amplifying transistor Q1 and the current Iref coincide with each other even if the environmental temperature change and the transistor characteristics vary from wafer to wafer. . Therefore, the current value of the collector current Ic1 of the amplifying transistor Q1 is not affected by variations in elements due to manufacturing variations and environmental temperature changes, and thus can not vary.

  In this embodiment, in order to reduce the current consumption of the reference voltage generation circuit, the size of the transistor of the reference voltage generation circuit is reduced, and a resistor R21 is added. This circuit configuration slightly deviates from the original mirror circuit. The collector current Ic1 of the amplifying transistor Q1 in this circuit format is measured by changing the current amplification factor and the environmental temperature, and the results are shown in FIGS. 3 and 4, respectively.

  FIG. 3 is a graph showing the relationship between the collector current Ic1 of the amplifying transistor Q1 and the relative current gain, the left of the vertical axis is the collector current Ic1 (mA), the right of the vertical axis is the variation rate (%), and the horizontal The axis indicates the relative current gain.

  FIG. 4 is a graph showing the relationship between the collector current Ic1 of the amplifying transistor Q1 and the ambient temperature. The left of the vertical axis is the collector current Ic1 (mA), the right of the vertical axis is the variation rate (%), and the horizontal axis is Indicates environmental temperature (degrees).

  The amplification transistor Q1 before the change has a collector current Ic1 of about 2.3 (mA) and a current amplification factor of 100. Therefore, in order to confirm the dependency of the collector current Ic1 of the amplifying transistor Q1 on the current amplification factor, the current amplification factors of the transistors Q1 to Q4 are largely changed to 50 to 200%, respectively. The current amplification factor is a characteristic of a bipolar transistor, and is known to be the characteristic that varies the most.

  However, when the collector current Ic1 of the amplifying transistor Q1 when the current amplification factor is greatly changed to 50 to 200% is confirmed, the fluctuation rate of the current is suppressed to a fluctuation within ± 1%, which is extremely stable. It can be seen that the current is maintained.

  Further, in order to confirm the temperature dependence of the collector current Ic1 of the amplifying transistor Q1, the environmental temperature is greatly changed from -30 to 95 degrees. However, it can be seen that the collector current Ic1 of the amplifying transistor Q1 is suppressed to a fluctuation within ± 3% when the fluctuation rate of the current is confirmed.

  Therefore, in the bias circuit of the present embodiment, the amplifying transistor Q1, the biasing transistor Q2, and the reference voltage generating transistors Q3 and Q4 constitute a mirror circuit for a bipolar transistor stacked in two stages. The current flowing through the reference voltage generating transistor Q4 flows through the amplifying transistor Q1.

  Therefore, if the current flowing through the reference voltage generating transistor Q4 is set, it is possible to set the current flowing through the amplifying transistor Q1, thereby suppressing the influence of element variations due to transistor manufacturing variations and environmental temperature changes, The bias conditions do not vary, and stable bias conditions can be maintained. Therefore, the current value of the collector current Ic1 of the amplifying transistor Q1 cannot be varied.

  On the other hand, a part of the high-frequency current given as a high-frequency signal that passes through the capacitor Cin from the input unit 11 and is input to the base of the amplifying transistor Q1 flows into the capacitor C1 via the emitter of the biasing transistor Q2. . As a result, the high-frequency current flowing between the base / emitter of the biasing transistor Q2 increases as the input level of the high-frequency signal increases.

  Then, since the base / emitter of the transistor has a diode characteristic, the high-frequency current is rectified, and the equivalent resistance between the base / emitter of the bias transistor Q2 gradually decreases as the high-frequency current increases.

  When the high-frequency current is small, the amplifying transistor Q1 and the biasing transistor Q2, the reference voltage generating transistor Q4 and the reference voltage generating transistor Q3 form a mirror circuit, and the current flowing through the reference voltage generating transistor Q4 A corresponding current flows through the amplifying transistor Q1, but as the high frequency current increases, the equivalent resistance between the base and the emitter of the biasing transistor Q2 decreases. Therefore, the current Iref supplied from the current source 15 is supplied to the base of the biasing transistor Q2 at a higher rate, and the collector current Ic1 of the amplifying transistor Q1 increases.

  As a result, the current flowing through the reference voltage generating transistor Q4 is slightly reduced, and the collector voltage is slightly reduced. However, since the ratio of the current flowing through the base of the bias transistor Q2 to the current flowing through the reference voltage generating transistor Q4 is extremely small, the degree of decrease in the collector voltage is very small.

  Therefore, as the input level of the high-frequency signal input to the input unit 11 increases, more current is supplied to the base of the biasing transistor Q2 than the current supplied to the base of the reference voltage generating transistor Q3. As a result, a bias current corresponding to the increase in the input level is supplied to the base of the amplifying transistor Q1. Therefore, if the amplifier circuit is configured to support small signals (low input levels), if a signal with a strong input level is input, the transistors to be amplified cannot handle all the signals, and the amplified signals are greatly distorted. appear. However, since the amplifying transistor Q1 that amplifies the high-frequency signal amplifies the high-frequency signal as the input level increases, it is possible to output the collector current Ic1 with reduced distortion even if the input level increases.

  Here, the results of measuring the input power dependence of the bias points of the amplifying transistor Q1, the biasing transistor Q2, and the reference voltage generating transistor Q4 are shown in FIGS. 5 and 6, respectively.

  FIG. 5 is a graph showing the relationship between the base current Ib2 of the biasing transistor Q2 and the input power and the relationship between the collector current Ic4 of the reference voltage generating transistor Q4 and the input power. The left side of the vertical axis shows the base current Ib2 (ΜA), the right side of the vertical axis indicates the collector current Ic4 (μA), and the horizontal axis indicates the input power (dBuV). As reference data, the characteristics of the small signal amplifying circuit 20 when there is no distortion compensation capacitor C1, that is, when there is no distortion compensation circuit, are indicated by broken lines.

  FIG. 6 is a graph showing the relationship between the collector current Ic1 and the input power of the amplifying transistor Q1, and the vertical axis shows the collector current Ic1 (mA) and the horizontal axis shows the input power (dBuV). In addition, as reference data, characteristics when there is no distortion compensation circuit are indicated by broken lines.

  As shown in the graph of FIG. 5, regardless of the presence or absence of the distortion compensating capacitor C1, the collector current Ic4 of the reference voltage generating transistor Q4 increases from about 85 (dBuV) as the input power increases. The base current Ib2 of the biasing transistor Q2 increases correspondingly.

  Further, about 60 (μA) flows through a constant voltage generating circuit, that is, a circuit constituting the current source 15 and the reference voltage generating transistor Q4. 6 (μA) flows through the base driving circuit, that is, the circuit constituting the biasing transistor Q2 and the amplifying transistor Q1, when the input signal is 100 (dBμV) which is the maximum peak power in this application. . As the current ratio at the maximum input power is increased, the distortion compensation characteristic becomes stronger. However, since the current consumption in the bias circuit is increased, a current ratio of about 5 to 20 times is generally used.

  It can also be seen that the collector current Ic1 of the amplifying transistor Q1 increases as the base current Ib2 of the biasing transistor Q2 increases as shown in FIG. Since the current amplification factor of these transistors is about 100, the collector current Ic1 of the amplifying transistor Q1 is about 2.3 (mA) when the input power is low, and the collector current Ic1 is increased by increasing the input power. It turns out that it increases to about 5 (mA).

  By the way, in an amplifier circuit, as the output level increases, the output saturates and the gain decreases. On the other hand, when the collector current of the amplifying transistor increases, the forward transfer characteristic (gm) of the transistor increases and the gain increases.

  Therefore, in the small signal amplifier circuit 20 of the present embodiment, by adding a distortion compensation circuit, the gain increase due to the increase in the collector current cancels (cancels) the gain decrease due to the output saturation, so that the linearity is improved. The result of measuring the gain is shown in FIG.

  FIG. 7 is a graph showing the relationship between gain and input power, and the relationship between relative gain and input power. The left vertical axis represents gain (dB), the right vertical axis represents relative gain (dB), and the horizontal axis. Indicates the input power (dBuV). In addition, as reference data, characteristics when there is no distortion compensation circuit are indicated by broken lines.

  As a result of adding the distortion compensation circuit, the gain without the distortion compensation circuit is gradually deteriorated from the input power of about 70 (dBuV), whereas the gain with the added distortion compensation circuit is the input power. It can be seen that the gain is hardly deteriorated up to about 80 (dBuV).

  Moreover, the result of having measured the 3rd order input intercept point (IIP3; Third Order Input Intercept Point) used as the linearity parameter | index is shown in FIG. FIG. 8 is a graph showing the relationship between IIP3 and input power, where the vertical axis represents IIP3 (dBuV) and the horizontal axis represents input power (dBuV). In addition, as reference data, characteristics when there is no distortion compensation circuit are indicated by broken lines.

  As a result of adding the distortion compensation circuit, it can be seen that IIP3 is improved by about 5 (dB) compared to the case without the distortion compensation circuit. Usually, in order to increase IIP3 by 4 (dB), it is necessary to flow the current three times corresponding to 5 (dB). However, in the small signal amplification circuit 20 of the present embodiment, it can be seen that the linearity is improved by adding a distortion compensation circuit without increasing the current while maintaining a low current consumption.

  Therefore, in the bias circuit of the present embodiment, since the base of the bias transistor Q2 is grounded at high frequency by the capacitor C1, the high-frequency voltage input to the input unit 11 is between the base and the emitter of the bias transistor Q2. It will be applied directly to. When the high-frequency voltage input to the input unit 11 is increased, the voltage amplitude applied between the base / emitter of the biasing transistor Q2 is increased. Therefore, the biasing transistor is characterized by the diode characteristics between the base / emitter of the biasing transistor Q2. The equivalent resistance between the base and emitter of Q2 is reduced.

  As a result, the ratio at which the current Iref supplied from the current source 15 is divided into the base of the biasing transistor Q2 and the base of the reference voltage generating transistor Q3 changes, and more current is supplied to the base of the biasing transistor Q2. Will be supplied. Therefore, the bias current can be increased according to the input level.

  Further, in the small signal amplifier circuit 20, when a large signal is input to the input unit 11, the output is saturated as the output level increases, and the gain decreases. On the other hand, in the small signal amplifier circuit 20, the gain is proportional to the bias current.

  Therefore, as the output level increases, the gain is originally suppressed. However, in the bias circuit of this embodiment, the bias current increases as the input level increases. The increase in gain cancels the suppression of gain that occurs as the output level increases. Therefore, it is possible to improve linearity under an optimal bias condition corresponding to the input level.

  Further, the conventional bias circuit is basically a class A bias, and there is no need to change the bias current according to the input level. Therefore, there is no big problem even if the impedance of the bias circuit is high. However, when a class AB bias or a class B bias is used, the bias current increases as the input level increases.

  On the other hand, the base voltage of the amplifying transistor Q1 that amplifies as the input level increases decreases only slightly. Therefore, the bias circuit must keep the voltage source operation, that is, the output impedance low. If a resistor or the like is provided at the output part of the bias circuit so that a high-frequency signal does not flow into the bias circuit as in the conventional bias circuit, the output impedance becomes high. It cannot be used for.

  Therefore, the bias circuit of the present embodiment sets a voltage by a mirror circuit, that is, is configured as a voltage source, and thus can be used for a class AB bias or a class B bias amplifier circuit.

  Therefore, the bias circuit of this embodiment can reduce power consumption by using a class AB bias or a class B bias.

  As described above, the bias circuit according to the present embodiment can improve linearity with low power consumption while maintaining a stable optimum bias condition according to an input signal. Further, since the bias circuit has a simple configuration, it can be reduced in size, and the small signal amplifier circuit 20 can also be reduced in size.

  Further, as described above, in the small signal amplifying circuit 20, a part of the reference current Iref flows into the base of the biasing transistor Q2 and the base of the reference voltage generating transistor Q3. The current that determines the collector current Ic1 is a current value obtained by subtracting the base currents Ib2 and Ib3 from the reference current Iref.

  For this reason, when a transistor having a low current amplification factor is used, if the current value of the reference current Iref is slightly deviated from the setting, the current values of the base currents Ib2 and Ib3 greatly change with the change of the current amplification factor. The collector current Ic1 of the amplifying transistor Q1 also changes.

  Therefore, as shown in FIG. 9, a base current supply bipolar transistor Q35 for supplying a base current is added to the base of the bias transistor Q2 and the base of the reference voltage generation transistor Q3. FIG. 9 is a circuit diagram showing a configuration example of the amplifier circuit 30 of the present embodiment.

  As shown in FIG. 9, the amplifier circuit 30 (grounded emitter amplifier circuit) includes a base current supply bipolar transistor Q35 (fifth transistor) in addition to the configuration of the amplifier circuit 10 shown in FIG. The amplifier circuit 30 is configured to be added to the configuration of the amplifier circuit 10. However, the configuration is not limited to this, and the base current supply bipolar transistor Q35 may be added to the configuration of the small signal amplifier circuit 20 illustrated in FIG. Good.

  The base current supply bipolar transistor Q35 has a base connected to the current source 15, a collector connected to the power supply, and an emitter connected to the base of the bias transistor Q2 and the base of the reference voltage generating transistor Q3. ing.

  The amplifier circuit 30 includes the base current supply bipolar transistor Q35, so that the base current supply bipolar transistor Q35 is used as the base currents Ib2 and Ib3 of the bias transistor Q2 and the reference voltage generation transistor Q3 from the reference current Iref. Only the current divided by the current gain is reduced.

  Therefore, the current value subtracted from the reference current Iref becomes extremely small. When a transistor having a low current amplification factor is used, if the current value of the reference current Iref is slightly deviated from the setting, the base current is changed along with the change in the current amplification factor. Since the current values of Ib2 and Ib3 change greatly, the phenomenon that the collector current Ic1 of the amplifying transistor Q1 also changes can be greatly suppressed.

  The base current supply bipolar transistor Q35 may be a field effect transistor. Since this transistor does not contribute to the generation of the reference voltage of the mirror circuit, it does not have to be bipolar. By using a field effect transistor, the location connected to the reference current source 15 becomes the gate of the field effect transistor, so that no current flows. For this reason, all of the reference current flows into the reference voltage generating transistor Q4, so that more accurate current setting can be performed.

[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIGS. Configurations other than those described in the present embodiment are the same as those in the first embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of the first embodiment are given the same reference numerals, and explanation thereof is omitted. FIG. 10 is a circuit diagram showing a configuration example of the high-frequency power amplifier circuit 40 of the present embodiment.

  As shown in FIG. 10, the high frequency power amplifier circuit 40 (grounded emitter amplifier circuit) includes a base ballast resistor R45, in addition to the configuration of the amplifier circuit 10 except the resistor R21 and the current source 15 of the first embodiment. A resistor R46, a control circuit 47, a current limiting resistor R48, and an inductor L1 are further provided. The transistors Q41 to Q45 correspond to the transistors Q1 to Q4 in the amplifier circuit 10, respectively, and have the same connection configuration. However, since the types of transistors used are different as will be described later, A sign is attached.

The transistors Q41 to Q44 are NPN heterojunction bipolar transistors (HBT) using GaAs. The total emitter area of the amplifying transistor Q41 is 360 (μm ² ), the total emitter area of the biasing transistor Q42 is 120 (μm ² ), and the total emitter area of the reference voltage generating transistors Q33 and Q34 is 60 (μm ² ). ² ).

  The base ballast resistor R45 is connected in series between the emitter of the biasing transistor Q42 and the amplifying transistor Q41 in order to prevent thermal runaway in which a large current flows through the amplifying transistor Q41 due to heat.

  In order to balance the base ballast resistor R45 and the bias circuit, a resistor R46 is connected in series between the emitter of the reference voltage generating transistor Q44 and the ground. In addition, since the degree of distortion compensation is slightly reduced when the base ballast resistor R45 is inserted, the capacitance value for distortion compensation is adjusted in consideration of this fact.

  In the high frequency power amplifier circuit 40, the control circuit 47 supplies a reference current that can control the current consumption according to the output level of the output unit 12. In the control circuit 47, the current generation direction side is connected to the base of the bias transistor Q42, the base of the reference voltage generation transistor Q43, and the reference voltage generation via a current limiting resistor R48 that limits the current output from the control circuit 47. It is connected to the collector of transistor Q44.

  Unlike the resistor provided as a load in the amplifier circuit provided in the receiver shown in the first embodiment, the inductor L1 is used as a load on the output side so as not to lose the high-frequency signal to be output. Further, it is an inductor for biasing the collector of the amplifying transistor Q41. The inductor L1 has one electrode connected to the collector of the amplifying transistor Q41 and the output unit 12 side, specifically to the output matching circuit 14, and the other electrode connected to the power source.

  In the high-frequency power amplifier circuit 40 of the present embodiment, since the output efficiency is important, cascode connection is not used.

  Here, the maximum voltage from the control circuit 47 is 2.9 (V), the current limiting resistor R48 is 125 (Ω), the base ballast resistor R45 is 15 (Ω), and the resistor R46 is 10 (Ω). Yes. Further, the collector current Ic41 during idling of the amplifying transistor Q41 is 34 (mA), which is a class AB bias. Further, when the input power is 20 (dBm), the collector current Ic41 is about 180 (mA).

  Next, FIG. 11 shows the result of measuring the gain when the input power is changed in the high-frequency power amplifier circuit 40. FIG. 11 is a graph showing the relationship between gain and input power, where the vertical axis represents gain (dB) and the horizontal axis represents input power (dBm). In addition, as reference data, characteristics when there is no distortion compensation circuit are indicated by broken lines.

  Even in the gain without the distortion compensation circuit, when the input power is −5 (dBm) or more, a slight gain expansion occurs due to the current dependency of the transistor current amplification factor or parasitic capacitance, but it is −5 (dBm) or less. It can be seen that gain suppression occurs in the region of. On the other hand, in the case of a gain with a distortion compensation circuit, it can be seen that gain expansion has occurred, and that suppression of gain is suppressed.

  FIG. 12 shows the result of measuring the third-order input intercept point (IIP3) that is an index of linearity. FIG. 12 is a graph showing the relationship between IIP3 and output power. The vertical axis represents IIP3 (dBm) and the horizontal axis represents input power (dBm). In addition, as reference data, characteristics when there is no distortion compensation circuit are indicated by broken lines.

  As a result of adding the distortion compensation circuit, it can be seen that IIP3 is improved by about 2 (dB) in the high output region where the output power is 15 (dBm) or more, compared to the case without the distortion compensation circuit. Therefore, it can be seen that the high frequency power amplifier circuit 40 has improved linearity.

  As described above, in the high-frequency power amplifier circuit 40 of the present embodiment, the class AB bias and the reference current can be controlled by the control circuit 47, so that the power consumption can be reduced. Further, even in a high-frequency power amplifier circuit that handles a relatively large current, if the high-frequency power amplifier circuit 40 according to the present embodiment is used, the values of each component are set as appropriate, and the distortion compensation function is added to the current mirror type bias circuit By adding, linearity can be improved.

[Embodiment 3]
The following will describe another embodiment of the present invention with reference to FIG. Configurations other than those described in the present embodiment are the same as those in the first and second embodiments. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiments 1 and 2 are given the same reference numerals, and descriptions thereof are omitted. FIG. 13 is a block diagram illustrating a configuration example of the mobile terminal 50 according to the present embodiment.

  As shown in FIG. 13, the portable terminal 50 includes an antenna 51, a band pass filter (BPF) 52, a small signal amplifier (LNA) 53 for high frequency signals, a mixer (MIX) 54, a voltage control oscillator ( VCO) 55 and demodulation circuit (DEMOD) 56.

  Here, the small signal amplifier 53 is configured by configuring the small signal amplifier circuit 20 having the above-described bias circuit of the present invention as a small signal amplifier that amplifies a high-frequency signal of a small signal. However, the present invention is not limited to this, and the amplifier circuit 30 may be used as long as it is a small signal high-frequency amplifier having the bias circuit of the present invention.

  In the portable terminal 50, the high-frequency signal received by the antenna 51 is filtered by the band-pass filter 52 so that only the high-frequency signal in the set band passes. The high-frequency signal that has passed is amplified by the small signal amplifier 53. Next, the amplified high frequency signal is mixed with the signal generated from the voltage control transmitter 55 in the mixer 54 and demodulated by the demodulation circuit 56.

  Therefore, since the portable terminal 50 includes the small signal amplifier 53 having the bias circuit of the present invention that is small and can improve the linearity, the linearity at the time of amplification is improved. It is possible to loosen the required specification for the cutoff characteristic of the band-pass filter 52 connected to the input side, or to remove the band-pass filter 52 itself. Thereby, the loss of the filter function in the band pass filter 52 part is reduced, and it becomes possible to improve reception sensitivity. Therefore, the portable terminal 50 of the present embodiment can be small and have a highly sensitive function.

  Moreover, it is assumed that the portable terminal 50 is used in various environments having different temperatures. However, the provision of the bias circuit of the present invention makes it possible to sufficiently suppress fluctuations in the characteristics of the amplifier due to the environmental temperature. Therefore, the stable small signal amplifier 53 can be used even in the temperature range required for the portable terminal 50. It becomes possible to realize the characteristics.

  Furthermore, the bias circuit of the present invention can optimize the relationship between gain and current consumption according to the characteristics of the communication system, thereby realizing a portable terminal 50 that can be used for a long time with low power consumption. It becomes possible to do.

  In addition, although the portable terminal 50 is used suitably for radio | wireless communication, you may use it not only for this but for wired communication as needed.

[Embodiment 4]
The following will describe another embodiment of the present invention with reference to FIG. Configurations other than those described in the present embodiment are the same as those in the first to third embodiments. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiments 1 to 3 are given the same reference numerals, and descriptions thereof are omitted. FIG. 14 is a block diagram illustrating a configuration example of the mobile terminal 60 according to the present embodiment.

  As shown in FIG. 14, the portable terminal 60 includes an antenna 51, a bandpass filter (BPF) 52, a power amplifier (PA) 63, a mixer (MIX) 54, a voltage control oscillator (VCO) 55, and a modulation circuit (MOD). 66).

  Here, the power amplifier 63 is configured by configuring the high-frequency power amplifier circuit 40 having the above-described bias circuit of the present invention as a power amplifier that amplifies the power of the high-frequency signal. However, the present invention is not limited to this, and any high-power high-frequency power amplifier having the bias circuit of the present invention may be used.

  In the portable terminal 60, the high frequency signal modulated in the modulation circuit 66 is mixed with the signal generated from the voltage control transmitter 55 in the mixer 54 and output to the power amplifier 63. Next, the mixed high-frequency signal is amplified by the power amplifier 63 and is filtered by the band-pass filter 52 so that only the high-frequency signal in the set band passes. The high-frequency signal that has passed is transmitted from the antenna 51 to the communication partner side.

  Since the power amplifier has a relatively high output, generally, the power consumed by the power amplifier in the mobile terminal is considerably large in the mobile terminal. However, since the portable terminal 60 is small in size and includes the power amplifier 63 having the bias circuit of the present invention that can improve the linearity with low power consumption, the power consumption occupied by the power amplifier is made efficient. The power consumption of the terminal 60 can be reduced. Therefore, since the battery driving time is increased due to the low power consumption, it is possible to extend the continuous communication time or drive with a small battery. Therefore, the portable terminal 60 according to the present embodiment can have a small size and a function that can be used for a long time.

  In recent years, modulation schemes such as CDMA and OFDM that require high linearity have become common. Therefore, it is very important to realize high linearity while maintaining low power consumption. On the other hand, the portable terminal 60 can cope with the above modulation method.

  Moreover, it is assumed that the portable terminal 60 is used in various environments having different temperatures. However, the provision of the bias circuit of the present invention makes it possible to sufficiently suppress fluctuations in the characteristics of the amplifier due to the environmental temperature, and to realize stable characteristics of the power amplifier 63 even in the temperature range required for the portable terminal 60. It becomes possible to do.

  Furthermore, the bias circuit of the present invention can optimize the relationship between gain and current consumption according to the characteristics of the communication system, thereby realizing a portable terminal 60 that can be used for a long time with low power consumption. It becomes possible to do.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and the technical means disclosed in different embodiments can be appropriately combined. Such embodiments are also included in the technical scope of the present invention.

  The present invention can be suitably used for a communication device that performs wireless communication.

It is a circuit diagram which shows one Embodiment of the amplifier circuit which has a bias circuit in this invention. It is a circuit diagram showing one embodiment of a small signal amplifier circuit having a bias circuit in the present invention. It is a graph which shows the current amplification factor dependence of the collector current of the transistor for amplification in the said small signal amplifier circuit. It is a graph which shows the environmental temperature dependence of the collector current of the transistor for amplification in the said small signal amplifier circuit. It is a graph which shows the input power dependence of the base current of the transistor for bias in the said small signal amplifier circuit, and the collector current of the transistor for reference voltage generation. It is a graph which shows the input power dependence of the collector current of the transistor for amplification in the said small signal amplifier circuit. It is a graph which shows the input power dependence of the gain in the said small signal amplifier circuit. It is a graph which shows the input power dependence of the tertiary input intercept point in the said small signal amplifier circuit. It is a circuit diagram which shows other embodiment of the said small signal amplifier circuit. It is a circuit diagram which shows one Embodiment of the high frequency power amplifier circuit which has a bias circuit in this invention. It is a graph which shows the input power dependence of the gain in the said high frequency power amplifier circuit. It is a graph which shows the input power dependence of the tertiary input intercept point in the said high frequency power amplifier circuit. It is a block diagram which shows the structure of a portable terminal provided with the small signal amplifier comprised by the said small signal amplifier circuit. It is a block diagram which shows the structure of a portable terminal provided with the power amplifier comprised from the said high frequency power amplifier circuit.

Explanation of symbols

10,30 Amplifier circuit (Emitter grounded amplifier circuit)
15 Current source 20 Small signal amplifier circuit (grounded emitter amplifier circuit)
40 High frequency power amplifier circuit (grounded emitter amplifier circuit)
47 Control circuit 50, 60 Mobile terminal 53 Small signal amplifier (amplifier)
63 Power amplifier
Q1, Q41 Common emitter bipolar transistor for signal amplification (first transistor)
Q2, Q42 Bipolar transistor for bias (second transistor)
Q3, Q43 Bipolar transistor for generating reference voltage (third transistor)
Q4, Q44 Reference voltage generating bipolar transistor (fourth transistor)
Q23 Field effect transistor Q35 Bipolar transistor for supplying base current (fifth transistor)
C1 capacitor (first capacitor)
R22 resistor (first resistor)
L1 inductor

Claims (4)

In the bias circuit connected to the grounded emitter amplifier circuit using the first bipolar transistor,
A second bipolar transistor having a base supplied with a current output from a current source, an emitter connected to the base of the first bipolar transistor, and a collector connected to a power source;
A third bipolar transistor having a base connected to the base of the second bipolar transistor and a collector connected to a power source;
A fourth bipolar transistor having a base connected to the emitter of the third bipolar transistor, an emitter grounded, and a collector connected to the current source;
One electrode connected to the bases of said third bipolar transistor of said second bipolar transistor and the other electrode comprises a first capacitor being grounded,
Above at least one either side of the first capacitor, a bias circuit, wherein that you have a first resistor is provided. In the bias circuit connected to the grounded emitter amplifier circuit using the first bipolar transistor,
A second bipolar transistor having an emitter connected to the base of the first bipolar transistor and a collector connected to a power source;
A third bipolar transistor having a base connected to the base of the second bipolar transistor and a collector connected to a power source;
A fourth bipolar transistor having a base connected to the emitter of the third bipolar transistor, an emitter grounded, and a collector connected to a current source;
A fifth bipolar transistor having a base connected to the current source, an emitter connected to the base of the second bipolar transistor, and a collector connected to a power source;
One electrode connected to the bases of said third bipolar transistor of said second bipolar transistor and the other electrode comprises a first capacitor being grounded,
Above at least one either side of the first capacitor, a bias circuit, wherein that you have a first resistor is provided. The bias circuit according to claim 1 or 2 ,
An amplifier comprising the first bipolar transistor to which a bias current is supplied from the bias circuit, and the grounded-emitter amplifier circuit for amplifying an input signal and generating an output signal. A portable terminal comprising the amplifier according to claim 3 .

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