JP2006333107A - Bias circuit and power amplifier using the same, and radio communication device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bias circuit capable of obtaining high output with less distortion and a power amplifier using the same, and a radio communication device. <P>SOLUTION: The bias circuit is equipped with a bias circuit 12 having a voltage dividing circuit 13 which divides a first voltage to a specified value, a capacitor C2 which has one end connected to an output terminal Vout of the voltage dividing circuit 13 and the other end grounded, a first transistor Q1 which has a base b1 connected to the output terminal Vout of the voltage dividing circuit 13 through a resistor R2 and a collector c1 connected to a second power source, and a second transistor Q2 which has a collector c2 connected to an emitter e1, the collector c2 and a base b2 connected to each other, and an emitter e2 grounded, and a power amplification section 11 having a third transistor Q3 having a base b3 connected to the emitter e1 through a coil L. A high-frequency signal Pl leaking from the coil L is bypassed through equivalent capacity Hfe1×C2 and a negative feedback resistor R2 suppresses a decrease in Hfe1 during a large-amplitude operation. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a bias circuit, a power amplifier using the bias circuit, and a radio communication apparatus, and more particularly to a bias circuit including means suitable for obtaining a high output with low distortion, a power amplifier using the bias circuit, and a radio communication apparatus. .

  2. Description of the Related Art Conventionally, a circuit having two diodes connected in series and an emitter follower transistor is known as a power amplification transistor base bias circuit used in a high-frequency power amplifier (see, for example, Patent Document 1).

  The bias circuit disclosed in Patent Document 1 is formed by connecting two transistors having a collector and a base connected in series, an anode connected to a control power source through a resistor, a cathode grounded, and an anode A transistor having a base connected and an emitter grounded via a resistor, and a connection point between the emitter and the resistor connected to the base of the high frequency amplifying transistor via a high frequency cutoff choke coil.

  However, the bias circuit disclosed in Patent Document 1 has a problem that high-frequency signals are likely to leak to the bias circuit side.

  That is, when the impedance viewed from the base of the high frequency transistor to the bias circuit side is not sufficiently large with respect to the input impedance of the high frequency transistor, a part of the high frequency signal flows through the high frequency cutoff choke coil and leaks to the bias circuit side. .

  As a result, the emitter potential is lowered due to the non-linearity of the emitter follower transistor, so that there is a problem that the base potential of the high frequency transistor is also lowered and the gain of the high frequency transistor is lowered.

  As the input power to the high-frequency transistor increases, the base potential of the high-frequency transistor decreases, so that there is a problem that the output power of the high-frequency transistor cannot follow the increase in input power of the high-frequency transistor and distortion occurs.

Therefore, when integrating a bias circuit and a power amplifier circuit, it is difficult to form a high-frequency cut-off choke coil with a large inductance due to chip size restrictions, and a low-distortion and high-output power amplifier can be obtained. There is no problem.
JP 2002-335135 A (page 4, FIG. 2 (b), FIG. 4)

  The present invention provides a bias circuit with low distortion and high output, a power amplifier using the bias circuit, and a wireless communication device.

  A bias circuit according to one embodiment of the present invention is connected to a first power supply, the voltage dividing circuit that divides the first voltage into a predetermined value, one end connected to the output end of the voltage dividing circuit, and the other end A grounded capacitor, a base connected to the output terminal of the voltage dividing circuit via a resistor, a first transistor having a collector connected to a second power supply, and a collector connected to the emitter of the first transistor; And a second transistor in which the collector and the base are connected directly or through a resistor and the emitter is grounded.

  A power amplifier of one embodiment of the present invention is connected to a first power supply, and a voltage dividing circuit that divides the first voltage into a predetermined value, one end connected to the output end of the voltage dividing circuit, and the other end A grounded capacitor, a base connected to the output terminal of the voltage dividing circuit via a resistor, a first transistor having a collector connected to a second power supply, and a collector connected to the emitter of the first transistor; A bias circuit comprising: a second transistor having a collector and a base connected directly or via a resistor and an emitter grounded; a base connected to the emitter of the first transistor via a coil; A power amplifying unit for amplifying a high-frequency signal; and a third transistor having a collector connected to a power source and an emitter grounded.

  A wireless communication device of one embodiment of the present invention is connected to a signal modulation unit that modulates a high-frequency signal based on an input signal input from the outside and a first power supply, and divides the first voltage into a predetermined value. A voltage dividing circuit to be compressed, a capacitor having one end connected to the output terminal of the voltage dividing circuit and the other end grounded, and a base connected to the output terminal of the voltage dividing circuit via a resistor, to a second power source A bias circuit comprising: a first transistor having a collector connected; and a second transistor having a collector connected to the emitter of the first transistor, the collector and the base connected directly or via a resistor, and the emitter grounded. A third transistor having a base connected to the emitter of the first transistor via a coil, a collector connected to a third power source, and an emitter grounded, and the modulated high frequency A power amplifier for amplifying a signal, is characterized by comprising an antenna for transmitting the amplified signal.

  According to the present invention, it is possible to provide a bias circuit with low distortion and high output, a power amplifier using the bias circuit, and a wireless communication device.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit diagram showing a configuration of a bias circuit and a power amplifier using the same according to Embodiment 1 of the present invention.

  As shown in FIG. 1, the power amplifier 10 of the present embodiment includes a power amplifying unit 11 and a bias circuit 12 connected to the power amplifying unit 11 via a coil L and supplying a bias voltage Vbi. .

  The bias circuit 12 is connected to a first power source (not shown) via a resistor R1, and a voltage dividing circuit 13 that divides the control voltage V1 into a predetermined value and a collector c1 are connected to a second power source (not shown). ), And in terms of alternating current, the first transistor Q1 is grounded via the capacitor C1, and the emitter c1 is connected to the emitter e1 of the first transistor Q1, the collector c2 and the base b2 are connected, and the emitter e2 is grounded. The second transistor Q2 is provided.

  The voltage divider circuit 13 has a series circuit of a fourth transistor Q4 in which a base b4 and a collector c4 are so-called diode-connected, and a fifth transistor Q5 in which a base b5 and a collector c5 are connected, and the collector of the fourth transistor Q4. c4 is connected to the first power supply via the resistor R1, and the emitter e5 of the fifth transistor Q5 is grounded.

  Further, a capacitor C2 having one end grounded is connected to the output terminal Vout of the voltage dividing circuit 13, and the output terminal Vout is connected to the base b1 of the first transistor Q1 via the resistor R2.

  Here, “resistance” in this specification is not a parasitic resistance due to wiring, but, for example, a resistance formed by an impurity diffusion region or a resistor film.

  The resistor R1 determines the operating currents of the fourth and fifth transistors Q4 and Q5 of the voltage dividing circuit 13, and the capacitor C1 causes the first transistor Q1 to operate as a collector ground circuit in terms of AC.

  The bias circuit 12 is more than the base current Ib1 of the first transistor Q1 so that the base potential of the first transistor Q1 is determined by the sum of the base-emitter voltages of the fourth and fifth transistors Q4 and Q5 (Vbe4 + Vbe5). A sufficiently large current is passed through the fourth and fifth transistors Q4 and Q5.

  Therefore, the bias voltage Vbi of the bias circuit 12 is (Vbe4 + Vbe5) −Vbe1−R2Ib1≈ (Vbe4 + Vbe5) −Vbe1.

  When the first to fifth transistors Q1 to Q5 are the same transistor, for example, an InGaP / GaAs HBT (Hetero Junction Bipolar Transistor) formed on a GaAs substrate, Vbi to Vbe to 1.3 V are obtained.

  The power amplifier 11 has a base b3 connected to the emitter e1 of the first transistor Q1 of the bias circuit 12 via a high frequency blocking choke coil L, a collector c3 connected to a third power source (not shown), and an emitter The third transistor Q3 is provided with e3 grounded.

  The base b3 of the third transistor Q3 is connected to the high-frequency signal generator 14 via a series circuit of a DC cut capacitor C3 and a resistor R3, and the collector c3 is connected to the load ZL.

  When the input signal Pin is input from the high frequency signal generator 14 to the base b3, the input signal Pin is subjected to class AB amplification by the third transistor Q3, and the output power Pout is supplied to the load ZL.

Next, effects of the capacitor C2 and the resistor R2 of the bias circuit 12 will be described in detail.
First, an operation when the bias circuit 12 does not have the capacitor C2 and the resistor R2 will be described.

  In the integrated circuit, when the high-frequency blocking choke coil L having a sufficiently large inductance cannot be formed due to the restriction condition of the chip size, a part Pl of the high-frequency input signal Pin flows through the high-frequency blocking choke coil L and the second It is transmitted to the collector c2 of the transistor Q2.

  The second transistor Q2 to which the collector c2 and the base b2 are connected operates as a diode and exhibits non-linear current-voltage characteristics. Therefore, the collector DC potential of the second transistor Q2 is lowered under the influence of the high-frequency input signal Pin.

  When the collector potential of the second transistor Q2 (emitter potential of the first transistor Q1) decreases, the base potential of the third transistor Q3 also decreases accordingly.

  As the base potential of the third transistor Q3 decreases, the base current Ib3 decreases and the gain of the third transistor Q3 decreases.

  As the input signal Pin increases, the decrease in the base potential of the third transistor Q3 increases, the output power Pout cannot follow the increase in the input signal Pin, and distortion occurs in the output power Pout.

  FIG. 2 is a diagram showing the voltage-current characteristics of the second transistor Q2 in which the collector c2 and the base b2 are connected. The vertical axis current Ix indicates the emitter current Ie2 of the second transistor Q2, and the horizontal axis voltage Vx indicates the second voltage Vx. The collector potential of the transistor Q2 is shown.

  As shown in FIG. 2, when a high-frequency input signal Pin leaks into the collector c2 of the second transistor Q2 via the high-frequency blocking choke coil L, the emitter current Ie2 indicated by the broken line c has an AC amplitude ΔIa, Accordingly, collector potential Vc2 indicated by broken line d has AC amplitude ΔVa.

Since the voltage-current characteristic b of the second transistor Q2 is non-linear (approximately an exponential function), when the emitter current amplitude ΔIa and the collector voltage amplitude ΔVa exceed a certain level, the collector DC potential of the second transistor Q2 becomes Vx Changes from Vy to Vy.
As a result, the collector DC potential of the second transistor Q2 is reduced.

  Next, the operation when the bias circuit 12 has only the capacitor C2 and does not have the resistor R2 will be described.

  Since the first transistor Q1 operates as a collector ground circuit by the capacitor C1, the capacitor C2 connected in parallel to the base b1 of the first transistor Q1 is multiplied by the AC current gain Hfe1 of the first transistor Q1, and equivalently Hfe1. It appears on the emitter e1 side as a capacitance of × C2.

  As a result, the impedance Zin of the bias circuit 12 viewed from the power amplification unit 11 side is connected in parallel with the impedance (Zq2) of the second transistor Q2 and the impedance (1 / jω (Hfe1 × C2)) of the equivalent capacitor Hfe1 × C2. become. If the value of Hfe1 × C2 is increased to some extent, Zq2 >> 1 / jω (Hfe1 × C2) can be obtained, and approximately Zin = 1 / jω (Hfe1 × C2), and the voltage current of the second transistor Q2 The characteristic a is apparently linear, and the slope (ω (Hfe1 × C2)) can be made sufficiently large.

  Therefore, the high-frequency input signal Pl leaked through the high-frequency blocking choke coil L can be bypassed to the ground by the equivalent capacitor Hfe1 × C2 and blocked from flowing into the bias circuit 12.

  As a result, the emitter current amplitude of the second transistor Q2 due to the high frequency input signal Pl leaking through the high frequency blocking choke coil L is greatly reduced from ΔIa to ΔIb, and accordingly the collector voltage amplitude is also reduced from ΔVa to ΔVb. The

  As a result, the collector DC potential Vx of the second transistor Q2 is maintained substantially at Vx without being affected by the non-linear voltage-current characteristics.

  Accordingly, it is possible to suppress fluctuations in the bias voltage Vbi that becomes the emitter potential of the first transistor Q1, that is, the base potential of the third transistor Q3.

  However, when the high-frequency input signal Pin is further increased, the voltage variation at the emitter e1 of the first transistor Q1 cannot be ignored only by the equivalent capacitance Hfe1 × C2, and the variation in the base-emitter voltage Vbe1 becomes larger. The AC current gain Hfe1 of the transistor Q1 is reduced.

FIG. 3 is a diagram showing an equivalent circuit of the first transistor Q1.
As shown in FIG. 3, Hfe1 of the first transistor Q1 is a value obtained by dividing the collector current Ic by the base current Ib. The base current Ib is the sum of the current I1 flowing through the equivalent capacitance Ci and the current I2 flowing through the equivalent resistance Ri, and the collector current Ic is a DC current amplification factor β times the current I2 flowing through the equivalent resistance Ri.

  Here, when the equivalent capacitance Ci increases, the base current Ib also increases. However, since the collector current Ic does not change, Hfe decreases.

  The equivalent capacitance Ci is a function of the base-emitter voltage Vbe, and as the base-emitter voltage Vbe increases, the equivalent capacitance Ci also increases.

  Therefore, during a large signal operation, Hfe1 of the first transistor Q1 decreases, and the bypass effect of the high-frequency signal Pl due to the equivalent capacitance Hfe1 × C2 does not work sufficiently.

  Therefore, during the large signal operation, the third transistor Q3 for high frequency amplification cannot output the output power Pout following the increase in the input power Pin, and distortion occurs.

  Next, the operation when the bias circuit 12 has both the capacitor C2 and the resistor R2 will be described.

  The resistor R2 causes a negative feedback action so as to suppress the fluctuation of the base-emitter voltage Vbe1 of the first transistor Q1.

  That is, if the base-emitter voltage Vbe1 of the first transistor Q1 is increased, the base current Ib1 of the first transistor Q1 increases, so that the voltage drop due to the resistor R2 increases and the base-emitter voltage Vbe1 is decreased. Acts on direction.

  As a result, since the increase in the base-emitter voltage Vbe1 of the first transistor Q1 is suppressed even during the large signal operation, the decrease in Hfe of the first transistor Q1 is also suppressed.

  Therefore, even when a high-amplitude high-frequency input signal Pin is input to the third transistor Q3, it is possible to suppress distortion of the output power Pout of the third transistor Q3 and obtain a high output.

  4 to 7 are diagrams showing the output characteristics of the power amplifier 10 by simulation compared with a conventional power amplifier having no capacitor C2 and resistor R2, and FIG. 4 shows the DC potential at the emitter e1 of the first transistor Q1. FIG. 5 is a diagram showing the relationship between the amplitude of the high-frequency signal Pl at the emitter e1 of the first transistor Q1 and the output power Pout.

FIG. 6 is a diagram showing the relationship between the gain of the power amplifier 10 and the output power Pout, and FIG. 7 is a diagram showing the phase characteristics of the output power Pout.
In each figure, the solid line a is according to the present embodiment, and the broken line b is according to the conventional example.

  As shown in FIG. 4, when the high-frequency input signal Pin is increased, the output power Pout also increases, but the high-frequency signal Pl passing through the high-frequency blocking coil L also increases, so that the DC potential of the emitter of the first transistor Q1 is increased. Gradually decreases.

  However, in the solid line a of this embodiment, since the output power Pout exceeds 15 dBmW, the decrease in the DC potential of the emitter e1 is suppressed lower than that of the conventional broken line b due to the negative feedback action of the resistor R2.

  As shown in FIG. 5, since the amplitude of the high-frequency signal Pl at the emitter e1 of the first transistor Q1 is opposite to the direct current potential of the emitter e1 of the first transistor Q1, the solid line a in this embodiment is the same as in FIG. Since the output power Pout exceeds 15 dBm, the amplitude of the high-frequency signal Pl is suppressed lower than that of the conventional broken line b.

Further, as shown in FIG. 6, the gain (output power Pout / input power Pin) gradually increases as the output power Pout increases, and shows a peak of gain.
However, the solid line a in this embodiment has an output power Pa that gives a gain peak, which is larger than the output power Pb that gives the gain peak in the conventional broken line b, and the output power Pout in this embodiment has low distortion. It shows that.

As shown in FIG. 7, as the output power Pout increases, a voltage phase delay gradually occurs between the input power Pin and the output power Pout.
However, the solid line a in this embodiment does not have an inflection point indicating a minimum value compared to the broken line b in the conventional example, and the phase characteristic shows the same characteristic as the conventional one.

  Thereby, the amplifier 10 can obtain a high output with little distortion by the capacitor C1 and the resistor R2.

  Next, a wireless communication apparatus using the power amplifier 10 of this embodiment will be described. In this embodiment, an external input signal, for example, a signal obtained by compressing and encoding an audio / image signal by a predetermined compression method, or a received signal is decoded to reproduce the original audio / image signal. This is the case of a wireless communication device.

  As shown in FIG. 8, the wireless communication device 30 of this embodiment includes an antenna 31 that transmits or receives a radio signal, a switch 32 that selects whether the antenna 31 transmits or receives a radio signal, The signal transmission means 33 which outputs the radio signal which processed the input signal input from the antenna 31 to the antenna 31, and the signal reception means 34 which processes the radio signal received by the antenna 31 and outputs it to the outside are provided.

  The signal transmission unit 33 includes an input signal processing circuit 35 that processes a signal input from the outside, a modulation circuit 37 that modulates the output signal of the first oscillation circuit 36 by an output signal of the input signal processing circuit 35, and a modulation circuit 37. And a power amplifier 10 having a bias circuit 12 are provided.

  The signal receiving means 34 is demodulated by a low noise amplifier 39 that amplifies the radio signal received by the antenna 31, a mixer 41 that demodulates the radio signal by mixing the output of the low noise amplifier 39 and the output signal of the second oscillation circuit 40. And an output signal processing circuit 42 for processing the output signal and outputting it to the outside.

  Thereby, the wireless communication apparatus 30 can perform wireless communication with low distortion and high output.

  As described above, in this embodiment, the equivalent capacitance Hfe1 × C2 bypasses the high-frequency signal Pl leaking from the high-frequency blocking coil L, and the negative feedback action of the resistor R2 causes the first transistor Q1 to operate at high output. A decrease in Hfe1 can be suppressed.

  As a result, it is possible to suppress fluctuations in the bias voltage Vbi due to a reduction in the capacitance of the equivalent capacitor Hfe1 × C2 during high output. Therefore, low distortion and high output power Pout can be obtained.

  Further, since the high frequency blocking coil L may be small, the bias circuit and the power amplifier circuit can be integrated without increasing the chip size, so that a small power amplifier and a wireless communication device can be obtained.

  For example, when the frequency of the high frequency input signal Pin is 1.95 GHz and Hfe1 of the first transistor Q1 is 2, by setting the capacitor C2 to 1.5 pF and the resistance R2 to about 50Ω, the high frequency blocking choke coil L is 1 nH. The sufficient effect of the present embodiment can be obtained with the degree.

  Although the case where the wireless communication device 30 includes the signal transmission unit 33 and the signal reception unit 34 has been described here, the wireless communication device 30 may include only the signal transmission unit 33.

  FIG. 9 is a circuit diagram showing a configuration of a power amplifier using a bias circuit according to Embodiment 2 of the present invention.

  In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described.

  This embodiment differs from the first embodiment in that the voltage dividing circuit is a series circuit of transistors connected in feedback to each other.

  That is, as shown in FIG. 9, in the bias circuit 52 of the power amplifier 50, the voltage dividing circuit 53 has sixth and seventh transistors Q6 and Q7, and the emitter e6 of the sixth transistor Q6 is the base of the seventh transistor Q7. At b7, the collector c7 of the seventh transistor Q7 is feedback-connected to the base b6 of the sixth transistor Q6.

Further, the collector c6 is connected to the second power source, and the emitter e6 is grounded via the resistor R4.
The collector c7 of the seventh transistor Q7 is connected to the first power supply via the resistor R1, and the emitter e7 is grounded.

  In the bias circuit 52, when the control voltage V1 is applied to the base b6 of the sixth transistor Q6 at the start-up of the circuit, the sixth transistor Q6 is turned on, an emitter current flows through the resistor R4, and a voltage drop occurs at the resistor R4. Will occur.

  When the drop voltage of the resistor R4 is applied to the base b7 of the seventh transistor Q7, the seventh transistor Q7 is turned on, a collector current flows through the resistor R1, and a drop voltage is generated at the resistor R1.

  The voltage at the base b6 of the sixth transistor Q6 is lowered due to the drop voltage of the resistor R1, and the drop voltage of the resistor R4 is also lowered. Therefore, the currents flowing through the sixth and seventh transistors Q6 and Q7 are balanced, and the output terminal Vout Is the sum of the base-emitter voltages of the sixth and seventh transistors Q6 and Q7 (Vbe6 + Vbe7).

  Thereby, for example, if the control voltage V1 of the first power supply increases and the base-emitter voltage Vbe6 of the sixth transistor Q6 increases, the emitter current of the sixth transistor Q6 increases and the voltage drop due to the resistor R4 Will increase.

  Next, since the collector current of the seventh transistor Q7 increases and the voltage drop due to the resistor R1 increases, this acts in the direction of decreasing the base-emitter voltage Vbe6 of the sixth transistor Q6.

  That is, the resistance R4 causes a negative feedback action to suppress the fluctuation of the base-emitter voltage Vbe6 of the sixth transistor Q6, so that the bias voltage Vbi is stabilized against the fluctuation of the control voltage V1 of the first power supply. It is possible to make it.

  As described above, in this embodiment, since the voltage dividing circuit includes a series circuit of transistors that are feedback-connected to each other, even if the control voltage V1 of the first power supply fluctuates due to the negative feedback action of the resistor R4, There is an advantage that a stable bias voltage Vbi can be obtained.

  FIG. 10 is a circuit diagram showing a configuration of a power amplifier using a bias circuit according to Embodiment 3 of the present invention.

  In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described.

  This embodiment differs from the first embodiment in that the base b2 and the collector c2 of the second transistor Q2 are connected via a resistor.

  That is, as shown in FIG. 10, in the bias circuit 62 of the power amplifier 60, the base b2 and the collector c2 of the second transistor Q2 are connected via the resistor R5.

  By connecting the base b2 and the collector c2 via the resistor R5, the equivalent circuit of the second transistor Q2 can be regarded as a series circuit of a resistor and a diode.

  As a result, since the load impedance of the second transistor Q2 is increased by the contribution of the resistor R5 in addition to the diode, less current flows through the second transistor Q2 to obtain the same bias voltage Vbi. It is possible to reduce current consumption.

  As described above, in this embodiment, since the base b2 and the collector c2 of the second transistor Q2 are connected via the resistor R5, the current consumption of the second transistor Q2 can be reduced to obtain the same bias voltage Vbi. There are advantages.

  FIG. 11 is a circuit diagram showing a configuration of a power amplifier using a bias circuit according to Embodiment 4 of the present invention.

  In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described.

  This embodiment differs from the first embodiment in that the voltage dividing circuit is a series circuit of transistors that are feedback-connected to each other, and the base b2 and the collector c2 of the second transistor Q2 are connected via a resistor.

  That is, as shown in FIG. 11, the bias circuit 72 of the power amplifier 70 includes a voltage dividing circuit 53, and a second transistor Q2 in which a base b2 and a collector c2 are connected via a resistor R5.

  The voltage dividing circuit 53 can stabilize the bias voltage Vbi even when the control voltage V1 of the first power supply fluctuates, and reduce the current consumption of the second transistor Q2 to obtain the same bias voltage Vbi. It is.

  As described above, in this embodiment, the current consumption of the second transistor Q2 is sufficient to supply a stable bias voltage Vbi against fluctuations in the control voltage Vcon of the first power supply and to obtain the same bias voltage Vbi. There is an advantage that can be reduced.

  In the above-described embodiments, the case where the power amplifier 11 is a one-stage amplifier circuit using the transistor Q3 has been described. However, a multi-stage amplifier circuit using a plurality of bias circuits 12 may be used.

Further, although the case where the transistors Q1 to Q7 are InGaP / GaAs HBTs formed on a GaAs substrate has been described, SiGe / Si HBTs formed on a Si substrate or Si bipolar transistors may be used.
As the bias voltage, about 0.7 V is obtained for the SiGe / Si-based HBT, and about 0.6 V is obtained for the Si bipolar transistor.

  Further, the first transistor Q1 is not limited to the bipolar transistor, and even the field effect transistor can obtain the effects of the present invention.

1 is a circuit diagram showing a configuration of a power amplifier using a bias circuit according to Embodiment 1 of the present invention. The figure which shows typically the voltage-current characteristic of the 2nd transistor which concerns on Example 1 of this invention. 1 is a circuit diagram showing an equivalent circuit of a first transistor according to Embodiment 1 of the present invention. The figure which shows the relationship with the output electric power with the emitter DC potential of the 1st transistor which concerns on Example 1 of this invention. The figure which shows the relationship between the amplitude of the high frequency signal in the emitter of the 1st transistor which concerns on Example 1 of this invention, and output electric power. The figure which shows the relationship between the gain and output power of the power amplifier which concerns on Example 1 of this invention. The figure which shows the phase characteristic of the output electric power of the power amplifier which concerns on Example 1 of this invention. 1 is a block diagram showing a configuration of a wireless communication device using a power amplifier according to Embodiment 1 of the present invention. The circuit diagram which shows the structure of the power amplifier using the bias circuit which concerns on Example 2 of this invention. FIG. 6 is a circuit diagram showing a configuration of a power amplifier using a bias circuit according to Embodiment 3 of the present invention. The circuit diagram which shows the structure of the power amplifier using the bias circuit which concerns on Example 4 of this invention.

Explanation of symbols

10, 50, 60, 70 Power amplifier 11 Power amplifier 12, 52, 62, 72 Bias circuit 13, 53 Voltage divider 14 High-frequency signal generator 30 Radio communication device 31 Antenna 32 Switch 33 Signal transmitter 34 Signal receiver 35 Input signal processing means 36 First oscillation circuit 37 Modulation circuit 39 Low noise amplifier 40 Second transmission circuit 41 Mixer 42 Output signal processing circuits Q1, Q2, Q3, Q4, Q5, Q6, Q7 Transistors C1, C2, C3 Capacitor R1, R2, R3, R4, R5 Resistance L Coil

Claims (5)

A voltage dividing circuit connected to the first power source and dividing the first voltage to a predetermined value;
A capacitor having one end connected to the output end of the voltage dividing circuit and the other end grounded;
A first transistor having a base connected to the output terminal of the voltage dividing circuit via a resistor and a collector connected to a second power source;
A second transistor having a collector connected to the emitter of the first transistor, a collector connected to the base directly or via a resistor, and an emitter grounded;
A bias circuit comprising: A voltage dividing circuit connected to the first power source and dividing the first voltage to a predetermined value;
A capacitor having one end connected to the output end of the voltage dividing circuit and the other end grounded;
A first transistor having a base connected to the output terminal of the voltage dividing circuit via a resistor and a collector connected to a second power source;
A second transistor having a collector connected to the emitter of the first transistor, a collector connected to the base directly or via a resistor, and an emitter grounded;
A bias circuit comprising:
A power amplifier for amplifying a high-frequency signal, comprising a third transistor having a base connected to the emitter of the first transistor via a coil, a collector connected to a third power source, and an emitter grounded;
A power amplifier comprising:   The voltage dividing circuit is a series circuit of fourth and fifth transistors each having a collector and a base connected to each other, the collector of the fourth transistor is connected to the first power supply, and the emitter of the fifth transistor is grounded. The power amplifier according to claim 2. The voltage dividing circuit includes sixth and seventh transistors. In the sixth transistor, a collector is connected to the second power source, a base is connected to the collector of the seventh transistor, and an emitter is connected via a resistor. Grounded
3. The power amplifier according to claim 2, wherein in the seventh transistor, a collector is connected to the first power source, a base is connected to an emitter of the sixth transistor, and an emitter is grounded. Signal modulating means for modulating a high-frequency signal based on an input signal input from the outside;
A voltage dividing circuit which is connected to a first power source and divides the first voltage into a predetermined value; a capacitor whose one end is connected to an output end of the voltage dividing circuit and whose other end is grounded; and the voltage dividing circuit And a collector connected to the emitter of the first transistor, and the collector and the base are connected directly or via a resistor. A bias circuit including a second transistor connected to each other and having an emitter grounded;
A power amplifier for amplifying the modulated high-frequency signal, comprising a third transistor having a base connected to the emitter of the first transistor via a coil, a collector connected to a third power source, and an emitter grounded; ,
An antenna for transmitting the amplified signal;
A wireless communication apparatus comprising:

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