CN107134985B - Wireless communication system - Google Patents
Wireless communication system Download PDFInfo
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- CN107134985B CN107134985B CN201710365711.2A CN201710365711A CN107134985B CN 107134985 B CN107134985 B CN 107134985B CN 201710365711 A CN201710365711 A CN 201710365711A CN 107134985 B CN107134985 B CN 107134985B
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- 239000003990 capacitor Substances 0.000 claims abstract description 25
- 230000003321 amplification Effects 0.000 abstract description 8
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 8
- 238000006243 chemical reaction Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 230000005669 field effect Effects 0.000 description 7
- 230000001133 acceleration Effects 0.000 description 2
- 238000013507 mapping Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
- H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
A wireless communication system comprising a high frequency power amplification circuit, the high frequency power amplification circuit comprising a high frequency amplifier, the high frequency amplifier comprising: the circuit comprises a first transistor, a second transistor, a first high-frequency choke coil, a second high-frequency choke coil, a first bias circuit, a second bias circuit and a capacitor, wherein the first bias circuit is connected to the base of the first transistor and used for providing bias current for the base of the first transistor according to control voltage; an emitter of the first transistor is grounded, and a collector is connected to a first power supply via a first high-frequency choke coil; the collector of the first transistor is also connected to the emitter of the second transistor, the base of the second transistor is grounded through a capacitor, the collector is connected to a second power supply through a second high-frequency choke coil, and a second bias circuit is connected to the base of the second transistor and used for providing bias current for the base of the second transistor. The wireless communication system provided by the invention reduces the distortion of the input high-frequency signal and increases the output power.
Description
Technical Field
The present invention relates to a wireless communication system, and more particularly, to a communication system for use in a mobile phone.
Background
Generally, in an amplitude modulated signal, particularly in multilevel modulation such as QAM (quadrature amplitude modulation), a high frequency power amplifier needs to be disposed in a transmission circuit for transmitting power to an antenna, and the high frequency power amplifier needs to linearly amplify an input high frequency modulated signal in order to keep the signal from being distorted. Therefore, a high frequency power amplifier used as a final stage of, for example, a mobile phone is generally operated in a class a or class ab state. However, in order to overcome the technical problem of using a single-tube amplifier with low output power, the prior art provides a cascode amplifier, which shares a bias circuit and causes distortion to the input signal.
Disclosure of Invention
To overcome the disadvantages of the prior art, it is an object of the present invention to provide a wireless communication system that reduces distortion of an input signal and increases output power.
To achieve the object, a wireless communication system includes a high-frequency power amplifying circuit including a high-frequency amplifier, wherein the high-frequency amplifier includes: the circuit comprises a first transistor, a second transistor, a first high-frequency choke coil, a second high-frequency choke coil, a first bias circuit, a second bias circuit and a capacitor, wherein the first bias circuit is connected to the base of the first transistor and used for providing bias current for the base of the first transistor according to control voltage; an emitter of the first transistor is grounded, and a collector is connected to a first power supply via a first high-frequency choke coil; the collector of the first transistor is also connected to the emitter of the second transistor, the base of the second transistor is grounded through a capacitor, the collector is connected to a second power supply through a second high-frequency choke coil, and a second bias circuit is connected to the base of the second transistor and used for supplying bias current to the base of the second transistor.
Preferably, the first bias circuit includes a third transistor having a collector connected to the first power supply, an emitter connected to a base of the first transistor through a first resistor and a high-frequency choke coil in this order, the base being connected to the first reference voltage.
Preferably, the wireless communication system further comprises a power supply circuit including a second resistor, a PN junction, and a third resistor connected in series and parallel in this order between the control voltage and the ground, the first bias circuit being supplied with a reference voltage from a node where the second resistor and the PN junction are connected.
Preferably, the PN junction is configured by a diode.
Preferably, the PN junction is configured by a transistor.
Compared with the prior art, the wireless communication system provided by the invention adopts the following amplifiers, and comprises: the circuit comprises a first transistor, a second transistor, a first high-frequency choke coil, a second high-frequency choke coil, a first bias circuit, a second bias circuit and a capacitor, wherein the first bias circuit is connected to the base of the first transistor and used for providing bias current for the base of the first transistor according to control voltage; the emitter of the first transistor is grounded, and the collector is connected to a first power supply through a first high-frequency choke coil; the collector of the first transistor is also connected with the emitter of the second transistor, the base of the second transistor is grounded through a capacitor, the collector is connected with the second power supply through a second high-frequency choke coil, and the second bias circuit is connected with the base of the second transistor and used for providing bias current for the base of the second transistor, so that the wireless communication system, particularly the transmitter, provided by the invention reduces the deformation of signals to be transmitted and increases the output power.
Drawings
Fig. 1 is a block diagram of a wireless communication system according to a first embodiment of the present invention;
fig. 2 is a circuit diagram of a high-frequency power amplifying circuit provided by a first embodiment of the present invention;
fig. 3 is a circuit diagram of a high-frequency power amplifying circuit provided by a second embodiment of the present invention;
fig. 4 is a circuit diagram of a high-frequency power amplifying circuit provided by a third embodiment of the present invention;
fig. 5 is a circuit diagram of a high-frequency power amplifying circuit according to a fourth embodiment of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that unless otherwise explicitly stated or limited, the terms "mounted" and "connected" are to be interpreted broadly, and may be, for example, directly connected to each other, indirectly connected to each other through an intermediate medium, or connected to each other through the internal communication of two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
First embodiment
Fig. 1 is a block diagram of a communication system according to a first embodiment of the present invention. As shown in FIG. 1, the first embodiment of the present inventionAn embodiment provides a communication system comprising a transmitter and a receiver, the transmitter comprising: the electromagnetic wave exciter comprises an exciter, a power amplification circuit used for carrying out power amplification on a signal to be sent by the exciter, an output filter used for matching the output impedance of the power amplification circuit with the input impedance of a transmitting antenna, and the transmitting antenna used for converting an electric signal subjected to power amplification into a magnetic signal and transmitting the magnetic signal to a space. The receiver includes: the space magnetic signal receiving device comprises a receiving antenna used for converting space magnetic signals into electric signals, a small signal amplifier used for amplifying the electric signals received by the receiving antenna, a first mixer used for carrying out down-conversion on the signals amplified by the small signal amplifier and local oscillation signals generated by a first local oscillator to form intermediate frequency signals, an analog-to-digital converter used for carrying out analog-to-digital conversion on the intermediate frequency signals to form data signals, an OFDM demodulator used for removing time intervals in the data signals and then carrying out serial-parallel conversion, FFT conversion and parallel-serial conversion in sequence, and a symbol inverse mapper used for carrying out symbol inverse mapping on the signals output by the OFDM demodulator. The exciter comprises a symbol mapper, an OFDM modulator, a D/A conversion circuit, a mixer, a local oscillator and a preamplifier, wherein the symbol mapper is used for grouping input serial binary code streams into data symbols and mapping the data symbols into complex data sequences, the OFDM modulator is used for carrying out serial-to-parallel conversion on the complex data sequences and modulating the complex data sequences onto K subcarriers, and data on the K subcarriers are marked as X 0 ，X 0 ...，X K-1 (ii) a Then IFFT transform is carried out to form parallel time domain data x 0 ，x 1 ，...，x K-1 I.e. x 0 ，x 1 ，...，x K-1 For one OFDM symbol, carrying out parallel-to-serial conversion on the parallel time domain data to form a serial OFDM symbol, and then inserting a guard time interval between every two OFDM symbols to form an OFDM code element; D/A conversion circuit converts the data stream into analog signal u i (ii) a The second mixer is used for mixing the analog signal u i And a local oscillator signal u generated by a second local oscillator 0 Up-conversion is carried out to form a signal u to be transmitted h The preamplifier being intended to transmit a signal u h Amplifying and sending to the final power amplifierAnd amplifying the line power.
Still as shown in fig. 1, the binary code stream input at the transmitting end is grouped to form data symbols, the data symbols are mapped by the symbol mapper to form complex data sequences, and the complex data sequences are transformed into K parallel low-speed data streams X 0 ，X 0 ，...，X K-1 (ii) a Performing IFFT to obtain a time-domain sample value:
wherein m is a discrete point of a frequency domain, and k is a discrete point of a time domain.
At the receiving end, the time domain data formed by the serial-parallel conversion of the signals without the guard time interval is y 0 、y 1 、...，y K-1 And FFT is carried out on the frequency domain data to obtain a frequency domain value:
fig. 2 is a circuit diagram of a high-frequency power amplifying circuit according to a first embodiment of the present invention, and as shown IN fig. 2, the high-frequency power amplifying circuit according to the first embodiment of the present invention includes a high-frequency signal input terminal IN, an input matching network 300, a high-frequency amplifier 500, an output matching network 400, a high-frequency signal output terminal OUT, a first bias circuit 100, and a second bias circuit, wherein the high-frequency amplifier 500 includes: the first bias circuit 100 is connected to the base of the first transistor T1 and used for providing bias current for the base of the first transistor T1 according to a control voltage Vcon 1; the emitter of the first transistor T1 is grounded, and the collector is connected to a first power supply Vcc1 via a first high-frequency choke coil L1; the collector of the first transistor T1 is further connected to the emitter of the second transistor T2, the base of the second transistor T2 is grounded via a capacitor C1, the collector is connected to a second power supply Vcc2 via a second high-frequency choke coil L2, and a second bias circuit is connected to the base of the second transistor T2 for supplying a bias current to the base of the second transistor T2, preferably, the second bias circuit is composed of a resistor R2, a first end of the resistor R2 is connected to the second power supply Vcc2, and a second end is connected to the base of the second transistor T2. Preferably, the first power supply Vcc1 is also grounded through a filter capacitor C3. The second power supply Vcc2 is also grounded through a filter capacitor C4.
The bias circuit 100 for supplying a bias voltage to the transistor T1 in accordance with a first reference voltage includes a transistor T11, a collector of the transistor T11 being connected to a power supply Vcc1, and an emitter thereof being connected to a base of the transistor T1 via a resistor R11 and a high-frequency choke coil L11 in this order. The first reference voltage is provided by a first power supply circuit 110, which is used for controlling the offset of the transistor T1, the first power supply circuit 110 comprises a resistor R14, a transistor T12 and a transistor T13, the transistor T12 is connected in a diode structure, i.e. the collector and the base of the transistor T12 are short-circuited; the transistor T13 is connected in a diode configuration, i.e., the collector and base of the transistor T13 are short-circuited. The resistor R14 has a first terminal connected to the control voltage Vcon1 and a second terminal connected to the base of the transistor T12, and the transistor T12 and the transistor T13 are connected in series and connected between the resistor R14 and the overshoot control circuit. The control signal Vcon1 is used to control the start and stop of the bias circuit 100. In the first power supply circuit 110, the resistor R14 and the transistors T12 and T13 are provided to reduce modulation accuracy due to temperature deviation when temperature changes, and these components perform a function of temperature compensation. In the invention, the node of the resistor R11 and the high-frequency choke coil L11 which are connected in series is also grounded through a bypass capacitor C12.
During the rise of the control voltage Vcon1, the speed-up circuit is used to temporarily increase the reference voltage output from the power supply circuit 110, thereby increasing the amount of increase to the transistor T1 by the bias circuit 100. The acceleration circuit comprises a capacitor C11, a time constant control circuit, a discharge circuit and an overshoot control circuit, wherein the first end of the capacitor C11 is connected to a control voltage Vcon1, the second end of the capacitor C11 is connected to the time constant control circuit, and the discharge circuit is connected with the capacitor C11 in parallel. The discharge circuit includes a transistor T16 having a gate connected to ground, a source connected to the base of the transistor T14, and a drain connected to the control voltage Vcon1. The time constant control circuit comprises a transistor T14, a resistor R12 and a transistor T15, wherein the base electrode of the transistor T14 is connected to the second end of the capacitor C11, the collector electrode of the transistor T14 is connected to the voltage Vcc1, and the emitter electrode of the transistor T is connected to the first end of the resistor R12; the second end of the resistor R12 is connected to the base of the transistor T15; the transistor T15 has a collector connected to the voltage Vcon1 and an emitter connected to the ground via the resistor R13. The time constant control circuit is used to determine the time constant for charging and discharging the capacitor C11. The overshoot circuit is used to determine the amount of the reference voltage output from the power supply circuit 110, which temporarily increases according to the amount of discharge of the capacitor C11. For example, the overshoot circuit may be a circuit including only resistor R13, and the first terminal of resistor R13 is connected to ground and the second terminal is connected to power supply circuit 110.
IN the high frequency power amplifier shown IN fig. 2, a high frequency signal is input from an input terminal IN, then input to a base of a cascode including a transistor T1 through impedance matching by an input matching network 300, input to an emitter of the cascode including a transistor T2 after amplification, output from a collector of the transistor T2 through power amplification, and then impedance matched to an antenna (not shown IN fig. 2) through an output matching network 400 to an output terminal OUT.
While the control voltage Vcon1 is rising, the capacitor C11 is charged, and the charging current flows in the resistor R13 from the base to the emitter of the transistor 14, the resistor R12, the base to the emitter of the transistor T15, and so on. The base potential of the bias transistor T11 temporarily rises to raise the base bias voltage of the amplifying transistor T1, thereby temporarily raising the gain of the transistor T1. During the fall of the control voltage Vcon1, the charge on the capacitor C11 is discharged by the transistor T16. The invention further restrains the reduction of modulation precision caused by the heat generated by the amplifier due to the configuration of the accelerating circuit.
Second embodiment
A communication system according to a second embodiment of the present invention is similar to that shown in fig. 1, except that only a high frequency power amplifier circuit is provided. A high-frequency power amplifying circuit provided by a second embodiment of the present invention will be described with reference to fig. 3. As shown in fig. 3, the high-frequency power amplifying circuit provided by the second embodiment of the present invention differs from the high-frequency power amplifying circuit provided by the first embodiment only in that the configuration of the first power supply circuit for supplying the reference voltage to the first bias circuit differs, and in the second embodiment, the first power supply circuit 110 includes a resistor R14, a diode D1, and a diode D2. The resistor R14 has a first end connected to the control voltage Vcon1, a second end connected to the anode of the diode D1, and the cathode of the diode D1 connected to ground through the overshoot circuit. The control signal Vcon1 is used to control the start and stop of the bias circuit 100. In the first power supply circuit 110, the resistor R14, the diode D1, and the diode D2 are provided in order to suppress the influence of temperature on the modulation accuracy.
Third embodiment
The third embodiment of the present invention provides a communication system having the same block diagram as that of fig. 1, except for a high-frequency power amplifier circuit. A high-frequency power amplifying circuit according to a third embodiment of the present invention will be described with reference to fig. 4. As shown in fig. 4, the high-frequency power amplifying circuit according to the third embodiment of the present invention is different from the high-frequency power amplifying circuit according to the first embodiment only in that a second bias circuit is different, and the bias circuit for supplying a bias voltage to the transistor T2 according to the second embodiment includes a transistor T21, a collector of the transistor T21 is connected to the second power supply Vcc2, and an emitter is connected to a base of the transistor T2 through a resistor R21 and a high-frequency choke coil L21 in this order. The second reference voltage is provided by a second power supply circuit 210, which is used for controlling the offset of the transistor T2, the second power supply circuit 210 comprises a resistor R24, a transistor T22 and a transistor T23, the transistor T22 is connected in a diode structure, that is, the collector and the base of the transistor T22 are connected in a short circuit; the transistor T23 is connected in a diode configuration, i.e., the collector and base of the transistor T23 are short-circuited. The resistor R24 has a first terminal connected to the control voltage Vcon2 and a second terminal connected to the base of the transistor T22, and the transistor T22 and the transistor T23 are connected in series and connected between the resistor R24 and ground. The control signal Vcon2 is used to control the start and stop of the bias circuit 200. In the second power supply circuit 210, the resistor R24 and the transistors T22 and T23 are provided to reduce modulation accuracy due to temperature bias when temperature changes, and these components function as temperature compensation.
Fourth embodiment
A block diagram of a communication system according to a fourth embodiment of the present invention is the same as that shown in fig. 1, except that a high-frequency power amplifier circuit is used. A high-frequency power amplifying circuit according to a fourth embodiment of the present invention will be described with reference to fig. 5, and as shown IN fig. 5, the high-frequency power amplifying circuit according to the fourth embodiment of the present invention includes a high-frequency signal input terminal IN, an input matching network 300, an amplifier 500, an output matching network 400, a high-frequency signal output terminal OUT, a first bias circuit 100, and a second bias circuit 200, wherein the amplifier 500 includes: a first field effect transistor T3, a second field effect transistor T4, a first high-frequency choke L1, a second high-frequency choke L2 and a capacitor C1, wherein the first bias circuit 100 is connected to the gate of the first transistor T3 and is configured to provide a gate bias voltage to the first field effect transistor T3 according to a control voltage; the source electrode of the first field effect transistor T3 is grounded, and the drain electrode is connected to a first power supply Vcc1 through a first high-frequency choking coil L1; the drain of the first fet T3 is further connected to the source of the second fet T2, the gate of the second fet T2 is grounded via the capacitor C1, the drain is connected to the second power supply Vcc2 via the second high-frequency choke L2, the second bias circuit 210 is configured to provide a bias voltage to the gate of the second fet T4, and includes a fet T26, a resistor R21 and a resistor R25, the drain of the fet T26 is connected to the second power supply Vcc2, and the source is connected to the ground via the resistor R21 and the resistor R25 in sequence. A node at which the resistor R21 and the resistor R25 are connected in series is connected to the gate of the second field effect transistor T4 via the high-frequency choke coil L22. A bypass capacitor C22 is connected in parallel with two ends of the resistor R25.
The second reference voltage for supplying to the gate of the fet T26 is supplied from the second power supply circuit 210 for controlling the offset amount of the fet T4, and the configuration of the second power supply circuit 210 is the same as that of the third embodiment, and will not be described again here. The first bias circuit 110 is configured to provide a bias voltage to the gate of the first fet T3, and includes a fet T16, a resistor R11, and a resistor R15, where the drain of the fet 16 is connected to the first power supply Vcc1, and the source is connected to the ground through the resistor R11 and the resistor R15 in sequence. A node at which the resistor R11 and the resistor R15 are connected in series is connected to the gate of the first field-effect transistor T3 via the high-frequency choke coil L11. The resistor R15 is connected in parallel with the filter capacitor C12.
The first reference voltage for supplying to the gate of the field effect transistor T16 is supplied from the first power supply circuit 110, and the configuration thereof is the same as that of the first power supply circuit in the first embodiment, and will not be described again here. The acceleration circuit provided by the fourth embodiment is also the same as that provided by the first embodiment, and will not be repeated here.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (5)
1. A wireless communication system comprising a high-frequency power amplifying circuit including a high-frequency amplifier, characterized in that the high-frequency amplifier comprises: the circuit comprises a first transistor, a second transistor, a first high-frequency choke coil, a second high-frequency choke coil, a first bias circuit, a second bias circuit and a capacitor, wherein the first bias circuit is connected to the base of the first transistor and used for providing bias current for the base of the first transistor according to control voltage; an emitter of the first transistor is grounded, and a collector is connected to a first power supply via a first high-frequency choke coil; the collector of the first transistor is also connected to the emitter of the second transistor, the base of the second transistor is grounded through a capacitor, the collector is connected to a second power supply through a second high-frequency choke coil, and a second bias circuit is connected to the base of the second transistor and used for supplying bias current to the base of the second transistor.
2. The wireless communication system according to claim 1, wherein the first bias circuit includes a third transistor, a collector of the third transistor is connected to the first power supply, an emitter of the third transistor is connected to a base of the first transistor through a first resistor and a high-frequency choke coil in this order, and the base is connected to the first reference voltage.
3. The wireless communication system of claim 2, further comprising a power supply circuit comprising a second resistor, a PN junction, and a third resistor connected in series and in communication between the control voltage and ground, wherein the first bias circuit is provided with a reference voltage from a node at which the second resistor and the PN junction are connected.
4. The wireless communication system of claim 3, wherein the PN junction is configured by a diode.
5. The wireless communication system of claim 3, wherein the PN junction is configured by a transistor.
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| CN1801606A (en) * | 2003-09-24 | 2006-07-12 | 松下电器产业株式会社 | Amplifier and frequency converter |
| JP2006333107A (en) * | 2005-05-26 | 2006-12-07 | Toshiba Corp | Bias circuit and power amplifier using the same, and radio communication device |
| CN103023440A (en) * | 2012-12-20 | 2013-04-03 | 中国科学院微电子研究所 | Circuit for improving linearity of power amplifier |
| JP2014022957A (en) * | 2012-07-19 | 2014-02-03 | Renesas Electronics Corp | Amplification circuit and amplification element |
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2017
- 2017-05-22 CN CN201710365711.2A patent/CN107134985B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1801606A (en) * | 2003-09-24 | 2006-07-12 | 松下电器产业株式会社 | Amplifier and frequency converter |
| JP2006333107A (en) * | 2005-05-26 | 2006-12-07 | Toshiba Corp | Bias circuit and power amplifier using the same, and radio communication device |
| JP2014022957A (en) * | 2012-07-19 | 2014-02-03 | Renesas Electronics Corp | Amplification circuit and amplification element |
| CN103023440A (en) * | 2012-12-20 | 2013-04-03 | 中国科学院微电子研究所 | Circuit for improving linearity of power amplifier |
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