JP2007074072A - High-frequency amplifying circuit, and transmitter, receiver, and transmitter receiver using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a high-frequency amplifying circuit which has small deterioration in output electric power at the time of intense input, is stable against a thermal runaway, and facilitates input matching, and a transmitter, a receiver, and a transmitter receiver using the same that have a wide dynamic range and superior receiving performance and transmitting performance and are stable by using the high-frequency amplifying circuit for functions of transmission and reception. <P>SOLUTION: Disclosed is the high-frequency amplifying circuit comprising a bias circuit composed of a current mirror circuit, an emitter follower circuit having a transistor for biasing, and a common emitter amplifying circuit having a transistor for amplification. The base of the transistor 45 for biasing is grounded by a grounding capacitor 101, the emitter of the transistor 45 for biasing is connected to the emitter of the transistor 5 for amplification through a grounding resistance 104 and a grounding capacitor 105, and the emitter of the transistor 43 for biasing is connected to be grounded. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technology of a high-frequency amplifier circuit, and in particular, a transmitter / receiver such as a cellular phone and a wireless LAN, a receiver such as a TV, CATV, satellite broadcast, and satellite communication, and a low-noise amplifier circuit and power amplifier used for them. The present invention relates to a technology effective when applied to a circuit.

  As a technique studied by the present inventor, for example, a conventional high-frequency amplifier circuit having a configuration as shown in FIG. 9 can be considered.

  The high-frequency amplifier circuit shown in FIG. 9 is the final part of a transmitter for transmitting a modulated radio frequency signal (RF signal) to an access point or another personal computer equipped with the wireless LAN system in a wireless LAN system. An example of a high-frequency amplifier circuit that performs power amplification used in the stage is shown. An input signal is an RF signal having a frequency of 5 GHz, and a power supply voltage is 3.3V.

  9 includes an RF signal input terminal 1, an RF signal output terminal 2, a power supply terminal 3, a reference voltage terminal 4, an amplifying transistor 5, grounding capacitors 6 and 7, and an input matching circuit 20. An output matching circuit 30, a bias circuit 40, a bias inductor 8, and a bias resistor 9. The amplifying transistor 5 has an emitter grounded, a base connected to the RF signal input terminal 1 via the input matching circuit 20, and a bias resistor 9 and a bias inductor 8 connected to the bias circuit 40. Are connected to the RF signal output terminal 2 and the power supply terminal 3 via the output matching circuit 30.

  Further, the bias circuit 40 includes bias transistors 43, 44 and 45 and current adjustment resistors 41 and 42. The bias transistor 43 has an emitter grounded, a base connected to the emitter of the bias transistor 44, a collector connected to the base of the bias transistor 44, and connected to the reference voltage terminal 4 via the current adjustment resistors 42 and 41. In addition, the connection point of the current adjustment resistors 41 and 42 is connected to the base of the biasing transistor 45. The power supply terminal 3 is connected to the collector of the bias transistor 44 and the collector of the bias transistor 45, and the emitter of the bias transistor 45 is connected to the base of the amplifying transistor 5 via the bias inductor 8 and the bias resistor 9. By connecting, a bias voltage is applied to the base of the amplifying transistor 5.

  The input matching circuit 20 includes capacitors 21 and 22 and an inductor 23, and impedance matching between the base of the amplifying transistor 5 and the RF signal source impedance is achieved. The output matching circuit 30 includes inductors 31 and 33 and a capacitor 32. The impedance matching between the collector of the amplifying transistor 5 and the load impedance is performed, and the voltage of the power supply terminal 3 is also supplied to the collector of the amplifying transistor 5.

  The above high frequency amplifier circuit amplifies the 5 GHz band RF signal input to the RF signal input terminal 1 by the amplifying transistor 5 and outputs the amplified signal to the RF signal output terminal 2. At this time, the bias circuit 40 that supplies a bias voltage to the amplifying transistor 5 detects bias current variations caused by changes in the voltage between the base and the emitter of the amplifying transistor 5 due to temperature changes. The temperature dependence of the collector current of the amplifying transistor 5 is suppressed (for example, non-current) by canceling out the fluctuation caused by the temperature change of the voltage between the base and the emitter of the emitter follower circuit of the bias transistor 45 and the current mirror circuit constituted by Patent Document 1).

  Further, the current mirror circuit and the amplifying transistor are connected via a buffer by an emitter follower circuit, so that the driving capability of the bias circuit at the time of high output in the high frequency amplifying circuit is prevented.

The collector current flowing through the amplifying transistor 5 can be adjusted by the values of the current adjusting resistors 41 and 42, and the connection between the base of the amplifying transistor 5 and the bias circuit 40 is a gain due to the influence of the impedance of the bias circuit 40. In order to suppress the decrease in the voltage, a bias inductor 8 and a bias resistor 9 are provided.
The Institute of Electronics, Information and Communication Engineers IEICE Technical Report "Efficiency improvement method using distortion cancellation in 2-stage power amplifier HBT MMIC for W-CDMA", ED2001-207, FIG.

  By the way, in the high-frequency amplifier circuit shown in the above prior art, when a strong RF signal is input such that the base and emitter of the amplifier transistor are turned on as a diode, the input RF signal is clipped at a positive amplitude. Therefore, the average value of the base-emitter voltage decreases, and the base current from the bias circuit increases. The collector current increases as the base current increases, and the output power is not shorted by increasing the collector current when the input is strong (also called strong signal level input or strong level input). . However, in the prior art of the high frequency amplifier circuit shown in FIG. 9, when the base current increases at the time of strong input, the voltage drop due to the bias resistor 9 becomes large, so that the bias current to the amplifying transistor 5 is insufficient. However, there is a problem that input / output characteristics deteriorate and sufficient output power cannot be obtained.

  For this reason, when the high-frequency amplifier circuit shown in FIG. 9 is used in the first-stage low-noise amplifier circuit of the receiver, the output waveform is distorted at the time of strong input, and a sufficient dynamic range cannot be obtained. When used in the final stage power amplifier circuit, sufficient transmission power cannot be obtained.

  Furthermore, when the conventional technology of the high frequency amplifier circuit shown in FIG. 9 is used for the power amplifier circuit at the final stage of the transmitter, the power amplifier circuit is required to have a strong input and a large output operation. At the time of input, when the collector current increases as the base current of the amplifying transistor increases, the amplifying transistor generates heat. Due to the heat generated by the amplifying transistor, the voltage between the base and the emitter is lowered, so that the base current further increases. Due to this increase, the collector current further increases, and accordingly, the transistor generates heat.

  When the above operation is repeated, there is a problem that the collector current increases endlessly, and the amplifying transistor is likely to malfunction, or in the worst case, thermal runaway is likely to occur.

  In the power amplifier circuit, since it is necessary to increase the transistor size of the amplifying transistor to increase the output, a plurality of small transistors are connected in parallel to increase the transistor size. For this reason, thermal runaway is considered to cause a malfunction due to partial thermal runaway in the central portion of the transistor array because the central portion of the transistors connected in parallel at the time of high output tends to generate heat.

  Furthermore, in the power amplifier circuit, since the transistor size of the amplifying transistor is increased, the base resistance of the amplifying transistor is reduced, and the junction capacitance between the base and the emitter and between the base and the collector is increased, so that the input impedance is reduced. It drops considerably. For this reason, when the transistor size of the amplifying transistor is increased in the prior art of the high-frequency amplifier circuit shown in FIG. 9, impedance matching in the input matching circuit 20 is difficult to achieve, the input matching circuit becomes complicated, and the number of parts increases. There are challenges.

  Accordingly, an object of the present invention is to obtain a high-frequency amplifier circuit that is less susceptible to thermal runaway and has a low input power deterioration at the time of strong input, and that is easy to obtain input matching. It is to provide a stable receiver and transmitter having a wide dynamic range and excellent transmission performance, and a transmitter / receiver.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In order to achieve the above object, the present invention has the following features as means for solving the above-mentioned problem that sufficient output power cannot be obtained at the time of strong input. Here, in order to make the characteristics of the present invention easier to understand, the description will be made in comparison with the high frequency amplifier circuit shown in the prior art of FIG.

  In the present invention, the means for solving the above-described problem is configured such that the base of the biasing transistor 45 is grounded by a capacitor and the emitter of the biasing transistor 45 is grounded by a series connection of a resistor and a capacitor.

  In the high frequency amplifier circuit shown in the prior art of FIG. 9, when a strong RF signal is input, the base and emitter of the amplifying transistor 5 are turned on when the input RF signal has a positive amplitude. The voltage between the base and the emitter is lowered, and the increase in the base current due to this drop causes a large voltage drop in the bias resistor 9, which leads to a shortage of output power. However, by adopting a configuration in which the base of the bias transistor 45 is grounded by a capacitor, the input RF signal is applied to the emitter of the bias transistor 45 via the bias resistor 9 and the bias inductor 8 at the time of strong input. By leaking, the RF signal input between the emitter and the base of the biasing transistor 45 is opposite to that between the base and the emitter of the amplifying transistor 5 and is turned on. Therefore, the potential of the emitter of the biasing transistor 45 rises with reference to the base potential of the biasing transistor 45.

  Therefore, since the decrease in the voltage between the base and the emitter of the amplifying transistor 5 can be canceled by the increase in the potential of the emitter of the biasing transistor 45 at the time of strong input, the shortage of output power at the time of strong input can be improved. .

  The rise in the potential of the emitter of the biasing transistor 45 can be adjusted by the grounding constant by the series connection of the resistor and the capacitor added to the emitter of the biasing transistor 45, so that these constants are optimized. As a result, the output of the high-frequency amplifier circuit can be increased.

  Next, as a means for solving the problem that thermal runaway is likely to occur when the above-described high-frequency amplifier circuit is used for a power amplifier circuit, it has the following characteristics. In order to make the characteristics of the present invention easier to understand, description will be made in comparison with the high frequency amplifier circuit shown in the prior art of FIG.

  In the present invention, the first means for solving the problem that the thermal runaway is likely to occur is that the emitter of the biasing transistor 45 is connected to the emitter of the amplifying transistor 5 through a series connection of a resistor and a capacitor. The bias circuit 40 is also grounded after being commonly connected to the emitter of the amplifying transistor 5.

  By adopting such a configuration, for example, when the series connection body of the resistor and the capacitor added to the emitter of the amplifying transistor 5 and the emitter of the biasing transistor 45 is separately grounded, the wiring of the substrate actually Although a small inductance component and a small resistance component are included, sufficient grounding cannot be performed. However, the grounding of the series connection body of the resistor and the capacitor and the grounding of the bias circuit should be connected to the emitter of the amplifying transistor 5 in common. Thus, the series connection of the resistor and the capacitor as viewed from the emitter of the amplifying transistor 5 and the bias circuit can be sufficiently grounded. Since the grounding can be sufficiently performed in this way, the harmonic component of the RF signal generated in the amplifying transistor 5 can be sufficiently attenuated by the grounding of the series connection body of the resistor and the capacitor. Therefore, it is possible to suppress generation of an unnecessary bias voltage caused by leaking into the bias circuit. For this reason, thermal runaway caused by this unnecessary bias voltage can be suppressed.

  Further, in the present invention, a second means for solving the problem that the thermal runaway is likely to occur is configured such that a plurality of small transistors are connected in parallel to the amplifying transistor 5, and the amplifying transistor 5 is The grounding of the emitters of the plurality of transistors is performed independently.

  An operation obtained by such a configuration will be described below. When a strong input level RF signal is input, the transistor generates heat due to an increase in the collector current of the amplifying transistor 5, and in particular, the temperature of the central portion of the transistors arranged in parallel increases, so that the central portion of the transistor The collector current increases. Actually, since a minute resistance component and a minute inductance component due to the wiring of the substrate are included, the emitter potential rises due to these voltage drops as the collector current increases. At this time, if the emitters of the transistors arranged in parallel are connected in common and grounded, the emitter potential of the transistors in the center is increased, and the emitters in the peripheral parts of the transistors connected in parallel are also connected in common. As a result, negative feedback is applied, and the collector current of the peripheral transistors decreases. Therefore, when the amplifying transistor 5 is composed of a plurality of transistors connected in parallel, a current flows only in the central part of the transistor and a current does not flow in the peripheral part at the time of strong input, so that the input RF signal level is larger than a certain level. Then, a thermal runaway occurs in which the collector current reaches its peak and the output power is saturated. For this reason, as described above, by independently grounding the emitters of a plurality of transistors, the influence of negative feedback due to an increase in the emitter potential due to an increase in the collector current at the center of the transistor is eliminated. When the value becomes larger than a certain level, it is possible to suppress thermal runaway such that the output power is saturated.

  Next, as means for solving the problem that it is difficult to achieve input matching when the transistor size of the amplification transistor, which is the problem described above, is increased, the following characteristics are provided. Here, in order to make the characteristics of the present invention easier to understand, the description will be made in comparison with the high frequency amplifier circuit shown in the prior art of FIG.

  In the present invention, the means for solving the above-described problem is configured such that a bias inductor is connected to the base of the amplifying transistor 5 and then connected to the bias circuit 40 via a bias resistor.

  An operation obtained by such a configuration will be described below. Since the bias inductor has a larger parasitic capacitance between the winding of the inductor and the ground than the resistance element, the base of the amplifying transistor 5 is usually connected to the bias resistor 9 as in the prior art shown in FIG. A bias inductor 8 is connected so that the influence of the parasitic component of the bias inductor 8 does not reach the base of the amplifying transistor 5. However, when the transistor size is increased for higher output as in the case of a power amplifier circuit, the input impedance is low, making input matching difficult. For this reason, as described above, when the transistor size of the amplifying transistor 5 is large, by connecting a bias inductor to the base, the parasitic capacitance of the bias inductor enters between the base and the ground, thereby achieving input matching. Can be made easier.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, it is possible to obtain a high-frequency amplifier circuit that has little deterioration in output power when a strong signal level is input, is stable against thermal runaway, and is easy to obtain input matching. By using the function, it is possible to obtain a stable receiver and transmitter, and a transmitter / receiver having a wide dynamic range and excellent transmission performance.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Outline of the embodiment of the present invention)
In the embodiment of the present invention, for the purpose of suppressing deterioration of output power when a strong signal level is input, the output power is improved by adopting a configuration that suppresses a decrease in bias voltage when inputting a strong signal level. In addition, thermal runaway due to an increase in collector current at the time of strong signal level input is made simple and easy to integrate, for example, by sharing the ground of the emitter of the amplifying transistor and the bias circuit. Each embodiment will be specifically described below.

(First embodiment)
FIG. 1 is a circuit diagram showing a high-frequency amplifier circuit according to a first embodiment of the present invention.

  In FIG. 1, reference numerals 101 and 105 denote ground capacitors, 102 denotes a bias resistor, 103 denotes a bias inductor, and 104 denotes a ground resistor. The other parts corresponding to those in FIG.

  That is, the high frequency amplifier circuit according to the first embodiment includes a bias circuit 40 including a current mirror circuit, an emitter follower circuit including a bias transistor 45, a grounded emitter amplifier circuit including an amplifier transistor 5, and the like. The bias current output terminal of the mirror circuit and the base of the biasing transistor 45 are connected, the emitter of the biasing transistor 45 is connected to the base of the amplifying transistor 5 through the bias applying element, and the bias current from the current mirror circuit is biased. The amplifier transistor 45 amplifies the current and supplies it to the base of the amplifier transistor 5. The base of the biasing transistor 45 is grounded by a grounding element composed of a grounding capacitor 101 or the like.

  Further, the bias circuit 40 includes a bias transistor 43 and a bias transistor 44, and the base of the bias transistor 43 whose emitter is grounded is connected to the emitter of the bias transistor 44, and the collector of the bias transistor 43 is biased. The base of the bias transistor 45 is connected to the reference voltage terminal 4 through the current adjustment resistors 42 and 41, and the base of the bias transistor 45 is connected to the connection point of the current adjustment resistors 42 and 41. The power supply voltage is applied to the collector of the bias transistor 44 and the collector of the bias transistor 45.

  Further, the bias applying element includes a bias resistor 102, a bias inductor 103, and the like. The bias inductor 103 and the base of the amplifying transistor 5 are connected, and the bias current from the emitter of the bias transistor 45 is used as the bias inductor 103. Is supplied to the base of the amplifying transistor 5 via A connection point between the emitter of the biasing transistor 45 and the biasing resistor 102 is grounded by a grounding element composed of a grounding capacitor 105 or the like.

  In FIG. 1, in the high frequency amplifier circuit according to the first embodiment, the RF signal input to the RF signal input terminal 1 is amplified by the amplifying transistor 5 via the input matching circuit 20 and then passed through the output matching circuit 30. , And output from the RF signal output terminal 2. The base of the biasing transistor 45 is grounded by the ground capacitor 101, and the emitter of the biasing transistor 45 is connected to the base of the amplifying transistor 5 through the biasing resistor 102 and the biasing inductor 103, and the grounding resistor 104. The grounding capacitor 105 is grounded together with the emitter of the biasing transistor 43 and the emitter of the amplifying transistor 5 via the grounding capacitor 105.

  Here, at least the amplifying transistor 5, the biasing transistors 43, 44, and 45, the biasing resistor 102, the biasing inductor 103, the grounding resistor 104, and the grounding capacitor 105 are formed on the same semiconductor substrate.

  With this configuration, when a high level RF signal is input, the decrease of the base-emitter voltage VBE of the amplifying transistor 5 is reduced by the addition of the ground capacitor 101, the ground resistor 104, and the ground capacitor 105. Since the drop in VBE can be canceled, the shortage of output power at the time of a strong input level can be improved.

  Further, the grounding of the series connection body of the grounding resistor 104 and the grounding capacitor 105 and the grounding of the emitter of the biasing transistor 43 are connected in common with the emitter of the amplifying transistor 5 and then grounded, whereby the harmonics of the RF signal to the biasing circuit are obtained. Since leakage of waves can be sufficiently suppressed, the occurrence of thermal runaway of the amplifying transistor 5 at the time of strong input can be suppressed.

  Further, by connecting the bias inductor 103 to the base of the amplifying transistor 5, the parasitic capacitance of the bias inductor enters between the base of the amplifying transistor 5 and the ground, thereby obtaining a configuration in which input matching can be easily achieved.

(Second Embodiment)
FIG. 2 is a circuit diagram showing a high frequency amplifier circuit according to a second embodiment of the present invention. An example of the configuration and operation of the high-frequency amplifier circuit according to the second embodiment will be described with reference to FIG.

  In FIG. 2, reference numerals 201 and 202 denote diodes, and other parts corresponding to those in FIG.

  In FIG. 2, a diode 201 and a diode 202 are connected in series, and the anode of the diode 201 is connected to the base of the bias transistor 45 and the ground capacitor 101 via the current adjustment resistor 42, and via the current adjustment resistor 41. The cathode of the diode 202 is connected to the reference voltage terminal 4 and connected to the emitter of the amplifying transistor 5 and then grounded.

  Compared with the first embodiment, the above configuration uses a forward voltage of a diode by a series connection body of diodes 201 and 202 as a reference voltage of the bias circuit. In addition to obtaining the same operation and effect as the embodiment, the bias circuit can be simplified, so that a high-frequency amplifier circuit with a small circuit scale can be obtained.

(Third embodiment)
FIG. 3 is a circuit diagram showing a high frequency amplifier circuit according to a third embodiment of the present invention. An example of the configuration and operation of the high-frequency amplifier circuit according to the third embodiment will be described with reference to FIG.

  In FIG. 3, reference numerals 301 and 302 denote bias transistors, and the other parts corresponding to those in FIG.

  In FIG. 3, the base of the bias transistor 302 is connected to the emitter of the bias transistor 301, the collector is connected to the base of the bias transistor 301, the current adjustment resistor 41 is connected to the reference voltage terminal 4, and Grounding is performed via the grounding capacitor 101. The collector of the bias transistor 301 is connected to the power supply terminal 3, and the emitter is connected to the base of the amplifying transistor 5 through the bias resistor 102 and the bias inductor 103. Further, the emitter of the bias transistor 301 is connected to the emitter of the amplifying transistor 5 together with the emitter of the bias transistor 302 via the ground resistor 104 and the ground capacitor 105.

  Compared to the first embodiment, the above configuration is a configuration in which the base current is directly supplied from the current mirror circuit to the amplifying transistor 5 without using the emitter follower circuit in the bias circuit. In addition to obtaining the same operation and effect as the first embodiment, the bias circuit can be simplified, so that a high-frequency amplifier circuit with a small circuit scale can be obtained.

(Fourth embodiment)
FIG. 4 is a circuit diagram showing a high frequency amplifier circuit according to a fourth embodiment of the present invention. An example of the configuration and operation of the high-frequency amplifier circuit according to the fourth embodiment will be described with reference to FIG.

  FIG. 4 specifically shows an IC layout and a wire bonding method when the high-frequency amplifier circuit according to the first embodiment shown in FIG. 1 is integrated, 401 is a semiconductor substrate, and 402 is an IC. The package frame, 403 is an IC package, 404 is a bonding pad, 405 is a bonding wire, 5a, 5b, and 5c are transistor cells constituting the amplifying transistor 5, and the other parts corresponding to those in FIG. A description will be omitted.

  In FIG. 4, transistor cells 5 a, 5 b, 5 c, bias circuit 40, bias resistor 102, bias inductor 103, ground resistor 104, and ground capacitor 105 are integrated on the same semiconductor substrate 401 and enclosed in an IC package 403. Has been.

  The amplifying transistor 5 is constituted by parallel connection of transistor cells 5a, 5b, and 5c, and these emitters are connected to the ground of the bias circuit and the grounding capacitor 105 in common, and then bonded to the bonding wire 405 via the bonding pad 404. The IC package frame 402 is grounded. Note that the grounding of the emitter of the amplifying transistor is provided with a plurality of bonding pads 404 and bonding wires 405 to reduce the inductance component of the emitter, thereby improving the gain. The high frequency amplifier circuit of the first embodiment can be integrated.

(Fifth embodiment)
FIG. 5 is a circuit diagram showing a high frequency amplifier circuit according to a fifth embodiment of the present invention. An example of the configuration and operation of the high-frequency amplifier circuit according to the fifth embodiment will be described with reference to FIG.

  FIG. 5 specifically shows another example of the IC layout and the wire bonding method when the high-frequency amplifier circuit according to the first embodiment shown in FIG. 1 is integrated. The parts corresponding to are assigned the same reference numerals and the description thereof is omitted.

  In FIG. 5, as compared with the fourth embodiment of FIG. 4, bonding pads are provided on the emitters of the transistor cells 5a, 5b, 5c, respectively, and grounded by separate bonding wires.

  With the configuration described above, the same effects as those of the first embodiment can be obtained. In addition, by independently grounding the emitter of the amplifying transistor cell, the center of the amplifying transistor at the time of strong input can be obtained. Since the influence of the negative feedback of the emitter due to the concentration of the collector current is suppressed, a more stable high-frequency amplifier circuit can be obtained against the thermal runaway of the amplifying transistor at the time of strong input.

(Effect of the embodiment of the present invention)
Next, effects in the embodiment of the present invention will be described with reference to FIGS.

  FIG. 6 shows an experimental result of gain characteristics with respect to the input when the ground capacitor 101 is added and when the ground capacitor 101 is removed in the high frequency amplifier circuit of the first embodiment shown in FIG. 10 shows experimental results of gain characteristics with respect to inputs of the high-frequency amplifier circuit of the second embodiment shown in FIG. 2 and the conventional high-frequency amplifier circuit shown in FIG.

  6 and 7 are experimental results when used in the power amplification circuit of the transmission unit of the wireless LAN terminal in the 5.2 GHz band, the power supply voltage is 3.3 V, the horizontal axis in the figure is the RF signal level, The vertical axis represents the gain of the high frequency amplifier circuit. In the experiment, a power amplifier circuit having three amplification stages was used, and only the final stage was measured using the circuit according to the embodiment of the present invention.

  From FIG. 6, it can be seen that improvement in gain reduction with respect to input is achieved by grounding the base of the emitter follower circuit of the bias circuit by the ground capacitor 101.

  Further, from FIG. 7, in the conventional high frequency amplifier circuit shown in FIG. 9, thermal runaway occurs from an input signal level of around 0 dBm, and the gain is deteriorated. However, in the second embodiment of FIG. In the high-frequency circuit, it can be seen that the grounding of the emitter of the bias follower circuit and the ground of the bias circuit are made common with the emitter of the amplifying transistor and then grounded, thereby suppressing the deterioration of thermal runaway.

(Transceiver using high-frequency amplifier circuit)
Next, a transceiver including a transmitter and a receiver using the high-frequency amplifier circuit in the above-described embodiment will be described with reference to FIG.

  FIG. 8 is a block diagram of a 5 GHz band wireless LAN terminal having a transmission / reception function. 801 is a transmission / reception antenna, 802 is a switching circuit, 803 is a low noise amplification circuit, 804, 806, 814, 816 are Bandpass filters (BPF) 805 and 813 are mixer circuits, 807 is a quadrature signal demodulator, 808 is a baseband signal processor, 809 is a controller, 810 is a local oscillator, 811 is a PLL circuit, and 812 is a quadrature signal modulator. Reference numeral 815 denotes a power amplifier circuit. Also, any of the high-frequency amplifier circuits shown in FIGS. 1 to 5 is used for the low-noise amplifier circuit 803 and the power amplifier circuit 815 of FIG.

  Regarding transmission / reception in the wireless LAN terminal of FIG. 8, a case will be described first where a 5.2 GHz band RF signal transmitted from a wireless LAN access point or a personal computer equipped with another wireless terminal is received.

  In FIG. 8, the control unit 809 of the baseband signal processing unit 808 switches the switching circuit 802 to the reception side and sets the transmission unit to an off state, so that the reception unit (low noise amplification circuit 803, bandpass filter 804, mixer circuit 805, Band-pass filter 806, orthogonal signal demodulator 807, etc.) are turned on.

  The RF signal transmitted from the access point or another personal computer is received from the transmission / reception antenna 801 and input to the low noise amplification circuit 803 via the switching circuit 802. The input RF signal is amplified and input to the mixer circuit 805 via the band pass filter 804. In the mixer circuit 805, the input RF signal is frequency-converted into an intermediate frequency signal in the 1 GHz band by the local oscillation signal from the local oscillation circuit 810 for both transmission and reception whose oscillation frequency is controlled by the PLL circuit 811, and the bandpass filter 806. Is input to the orthogonal signal demodulator 807. In the orthogonal signal demodulator 807, the input intermediate frequency signal is demodulated into an I / Q orthogonal signal, and then demodulated into a baseband data signal by a baseband signal processor 808 (not shown). The demodulated data signal is stored in a memory of a personal computer or the like equipped with the transceiver via an interface.

  Next, a case where a data signal is transmitted from the wireless LAN transmission / reception unit to an access point or another personal computer equipped with the wireless LAN will be described.

  In FIG. 8, the control unit 809 of the baseband signal processing unit 808 switches the switching circuit 802 to the transmission side, turns the reception unit off, and transmits the transmission unit (orthogonal signal modulation unit 812, mixer circuit 813, bandpass filter 814, Power amplifier circuit 815, bandpass filter 816, etc.) are turned on.

  The baseband signal processing unit 708 modulates the data signal into an I / Q quadrature signal and inputs it to the quadrature signal modulation unit 812. The input I / Q quadrature signal is modulated and output as an intermediate frequency signal in the 1 GHz band by the quadrature signal modulation unit 812 and input to the mixer circuit 813. The input intermediate frequency signal is frequency-converted and output to a 5.2 GHz band RF signal in the mixer circuit 813 by the local oscillation signal from the local oscillation circuit 810 for both transmission and reception whose oscillation frequency is controlled by the PLL circuit 811. The signal is input to the power amplifier circuit 815 via the pass filter 814. The power amplifier circuit 815 amplifies the input RF signal and transmits the amplified RF signal through the band-pass filter 816 and the switching circuit 802 by the transmission / reception antenna 801.

  In the transmitter / receiver in the wireless LAN terminal of FIG. 8 described above, by using the high-frequency amplifier circuit shown in FIGS. 1 to 5 for the low noise amplifier 803 and the power amplifier circuit 815, the reception performance and transmission performance with a wide dynamic range are excellent. Can get a transceiver.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The high-frequency amplifier circuit of the present invention is well applied to transceivers such as cellular phones and wireless LANs, receivers for TV, CATV, satellite broadcasting, satellite communication, etc., and low-noise amplifier circuits and power amplifier circuits used for them. Is possible.

1 is a circuit diagram showing a high-frequency amplifier circuit according to a first embodiment of the present invention. It is a circuit diagram which shows the high frequency amplifier circuit of 2nd Embodiment by this invention. It is a circuit diagram which shows the high frequency amplifier circuit of 3rd Embodiment by this invention. It is a circuit diagram which shows the high frequency amplifier circuit of 4th Embodiment by this invention. It is a circuit diagram which shows the high frequency amplifier circuit of 5th Embodiment by this invention. It is a figure which shows the experimental result of the gain characteristic with and without the bias voltage correction in the high-frequency amplifier circuit according to the first embodiment of the present invention. It is a figure which shows the experimental result of the gain characteristic of the high frequency amplifier circuit of 2nd Embodiment by this invention, and the high frequency amplifier circuit of a prior art. It is a block diagram which shows the transmitter / receiver comprised using the high frequency amplifier circuit by this invention. It is a circuit diagram which shows the high frequency amplifier circuit of a prior art.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... RF signal input terminal, 2 ... RF signal output terminal, 3 ... Power supply terminal, 4 ... Reference voltage terminal, 5 ... Amplifying transistor, 6, 7, 101, 105 ... Grounding capacitor, 8, 103 ... Bias inductor, DESCRIPTION OF SYMBOLS 9,102 ... Bias resistor, 20 ... Input matching circuit 21, 22, 32 ... Capacitor, 23, 31, 33 ... Inductor, 30 ... Output matching circuit, 40 ... Bias circuit, 41, 42 ... Current adjustment resistor, 43, 44, 45, 301, 302: bias transistor, 104: ground resistance, 201, 202 ... diode, 401 ... semiconductor substrate, 402 ... IC package frame, 403 ... IC package, 404 ... bonding pad, 405 ... bonding wire 801... Transmission / reception antenna, 802. Switching circuit, 803. Low noise amplification circuit, 804 806, 814, 816 ... band pass filter, 805, 813 ... mixer circuit, 807 ... orthogonal signal demodulator, 808 ... baseband signal processor, 809 ... controller, 810 ... local oscillator, 811 ... PLL circuit, 812 ... Orthogonal signal modulator, 815... Power amplifier circuit.

Claims (10)

A bias circuit composed of a current mirror circuit, an emitter follower circuit having a third biasing transistor, and a grounded emitter amplifier circuit having an amplifying transistor;
A bias current output terminal of the current mirror circuit and a base of the third bias transistor are connected; an emitter of the third bias transistor is connected to a base of the amplification transistor via a bias applying element; A high-frequency amplifier circuit configured to amplify a bias current from a current mirror circuit with the third bias transistor and supply the current to a base of the amplifier transistor;
A high frequency amplifier circuit characterized in that the base of the third biasing transistor is grounded by a first grounding element comprising a capacitor. The high frequency amplifier circuit according to claim 1,
The bias circuit includes a first bias transistor and a second bias transistor, and a base of the first bias transistor whose emitter is grounded is connected to an emitter of the second bias transistor, and The collector of one bias transistor is connected to the base of the second bias transistor and the base of the third bias transistor, and a reference voltage is applied via a current adjusting resistor, and the second bias transistor is applied. A high frequency amplifier circuit characterized in that a power supply voltage is applied to the collector of the transistor for transistor and the collector of the third bias transistor. In the high frequency amplifier circuit according to claim 1 or 2,
A high-frequency amplifier circuit, wherein a connection point between the emitter of the third bias transistor and the bias applying element is grounded by a second grounding element comprising a capacitor. The high frequency amplifier circuit according to any one of claims 1 to 3,
The bias applying element includes a bias resistor and a bias inductor, connects the bias inductor and the base of the amplifying transistor, and transmits a bias current from the emitter of the third bias transistor via the bias inductor. A high-frequency amplifier circuit characterized in that the high-frequency amplifier circuit is supplied to the base of the amplifying transistor. In the high frequency amplifier circuit according to any one of claims 1 to 4,
The multi-stage amplifier circuit includes one or more stages of the high-frequency amplifier circuit, and the high-frequency amplifier circuit of the multi-stage amplifier circuit includes the same bias circuit, the third bias transistor, the amplifier transistor, and the bias applying element. A high frequency amplifier circuit formed on a semiconductor substrate. The high frequency amplifier circuit according to claim 5,
The ground terminal of the bias circuit and the ground terminal of the second ground element are commonly connected to the emitter of the amplifying transistor, and the emitter of the amplifying transistor is encapsulated in a high-frequency amplifier circuit formed on the same semiconductor substrate. A high frequency amplifier circuit characterized by being grounded to a ground terminal of an IC package. The high frequency amplifier circuit according to claim 5,
The amplifying transistor has a configuration in which two or more unit transistor cells are connected in parallel, and the emitters of a plurality of unit transistor cells constituting the amplifying transistor are independently formed on the same semiconductor substrate. A high frequency amplifier circuit characterized in that it is grounded to the ground terminal of an IC package enclosing the high frequency amplifier circuit. From a low noise amplifier circuit that amplifies and outputs the received RF frequency signal, a mixer circuit that converts the RF frequency signal output from the low noise amplifier circuit into an intermediate frequency signal by a local oscillation signal, and the mixer circuit A receiver having a demodulation circuit for demodulating an output intermediate frequency signal,
A receiver using the high-frequency amplifier circuit according to claim 1 as the low-noise amplifier circuit. A mixer circuit that converts an intermediate frequency signal modulated and output in the modulation circuit into an RF frequency signal by a local oscillation signal, and a power amplifier circuit that amplifies the RF frequency signal output from the mixer circuit to a desired signal level; A transmitter,
A transmitter using the high-frequency amplifier circuit according to claim 1 for the power amplifier circuit. A low noise amplifier circuit that amplifies and outputs the received RF frequency signal; a first mixer circuit that converts the RF frequency signal output from the low noise amplifier circuit into an intermediate frequency signal using a local oscillation signal; and A receiver having a demodulation circuit for demodulating the intermediate frequency signal output from the first mixer circuit;
A second mixer circuit that converts an intermediate frequency signal modulated and output in the modulation circuit into an RF frequency signal by a local oscillation signal, and amplifies the RF frequency signal output from the second mixer circuit to a desired signal level. A transmitter having a power amplifier circuit
A transmitter / receiver configured to perform transmission and reception alternately with the receiving unit turned off at the time of transmission and the transmission unit turned off at the time of reception;
A transceiver comprising the high-frequency amplifier circuit according to claim 1 as the low-noise amplifier circuit and the power amplifier circuit.

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