JP2008271517A - High frequency power amplifier and amplification method, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high frequency power amplifier which accurately detects a change in a gain, is immune to load variation and reduces nonlinear distortion in a mobile unit adopting a digital modulation scheme with amplitude variation. <P>SOLUTION: A first detection circuit and a second detection circuit are connected to an input node and an output node of a final stage. Detection signals detected in the respective detection circuits are input to a differential amplifier circuit. The signal level difference output from the differential amplifier circuit does not change even if the input power varies. Because a change in the power gain at the output node does not travel back to the input node when the load impedance of a high frequency power amplifier varies, it is possible to detect only the change in the load impedance. Damage to the final stage can be prevented by controlling the operating current of the final stage and the gain of the drive stage according to the detected load variation. Furthermore, nonlinear distortion in the high frequency power amplifier can also be reduced by detecting the change in the gain of the drive stage and canceling the change in the gain of the adjustment stage. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique for amplifying a high-frequency signal in a small-sized, light-weight and low-current-consumption mobile radio communication device such as a mobile phone, and more particularly to a technique for a high-frequency power amplifier, a semiconductor device, and a high-frequency power amplification method.

  A mobile device typified by a cellular phone includes a high frequency power amplifier and transmits a signal in a radio frequency band to a sufficiently large power for transmission from an antenna to a fixed station. This high-frequency power amplifier is required to be small in size, low in power consumption, and inexpensive. In order to amplify radio frequency band signals, gallium arsenide field-effect transistors (GaAsFETs), heterojunction bipolar transistors (HBTs), and silicon germanium HBTs (SiGe-HBTs) are used. High performance transistors are used.

  The modulated radio frequency band signal is amplified from 100 times to 10,000 times by the high frequency power amplifier and transmitted from the antenna end. In order to obtain such high amplification performance, the high-frequency power amplifier employs a multistage configuration in which a plurality of stages are connected. The above-described high-performance transistor is used for each stage. The signal amplified at each stage is input to the next amplification stage, and the amplitude of the signal increases as it passes through the amplification stage. In the final stage, the signal is amplified to about 1 W.

  The output end of the high frequency power amplifier is connected to the antenna. The antenna is attached to the mobile phone, but the other is terminated in space. When a shielding object such as a metal approaches the antenna, the impedance of the mounting portion varies greatly. This variation impairs the characteristics and reliability of the high frequency power amplifier. In addition, this fluctuation may cause the final stage amplification transistor to oscillate abnormally, and the amplified high-power signal may be reflected and destroyed.

  In digital modulation schemes such as code division multiple access (CDMA) and wireless local area network (WLAN), which have been adopted in many mobile phones and wireless terminals in recent years, amplitude changes in the modulation signal Therefore, linearity is required for a high-frequency power amplifier. The impedance fluctuation described above adversely affects the linearity of the high-frequency power amplifier, so that the output modulation signal is distorted to deteriorate the transmission quality of the mobile phone.

  In order to avoid this, parts having directionality such as an isolator or a circulator are mounted on the mobile phone. If a component having such directivity is arranged between the high-frequency power amplifier and the antenna so that the signal has directivity from the high-frequency power amplifier to the antenna, the signal does not return from the antenna to the high-frequency power amplifier. Impedance fluctuation is not observed on the high frequency power amplifier side. On the other hand, directional parts such as isolators and circulators are composed of members such as magnets and ferrite, and there are significant restrictions on miniaturization, weight reduction, and high integration. In recent mobile phones, there is a tendency that parts having such directionality are omitted in preference to miniaturization and price reduction.

  FIG. 12 is an example of a transmission / reception circuit unit in a radio frequency band that is mounted on a mobile phone adopting a wideband CDMA (W-CDMA: Wideband-CDMA) system. Transmission from the modem IC is input to the high frequency power amplifier 92 through the filter 90. An isolator 93 is connected to the output side of the high frequency power amplifier 92. The isolator 93 is connected to the antenna 95 via the high frequency switch 94.

  FIG. 13 is a power amplifier protection circuit disclosed in Japanese Patent Laid-Open No. 2000-341052. The protection circuit eliminates the isolator by flowing a feedback current through an element arranged between the base and collector of the final stage transistor when a voltage higher than a predetermined voltage is applied to the collector terminal of the final stage transistor. Is a circuit that can protect the high-frequency power amplifier.

  FIG. 14 shows an electronic component for high frequency power amplification and a wireless communication system disclosed in Japanese Patent Application Laid-Open No. 2004-140633. A capacitive element is interposed between the output terminal of the transistor for amplifying the high-frequency signal used in the final stage and the gate terminal of the transistor constituting the current mirror circuit of the circuit ODT for detecting the output level. A change in output power due to impedance variation is reflected in the detection current of the output level detection circuit.

Further, in Japanese Patent Application Laid-Open No. 2005-054771, a detection circuit is connected to each of an input terminal and an output terminal of a power amplifier circuit, and a gain fluctuation is detected by comparing outputs of two detection circuits with a comparison circuit. By controlling the gain of the amplifier circuit based on the gain fluctuation, the linearity of the amplifier circuit is improved.
JP 2000-341052 A JP 2004-140633 A JP 2005-054771 A

  In the prior art, as a technology for configuring a mobile phone adopting the W-CDMA system, a high-frequency power amplifier is included in a transmission / reception circuit unit configured by a technology in a range as shown in FIG. In this configuration, the high-frequency power amplifier 92 does not include a protection circuit associated with the impedance variation of the antenna 95. In order to maintain the transmission quality of the mobile phone and operate stably, an isolator 93 must be connected. Since the isolator 93 is made of ferrite, permanent magnets, etc., it becomes an obstacle to reducing the size and weight of mobile devices such as mobile phones not only in size but also in weight.

  On the other hand, it is ideal that the loss of the forward pass characteristic is 0 dB, but in reality, the loss is about 0.5 dB to 1 dB. Since the isolator 93 must be inserted between the high frequency power amplifier 92 and the antenna 95, it is necessary to increase the output level of the high frequency power amplifier 92 in consideration of the power lost in the isolator 93. This is a factor that increases the power consumption of the high-frequency power amplifier, and the call time of the mobile phone is shortened or the capacity of the battery is increased.

  In order to solve the above-described problem, a power amplifier protection circuit disclosed in Japanese Patent Laid-Open No. 2000-341052 has been proposed (see FIG. 13). In this protection circuit, when the load terminated at the output terminal of the high-frequency power amplifier fluctuates, the protection circuit is started by a voltage higher than a predetermined voltage applied to the collector terminal. However, the technology including this protection circuit is mentioned for application to a GSM (Global System for Mobile Communications) system, which is a second generation digital cellular phone system standardized by Europe.

  As another conventional example, there is a technique disclosed in Japanese Patent Application Laid-Open No. 2004-140633. In this conventional example, a current mirror circuit is configured for the amplification transistor at the final stage, and a current change generated along with an impedance variation of the antenna is detected to protect the high-frequency power amplifier (see FIG. 14). reference). With regard to this circuit configuration, only the GSM system and a DCS (Digital Cellular System) system similar to this are mentioned. Furthermore, although both technologies mention protection against destruction of the high-frequency power amplifier when the load fluctuates, deterioration of modulation accuracy of the modulation signal, adverse effects on adjacent channels due to increase in distortion components of the signal waveform, etc. A technique for improving the deterioration of transmission quality is not disclosed.

  In the modulation schemes used for the GSM scheme and the DCS scheme, the amplitude signal is not included in the generated modulation signal. Therefore, in the technique disclosed in the conventional example, regarding the change from the state where the antenna is normally terminated to the state where the load fluctuation occurs, the high-frequency signal at the collector end of the signal amplification transistor at the final stage is changed. It can be detected by observing power changes, voltage changes, and current changes. However, in the W-CDMA system, CDMA system, PDC (Personal Digital Cellular) system, EDGE (Enhanced Data GSM Environment) system, WLAN, and other digital modulation systems, the modulated signal always has a signal level amplitude change. Therefore, the disclosed technique cannot distinguish between the amplitude change of the modulation signal and the amplitude change due to the load variation.

  15, FIG. 16A, FIG. 16B, FIG. 17A, and FIG. 17B show input / output characteristics at the time of 50Ω termination of the conventional high-frequency power amplifier. As shown in FIG. 15, FIG. 16A, and FIG. 16B, in the saturation region, the output power is constant with respect to the input signal level (FIG. 15). The applied voltage amplitude (FIG. 16A) is constant. On the other hand, as shown in FIG. 15, FIG. 17A, and FIG. 17B, in the non-saturated region, the output power changes according to the power level of the input signal (FIG. 15). 17B), the voltage amplitude applied to the collector (FIG. 17A) also changes.

  In the GSM system and the DCS system, the amplitude change is not included in the modulation signal, so that the high frequency power amplifier can be used in the saturation region. Moreover, since there is no amplitude change in the input signal, the output power is constant, and the current amplitude and voltage amplitude of the collector are also stable at a constant value. Under these conditions, even if the impedance of the antenna fluctuates and the operating state of the high-frequency power amplifier changes, the detected output power, current amplitude, and voltage amplitude change are all caused by load fluctuations. It is possible to detect.

  On the other hand, in the case of a digital modulation system using a high-frequency power amplifier in a non-saturated region, such as the W-CDMA system, an input modulation signal is always received even during normal operation terminated at 50Ω. The amplitude is changing. For this reason, the output power, the current amplitude, and the voltage amplitude constantly change and do not take constant values. Therefore, even if the impedance of the antenna fluctuates and the operating state of the high-frequency power amplifier changes, the change in output power, current amplitude, and voltage amplitude detected at the collector terminal of the amplification transistor at the final stage can cause load fluctuation. The resulting change cannot be detected electrically.

  Furthermore, in the configuration disclosed in Japanese Patent Application Laid-Open No. 2005-054771, gain fluctuation is detected from the input / output terminal of the power amplifier circuit. In this case, if a shield such as metal approaches and the terminal impedance of the antenna connected to the output terminal of the power amplifier circuit varies, the gain of the power amplifier circuit itself cannot be detected accurately. As a result, not only the linearity cannot be improved, but also if the detected power at the output end decreases due to the variation of the termination impedance of the antenna, the gain at the previous stage increases, and the transistor at the previous stage may be damaged. In addition, since the gain at the input / output end of the power amplifier circuit is usually set to a large value of about 30 to 40 dB, the gain detection from the input / output end has a large error, and the linearity improvement is insufficient.

  The present invention solves the above-described conventional problems, and stabilizes the operation of the high-frequency power amplifier by effectively detecting the load impedance fluctuation in the high-frequency power amplifier that amplifies the modulation signal accompanied by the amplitude fluctuation. Another object is to improve the linearity of the amplifier by effectively detecting the nonlinearity of the amplifier.

  In order to solve the above-described problems, a high-frequency power amplifier according to the present invention includes a first amplification stage that amplifies a first modulation signal into a second modulation signal, and a second amplification that amplifies the second modulation signal into a third modulation signal. And a gain change detecting unit that detects a change in gain of the second amplification stage based on the second modulation signal and the third modulation signal and generates a gain change detection signal, and the first amplification At least one of the stage and the second amplification stage changes in gain based on the gain change detection signal.

  In the semiconductor device of the present invention, the above-described high-frequency power amplifier is constituted by a semiconductor chip.

  Furthermore, the high frequency power amplification method of the present invention includes a step of amplifying the first modulation signal to the second modulation signal, a step of amplifying the second modulation signal to the third modulation signal, the second modulation signal and the third modulation signal. And detecting a change in gain in the step of amplifying the third modulated signal to generate a gain change detection signal, and amplifying the second modulated signal or the third modulated signal. In at least one of the steps of amplifying the gain, the gain changes based on the gain change detection signal.

  As described above, according to the high-frequency power amplifier, the semiconductor device, and the high-frequency power amplification method of the present invention, as in the W-CDMA system, a high-frequency power is amplified and supplied to an antenna by amplifying a digital modulation signal with an amplitude change in the modulation signal Even if there is no directional component such as an isolator in the power amplifier, the high-frequency power amplifier is protected from damage due to large power fluctuations due to load fluctuations, and is compact, lightweight, low power consumption, and stable operation. An amplifier can be provided. In addition, since it is possible to prevent the deterioration of the modulation accuracy of the modulation signal and the adverse effect on the adjacent channel due to an increase in the distortion component of the signal waveform, it is possible to provide a high-frequency power amplifier with high transmission quality. As described above, it is possible to stabilize the operation of the high frequency power amplifier and the mobile device equipped with the high frequency power amplifier.

  Several examples relating to the best mode for carrying out the present invention will be described below with reference to the drawings. In the drawings, elements that represent substantially the same configuration, operation, and effect are denoted by the same reference numerals. In addition, all the numbers described below are exemplified for specifically explaining the present invention, and the present invention is not limited to the illustrated numbers. Furthermore, the logic level represented by high / low or the switching state represented by on / off is exemplified to specifically describe the present invention, and the illustrated logic levels or switching states are different combinations. It is possible to obtain an equivalent result. In addition, the connection relationship between the components is exemplified for specifically explaining the present invention, and the connection relationship for realizing the function of the present invention is not limited to this. Furthermore, although the following embodiments are configured using hardware and / or software, the configuration using hardware can also be configured using software, and the configuration using software uses hardware. Can be configured.

(Embodiment 1)
FIG. 1 is an equivalent circuit diagram showing a configuration example of the high-frequency power amplifier according to the first embodiment. As shown in FIG. 1, the high-frequency power amplifier according to the first embodiment includes an amplifying transistor 1, a matching circuit 7, and a driving stage 2. An amplifier input signal Pin is input to the amplifier input terminal P1. The amplification transistor 1 is also called the final stage 1 or the amplification stage 1, the drive stage 2 is also called the amplification stage 2, and the amplifier input signal Pin is also called the modulation signal.

  The modulation signal is generated by modulating the carrier wave with the modulated signal based on the modulation method. The modulated signal is an audio signal or an internet data signal in the case of a mobile phone, and an internet data signal in the case of a wireless local area network (WLAN). In this case, the modulation signal involves not only phase fluctuation but also amplitude fluctuation in accordance with the modulated signal, such as code division multiple access (CDMA). The modulation signal has a frequency band from 800 MHz to over 2 GHz in the case of a cellular phone, and a frequency band from 2.4 GHz to over 5 GHz in the case of WLAN. The high frequency power amplifier according to the first embodiment amplifies the power of a modulation signal accompanied by amplitude fluctuation in such a frequency band.

  The amplifier input signal Pin is input to the base terminal of a transistor that is included in the drive stage 2 and whose emitter terminal is grounded, amplified by the drive stage 2 to the drive stage output signal S2, and output from the collector terminal. The drive stage output signal S2 is also called a modulation signal, the base terminal is also called an input terminal, the emitter terminal is also called a common terminal, and the collector terminal is also called an output terminal. The drive stage output signal S2 becomes an amplification transistor input signal S1A through the matching circuit 74 and is input to the base terminal 1A of the amplification transistor 1. The amplification transistor input signal S1A is also called a final stage input signal or a modulation signal, and the base terminal 1A is also called an input terminal. The matching circuit 74 is constituted by, for example, one capacitor, matches input / output impedances, and converts the drive stage output signal S2 into an amplification transistor input signal S1A. The matching circuit 74 also functions as a coupling capacitor.

  The amplifying transistor input signal S1A is amplified to an amplifying transistor output signal S1B by the amplifying transistor 1 whose emitter terminal 1C is grounded (that is, the emitter is grounded), and is output from the collector terminal 1B. The amplification transistor output signal S1B is also called a final stage output signal or a modulation signal, the emitter terminal 1C is also called a common terminal, and the collector terminal 1B is also called an output terminal. The amplification transistor output signal S1B becomes an amplifier output signal Pout through the matching circuit 7, is output from the amplifier output terminal P2, and is supplied to an antenna (not shown). The amplifier output signal Pout is also called a modulation signal.

  That is, the amplifying transistor 1 inputs the modulation signal S1A between the input terminal 1A and the common terminal 1C, amplifies the modulation signal S1A to the modulation signal S1B, and outputs it between the output terminal 1B and the common terminal 1C. To do. The power supply voltage Vcc is supplied from the circuit power supply to the collector terminal 1B of the driving stage 2 and the collector terminal 1B of the amplifying transistor 1 via the inductance loads L2 and L1, respectively.

  The matching circuit 7 includes, for example, an inductance 7L whose one end is connected to the input terminal, a capacitor 7C1 connected between the other end of the inductance 7L and the ground terminal, and a connection between the other end of the inductance 7L and the output terminal. Including the capacitor 7C2. The matching circuit 7 matches the input / output impedance of the matching circuit 7 and converts it from the amplification transistor output signal S1B to the amplifier output signal Pout. That is, the output impedance of the amplifying transistor 1 is matched to the 50 ohm transmission line impedance from the amplifier output terminal P2 to the antenna. The matching circuit 7 is also called a matching unit.

  The amplification transistor 1 includes a detection circuit 3 that generates a detection output signal S3 that indicates the magnitude of the amplification transistor input signal S1A, and a detection circuit that generates a detection output signal S4 that indicates the magnitude of the amplification transistor output signal S1B. 4 is connected. In the detection circuit 3, in the frequency band amplified by the amplification transistor 1, the amplification transistor input signal S1A is detected and converted into a detection output signal S3 that generally represents a DC voltage. In the detection circuit 4, in the frequency band amplified by the amplification transistor 1, the amplification transistor output signal S1B is detected and converted into a detection output signal S4 that substantially represents a DC voltage. Each detection output signal S3, S4 is also simply referred to as a detection signal.

  The detection circuit 3 includes a capacitor 3C1, a resistor 3R, a rectifying diode 3D, and a capacitor 3C2. The capacitor 3C1 is connected to the base terminal 1A of the amplification transistor 1, and cuts off the direct current component of the amplification transistor input signal S1A. The resistor 3R is connected to the other end of the capacitor 3C1 and adjusts the amount of attenuation of the signal level of the amplification transistor input signal S1A. The rectifying diode 3D has an anode terminal connected to the other end of the resistor 3R. The capacitor 3C2 is connected between the cathode terminal of the rectifying diode 3D and the ground terminal, and bypasses the AC component.

  The detection circuit 4 is configured similarly to the detection circuit 3, and includes a capacitor 4C1, a resistor 4R, a rectifying diode 4D, and a capacitor 4C2. The capacitor 4C1 is connected to the collector terminal 1B of the amplification transistor 1, and cuts off the direct current component of the amplification transistor output signal S1B. The resistor 4R is connected to the other end of the capacitor 4C1 and adjusts the amount of attenuation of the signal level of the amplification transistor output signal S1B. The rectifying diode 4D has an anode terminal connected to the other end of the resistor 4R. The capacitor 4C2 is connected between the cathode terminal of the rectifying diode 4D and the ground terminal, and bypasses the AC component.

  In order to minimize the loss of the amplification transistor input signal S1A and the amplification transistor output signal S1B due to the connection of the detection circuits 3 and 4, the capacitors 3C1 and 3C2 are set sufficiently small. Detected power S3P appears between the resistor 3R and the diode 3D, and detected power S4P appears between the resistor 4R and the diode 4D. When the amplifier output terminal P2 is terminated at 50 ohms, that is, when there is no load impedance fluctuation, which will be described later, a resistance corresponding to the power gain of the amplifying transistor 1 is set so that the detected powers S3P and S4P are substantially equal to each other. The size of 4R is made larger than that of the resistor 3R. In this case, the magnitude of the detection output signal S3 at both ends of the capacitor 3C2 is approximately equal to the magnitude of the detection output signal S4 at both ends of the capacitor 4C2. For example, the power gain of the amplifying transistor 1 is 10 times, the capacitors 3C1, 4C1 are 1 pF, the resistor 3R is 10 ohms, and the resistor 4R is 100 ohms.

  The detection output signal S3 and the detection output signal S4 are input to the inverting input terminal and the non-inverting input terminal of the differential amplifier circuit 5, respectively. The differential amplifier circuit 5 outputs a gain change detection signal S5 representing a difference signal obtained by subtracting the detection output signal S3 from the detection output signal S4. The differential amplifier circuit 5 is not limited to the differential amplifier circuit, and may be any block that functions to generate a difference signal between two input signals. In this sense, the differential amplifier circuit 5 is also called a difference unit. As described above, when there is no load impedance variation, the detection output signals S3 and S4 are approximately equal to each other, and thus the gain change detection signal S5 is approximately zero.

  The configuration including the detection circuit 3, the detection circuit 4, and the differential amplifier circuit 5 is also referred to as a gain change detection unit. As described above, the gain change detection unit detects a change in the power gain of the amplification transistor 1 based on the amplification transistor input signal S1A and the amplification transistor output signal S1B, and generates the gain change detection signal S5. The gain change detection signal S5 changes monotonously as the gain of the amplifying transistor 1 increases. The gain change detection unit may generate the gain change detection signal S5 based on the amplifier output signal Pout instead of the amplification transistor output signal S1B. The gain change detection unit may generate the gain change detection signal S5 based on the drive stage output signal S2 instead of the amplification transistor input signal S1A.

  The gain change detection signal S5 is compared with a predetermined reference voltage VrefA by the comparator 6A. When the gain change detection signal S5 exceeds the reference voltage VrefA, a comparison output voltage S6A is output. That is, the comparison output voltage S6A changes from the low state to the high state. The comparator 6A is also called a comparison unit.

  The comparison output voltage S6A is input to the base bias circuit 70A. The base bias circuit is also called a bias signal generation unit. In the base bias circuit 70A, the comparison output voltage S6A is input to the base terminal of the transistor 10, and the collector output of the transistor 10 is input to the base terminals of the transistors 8 and 9. At the same time, a predetermined voltage Vbias lower than the power supply voltage Vcc is supplied from the Vbias power supply to the base terminals of the transistors 8 and 9. A power supply voltage Vcc is supplied from the Vcc power supply to the collector terminals of the transistors 8 and 9, and base bias currents S8 and S9 are output from the emitter terminals of the transistors 8 and 9, respectively. The base bias currents S8 and S9 are respectively input to the base terminal of the driving stage 2 and the base terminal 1A of the amplifying transistor 1 and supplied with an amount of current necessary to operate each of them. The direct current input current of the amplifying transistor 1 included in the amplifying transistor input signal S1A is equal to the base bias current S9. The base bias current is also called a bias signal.

  In the base bias circuit 70A, when the comparison output voltage S6A is in the low state, the transistors 8 and 9 are set in the active state by setting the base voltage to the predetermined voltage Vbias, and the base bias currents S8 and S9 are respectively supplied to the drive stage 2 and the amplifier. The transistor 1 is sufficiently supplied. On the other hand, when the comparison output voltage S6A is in the high state, the transistor 10 is turned on. Therefore, the base voltages of the transistors 8 and 9 are in the low state, so that the base bias currents S8 and S9 are digitally cut off.

  As another embodiment, the gain change detection signal S5 may be directly input to the base bias circuit 70A. In this case, the base bias circuit 70A operates in an active state. That is, as the gain change detection signal S5 increases, the collector voltage of the transistor 10 decreases, and thus the base voltages of the transistors 8 and 9 decrease, so that the base bias currents S8 and S9 decrease in an analog manner.

  As yet another embodiment, when the gain change detection signal S5 exceeds the reference voltage VrefA in the comparator 6A, a comparison output voltage S6A proportional to the gain change detection signal S5 may be output. In this case, if the gain change detection signal S5 does not increase to the reference voltage VrefA, the base bias currents S8 and S9 are sufficiently supplied. If the gain change detection signal S5 exceeds the reference voltage VrefA, the base bias currents S8 and S9 are Decrease in analog.

  For example, when the amplifier input signal Pin is a modulated signal with amplitude fluctuation and there is no load fluctuation as in the CDMA system, both the amplification transistor input signal S1A and the amplification transistor output signal S1B fluctuate synchronously. In this case, the gain change detection signal S5 is substantially zero as described above.

  On the other hand, the power gain of the amplifying transistor 1 changes due to the fluctuation of the load impedance at the amplifier output terminal P2. The amplification transistor output signal S1B fluctuates due to direct influence, but the amplification transistor input signal S1A does not fluctuate and does not fluctuate because it passes through the amplification transistor 1. For this reason, the voltage of the gain change detection signal S5 varies according to the load variation.

  Thus, the gain change detection signal S5 does not show the influence of the amplitude fluctuation of the modulation signal, but only the influence of the load fluctuation. When the load fluctuation increases, the base bias currents S8 and S9 are cut off or reduced. When the base bias current S8 is cut off or reduced, the signal amplitude of the drive stage output signal S2 decreases and the signal amplitude of the amplification transistor input signal S1A decreases. When the base bias current S9 is cut off or reduced, the direct current component of the amplification transistor input signal S1A decreases. Thus, when the base bias currents S8 and S9 are cut off or reduced (that is, reduced to a predetermined amount or less), the signal amplitude and DC component of the amplification transistor input signal S1A are reduced, and as a result, The signal amplitude of the amplification transistor output signal S1B decreases. That is, the gains of the driving stage 2 and the amplifying transistor 1 are reduced, and the amplifying operation of the amplifying transistor 1 is stabilized.

  As described above, when the high-frequency power amplifier amplifies a modulation signal including amplitude variation such as CDMA, when a shield approaches the antenna and receives load impedance variation, the collector terminal 1B of the amplifying transistor 1 Both amplitude fluctuations and load fluctuations appear. In this case, only the load fluctuation is detected in the gain change detection signal S5 generated by the detection circuits 3 and 4 and the differential amplifier circuit 5.

  Therefore, when the gain change detection signal S5 becomes larger than a predetermined value, the base bias circuit 70A is used to reduce the magnitudes of the base bias currents S8 and S9 to a predetermined amount or less. As a result, the amplification transistor input signal S1A can be controlled, and overcurrent and overvoltage at the collector terminal 1B of the amplification transistor 1 can be avoided.

  In this way, the high frequency power amplifier is protected from destruction due to load fluctuations, and reliability is increased. In addition, a mobile device equipped with such a high-frequency power amplifier can prevent burning due to load fluctuations. Therefore, the operation of the high frequency power amplifier and the mobile device equipped with the high frequency power amplifier is stabilized. Furthermore, since it is not necessary to use an isolator, the mobile device can be reduced in size and weight. In addition, since there is no insertion loss of the isolator, it is possible to reduce the power consumption of the high-frequency power amplifier and extend the usage time of the mobile phone.

  The comparator 6A and the base bias circuit 70A constitute a control unit. In the first embodiment, the amplification transistor 1, the detection circuit 3, the detection circuit 4, the differential amplifier circuit 5, and the control unit are configured by one or more semiconductor chips.

(Embodiment 2)
A high-frequency power amplifier according to the second embodiment will be described. In the second embodiment, a description will be given focusing on differences from the first embodiment. Since other configurations, operations, and effects are the same as those of the first embodiment, description thereof is omitted.

  FIG. 2 is an equivalent circuit diagram showing a configuration example of the high-frequency power amplifier according to the second embodiment. As shown in FIG. 2, in the second embodiment, the base bias circuit 70B outputs predetermined base bias currents S8 and S9 based on the predetermined voltage Vbias without being controlled by the comparison output voltage S6A. On the other hand, the power supply voltage Vcc 1 is supplied from the battery 73 via the regulator circuit 72. The power supply voltage Vcc1 is also called DC power in the sense that it also includes the power supply current, and the regulator circuit 72 is also called a DC power generation unit.

  The regulator circuit 72 includes a p-type MOS transistor 20 and an operational amplifier 19. The p-type MOS transistor 20 inputs the power supply current from the battery 73 to the source terminal and supplies the power supply voltage Vcc1 from the drain terminal. The operational amplifier 19 amplifies the difference voltage between the drain terminal voltage input to the inverting input terminal and the predetermined control voltage Vctl input to the non-inverting input terminal, and outputs the amplified voltage to the gate terminal of the transistor 20. When the power supply voltage Vcc1 is increased, the difference voltage input to the operational amplifier 19 is decreased. Therefore, the current flowing through the p-type MOS transistor 20 is decreased to suppress the power supply voltage Vcc1. That is, the regulator circuit 72 adjusts the power supply voltage Vcc1 to a predetermined value based on the control voltage Vctl. The magnitude of power supply voltage Vcc1 is approximately equal to the magnitude of power supply voltage Vcc.

  The comparison output voltage S6A is input to the base terminal of the transistor 18. The emitter terminal of the transistor 18 is grounded through a resistor, the collector terminal and the power supply terminal of the operational amplifier 19 are connected to each other, and the power supply voltage Vcc is supplied from the Vcc power supply through the resistor. When the comparison output voltage S6A is in the low state, the transistor 18 is turned off, and the regulator circuit 72 adjusts the power supply voltage Vcc1 to a predetermined value. Since the transistor 18 is turned on when the comparison output voltage S6A is in the high state, the power supply voltage of the operational amplifier 19 is substantially the ground voltage, and the p-type MOS transistor 20 is turned off. That is, power supply voltage Vcc1 is approximately equal to the ground voltage.

  In some devices, the current flowing through the transistor 20 is up to about 2A. For example, load impedance fluctuations exceeding the normal assumed range such as antenna breakage may occur. In this case, the amplifying transistor 1 oscillates abnormally, an abnormal collector current flows, an overcurrent flows inside the battery, and the wiring burns out. Thus, even if the operation of the amplifying transistor 1 cannot be completely stopped in the base bias circuit 70A, the operation of the regulator circuit 72 is stopped by the comparison output voltage S6A, whereby the p-type MOS transistor 20 is removed from the battery 73. The current flowing through can be completely cut off.

  Therefore, when the gain change detection signal S5 becomes larger than a predetermined value, the amplifying operation of the driving stage 2 and the amplifying transistor 1 is stopped using the regulator circuit 72. That is, the gain of the driving stage 2 and the amplifying transistor 1 is substantially zero. As a result, the amplification transistor input signal S1A and the amplification transistor output signal S1B can be controlled, and overcurrent and overvoltage at the collector terminal 1B of the amplification transistor 1 can be avoided. Therefore, the operations of the amplifying transistor 1, the high frequency power amplifier, and the mobile device equipped with the high frequency power amplifier are stabilized. This blocking function more reliably executes the function of blocking the base bias currents S8 and S9 in the first embodiment, and therefore the same effect as in the first embodiment can be reliably obtained.

  The comparator 6A, the transistor 18, and the regulator circuit 72 constitute a control unit.

(Embodiment 3)
A high-frequency power amplifier according to the third embodiment will be described. In the third embodiment, a description will be given focusing on differences from the first embodiment. Since other configurations, operations, and effects are the same as those of the first embodiment, description thereof is omitted.

  FIG. 3 is an equivalent circuit diagram showing a configuration example of the high-frequency power amplifier according to the third embodiment. As shown in FIG. 3, in the third embodiment, the base bias circuit 70B outputs predetermined base bias currents S8 and S9 based on the predetermined voltage Vbias without being controlled by the comparison output voltage S6A. The high frequency power amplifier further includes a stabilization circuit 28 inserted between the input terminal 1A and the emitter terminal 1C (ground terminal) of the amplifying transistor 1. The configuration including the stabilization circuit 28 and the amplification transistor 1 is also referred to as a final stage or an amplification stage in the third embodiment. The stabilization circuit 28 forms part of the AC load of the driving stage 2 and forms part of the input impedance of the amplifying transistor 1.

  Stabilization circuit 28 includes a sub-stabilization circuit 28A and a sub-stabilization circuit 28B, which are connected in parallel to each other. In the sub-stabilizing circuit 28A, the resistor 32 and the capacitor 33 are connected in series with each other, and in the sub-stabilizing circuit 28B, the resistor 29, the capacitor 30 and the switching transistor 31 are connected in series with each other. The sub-stabilizing circuit 28A reduces particularly high frequency components of the driving stage output signal S2 and the amplifying transistor input signal S1A, and stabilizes the amplifying operation of the amplifying transistor 1 in a normal state where the load fluctuation can be substantially ignored. .

  The comparison output voltage S6A is input to the gate terminal of the switching transistor 31. When the comparison output voltage S6A is in the low state, the switching transistor 31 is turned off, and the stabilization circuit 28 operates only the sub-stabilization circuit 28A. Since the switching transistor 31 is turned on when the comparison output voltage S6A is in the high state, the stabilization circuit 28 operates both the sub-stabilization circuit 28A and the sub-stabilization circuit 28B. By making the stabilization circuit 28 into the configuration of the two sub-stabilization circuits 28A and 28B, it is possible to mitigate sudden power gain change and noise generation when the stabilization circuit is switched.

  Therefore, when the gain change detection signal S5 becomes larger than the predetermined value, the sub-stabilization circuit 28B further reduces particularly the high frequency component of the drive stage output signal S2 and the amplification transistor input signal S1A. As a result, the sub-stabilization circuit 28B reduces the gain of the high frequency component of the drive stage 2. When the impedance of the antenna fluctuates, the gain of the amplifying transistor 1 increases and the gain change detection signal S5 becomes larger than a predetermined value, and the sub-stabilization circuit 28B operates. Therefore, the sub-stabilizing circuit 28B reduces the power gain of the amplifying transistor 1 that is about to increase when the impedance of the antenna fluctuates by reducing the amplitude level of the amplifying transistor input signal S1A. Thus, the gains of the driving stage 2 and the amplifying transistor 1 are reduced using the sub-stabilizing circuit 28B, and the amplifying operation of the amplifying transistor 1 is further stabilized. As a result, it is possible to control the drive stage output signal S2 and the amplification transistor input signal S1A, and to avoid overcurrent and overvoltage at the collector terminal 1B of the amplification transistor 1. Therefore, the operation of the high frequency power amplifier and the mobile device equipped with the high frequency power amplifier is stabilized. This function is the same as that in the case where the base bias currents S8 and S9 are reduced in the first embodiment. Therefore, the same effect as in the first embodiment can be obtained.

  The comparator 6A constitutes a control unit. The stabilization circuit 28 may be inserted between the drive stage 2 and the matching circuit 74. The operation and effect in this case are the same as those of the third embodiment described above. The stabilization circuit 28 may be included in the control unit, and the final stage may not include the stabilization circuit 28. Also in this case, the substantial operation and effect are the same as those of the third embodiment described above.

(Embodiment 4)
A high-frequency power amplifier according to the fourth embodiment will be described. The fourth embodiment will be described with a focus on differences from the first embodiment. Since other configurations, operations, and effects are the same as those of the first embodiment, description thereof is omitted.

  FIG. 4 is an equivalent circuit diagram showing a configuration example of the high-frequency power amplifier according to the fourth embodiment. As shown in FIG. 4, in the fourth embodiment, the high frequency power amplifier further includes a variable attenuator 45 between the drive stage 2 and the matching circuit 74. The configuration including drive stage 2 and variable attenuator 45 is also referred to as an amplification stage in the fourth embodiment. The variable attenuator 45 forms part of the load of the driving stage 2.

  The gain change detection signal S5 is input to the comparator 6A and input to the comparator 6B and compared with a predetermined reference voltage VrefB. When the gain change detection signal S5 exceeds the reference voltage VrefB, the comparison output voltage S6B is Is output. That is, the comparison output voltage S6B changes from the low state to the high state. The comparison output voltage S6B is input to the variable attenuator 45. The comparator 6B is also called a comparison unit.

  In the variable attenuator 45, the comparison output voltage S6B is input to the base terminal of the transistor 41 and the gate terminals of the common-source transistors 43 and 44. The transistor 41 has an emitter terminal grounded via a resistor 41R2 and a collector terminal connected to a Vcc power supply via a resistor 41R1 and to the gate terminal of the transistor 42. The drain terminal of the transistor 43 is connected to the output terminal of the driving stage 2 through a capacitor 43C and a resistor 43R connected in series with each other, and the drain terminal of the transistor 44 is connected through a capacitor 44C and a resistor 44R connected in series with each other. To the matching circuit 74. The source terminal of the transistor 42 is connected to the output terminal of the driving stage 2 through the resistor 42R, and the drain terminal is connected to the matching circuit 74.

  When the comparison output voltage S6B is in the low state, the transistors 41, 43, and 44 are turned off and the transistor 42 is turned on. As a result, the drive stage 2 and the matching circuit 74 are in a conductive state, which is equivalent to the operation in the first embodiment. On the other hand, when the comparison output voltage S6B is in the high state, the transistors 41, 43, and 44 are turned on and the transistor 42 is turned off.

  In this case, the variable attenuator 45 has a pie-shaped (Greek character) type circuit configuration. A capacitor 43C and a resistor 43R connected in series with each other and a capacitor 44C and a resistor 44R connected in series with each other are connected in parallel with each other at both ends of the resistor 42R connected in series with each other and the transistor 42 having a high off-resistance. The As described above, the variable attenuator 45 can attenuate the drive stage output signal S2 when the comparison output voltage S6B is in the high state. As a result, the gain of the amplification stage including the drive stage 2 and the variable attenuator 45 is reduced, the amplification transistor input signal S1A is reduced, and the amplitude of the amplification transistor output signal S1B is also reduced. Operation is stabilized.

  When the load fluctuation is relatively small so that the standing wave ratio (VSWR: Voltage Standing Wave Ratio) does not exceed 3: 1, the variable attenuator 45 operates in the linear region, and therefore, the amplifier is compared with the base bias circuit 70A. There is an advantage of reducing the distortion component of the output signal Pout. Therefore, when the reference voltage VrefB is smaller than the reference voltage VrefA and the load fluctuation is small, the variable attenuator 45 is operated. When the load fluctuation is large, the base bias circuit 70A is operated together with the variable attenuator 45.

  That is, when the gain change detection signal S5 becomes larger than the predetermined value VrefB, the gain of the driving stage 2 is reduced using the variable attenuator 45. As a result, the driving stage output signal S2 and the amplification transistor input signal S1A can be controlled so that the amplification transistor input signal S1A is not distorted. For this reason, it is possible to prevent the deterioration of the modulation accuracy due to the load impedance fluctuation and the leakage of the distortion component to the adjacent channel due to the increase of the distortion component of the signal waveform. Further, when the gain change detection signal S5 becomes greater than the predetermined value VrefA, the base bias circuit 70A is used to reduce the magnitudes of the base bias currents S8 and S9 to a predetermined amount or less. As a result, it is possible to control the drive stage output signal S2 and the amplification transistor input signal S1A, and to avoid overcurrent and overvoltage at the collector terminal 1B of the amplification transistor 1. Therefore, the operation of the high frequency power amplifier and the mobile device equipped with the high frequency power amplifier is stabilized. This function is the same as that in the case where the base bias currents S8 and S9 are reduced in the first embodiment. Therefore, the same effect as in the first embodiment can be obtained.

  The comparator 6A, the base bias circuit 70A, and the comparator 6B constitute a control unit.

(Embodiment 5)
A high-frequency power amplifier according to the fifth embodiment will be described. In the fifth embodiment, a description will be given focusing on differences from the first embodiment. Since other configurations, operations, and effects are the same as those of the first embodiment, description thereof is omitted.

  FIG. 5 is an equivalent circuit diagram showing a configuration example of the high-frequency power amplifier according to the fifth embodiment. As shown in FIG. 5, in the fifth embodiment, the base bias circuit 70B outputs predetermined base bias currents S8 and S9 based on the predetermined voltage Vbias without being controlled by the comparison output voltage S6A. The high frequency power amplifier further includes an impedance conversion circuit 53 between the matching circuit 7 and the amplifier output terminal P2. The impedance conversion circuit 53 is also called an impedance setting unit. The configuration including the matching circuit 7 and the impedance conversion circuit 53 is also called a matching unit.

  The impedance conversion circuit 53 includes a transmission line 54, a capacitor 55, and a switching transistor 56. The switching transistor 56 is also referred to as a switching element, including a switching structure other than the transistor. The transmission line 54 has a characteristic impedance of approximately 50 ohms, and is inserted in series between the matching circuit 7 and the amplifier output terminal P2. Capacitor 55 and switching transistor 56 are connected in series with each other, and are connected between amplifier output terminal P2 and the ground terminal.

  The comparison output voltage S6A is input to the gate terminal of the switching transistor 56. When the comparison output voltage S6A is in the low state, the switching transistor 56 is turned off, and the operation is the same as that in the first embodiment when the comparison output voltage S6A is in the low state. On the other hand, when the comparison output voltage S6B is in the high state, the switching transistor 56 is turned on, and the impedance conversion circuit 53 is enabled. In this case, the transfer characteristics of the matching unit including the matching circuit 7 and the impedance conversion circuit 53 change. That is, the impedance conversion circuit 53 can attenuate the high frequency component of the amplifier output signal Pout and effectively correct the load impedance fluctuation. Changing the transfer characteristic of the matching unit is also referred to as changing the gain of the matching unit.

  Since the antenna connected to the amplifier output terminal P2 and the matching part form a part of the load of the amplification transistor 1, the gain of the amplification transistor 1 may increase when the impedance of the antenna fluctuates. . As a result, the gain change detection signal S5 becomes larger than a predetermined value, the switching transistor 56 is turned on, and the impedance conversion circuit 53 absorbs and removes the influence of the impedance variation of the antenna by the capacitor 55 connected in parallel to the antenna. . Therefore, the impedance conversion circuit 53 reduces the power gain of the amplifying transistor 1 that is about to increase when the antenna impedance fluctuates by absorbing and removing the antenna impedance fluctuation.

  Thus, when the gain change detection signal S5 becomes larger than a predetermined value, the amplification transistor 1 is stabilized using the impedance conversion circuit 53. As a result, the amplification transistor output signal S1B and the amplifier output signal Pout can be controlled, and overcurrent and overvoltage at the collector terminal 1B of the amplification transistor 1 can be avoided. This function is the same as that in the case where the base bias currents S8 and S9 are reduced in the first embodiment. Therefore, the same effect as in the first embodiment can be obtained. In addition, since the impedance conversion circuit 53 operates in the linear region, the amplifier output signal Pout can be prevented from being distorted. Thereby, it is possible to prevent the modulation accuracy from being deteriorated due to the load impedance fluctuation and the leakage of the distortion component to the adjacent channel due to the increase of the distortion component of the signal waveform. As described above, it is possible to stabilize the operation of the high frequency power amplifier and the mobile device equipped with the high frequency power amplifier.

  The comparator 6A constitutes a control unit. The impedance conversion circuit 53 may be included in the control unit. Also in this case, the substantial operation and effect are the same as those of the fifth embodiment described above.

(Embodiment 6)
A high-frequency power amplifier according to the sixth embodiment will be described. In the sixth embodiment, a description will be given focusing on differences from the first embodiment. Since other configurations, operations, and effects are the same as those of the first embodiment, description thereof is omitted.

  FIG. 6 is an equivalent circuit diagram showing a configuration example of the high-frequency power amplifier according to the sixth embodiment. As shown in FIG. 6, in the sixth embodiment, the base bias circuit 70B outputs predetermined base bias currents S8 and S9 based on the predetermined voltage Vbias without being controlled by the comparison output voltage S6A. The high frequency power amplifier further includes an output terminal P2C of the matching circuit 7, an amplifier output terminal P2A, and an amplifier output terminal P2B. The amplifier output terminal P2A is connected to the antenna 65, and the amplifier output terminal P2B is connected to the antenna 66. The high frequency power amplifier further includes a high frequency switch 64 between the output terminal P2A, the output terminal P2B, and the output terminal P2C. The high frequency switch 64 is also called a switch unit. The configuration including the matching circuit 7 and the high frequency switch 64 is also called a matching unit.

  The high frequency switch 64 includes a switch 62 and a switching control circuit 63. The switching control circuit 63 switches whether the amplifier output signal Pout is output to the antenna 65 or the antenna 66 based on the comparison output voltage S6A. The switching control circuit 63 maintains the current connection state when the comparison output voltage S6A is in the low state, and switches to a connection state different from the current connection state when the comparison output voltage S6A is in the high state. That is, the high frequency switch 64 controls the amplifier output signal Pout based on the comparison output voltage S6A, and selects a path through which the amplifier output signal Pout is output to the antennas 65 and 66. When the output terminal P2C and the output terminal P2A are connected, the amplifier output signal Pout is output to the output terminal P2A. Conversely, when the output terminal P2C and the output terminal P2B are connected, the amplifier output signal Pout is output from the output terminal P2A. Output to P2B.

  The reason why the comparison output voltage S6A is in the high state is that the shielding object approaches the antenna and the load impedance fluctuates. In this case, since the amplifier output signal Pout can be transmitted by switching to another antenna with a good termination status, a mobile device with high transmission quality can be provided. Also, even if the antenna is damaged, the load impedance fluctuates, so that a normal antenna can be automatically selected and the amplifier output signal Pout can be transmitted. Therefore, a highly reliable mobile device can be provided.

  As described above, for any one of the amplifier output terminal P2A and the amplifier output terminal P2B, the transfer characteristic of the matching unit including the matching circuit 7 and the high frequency switch 64 is cut off from the normal transfer characteristic by switching the high frequency switch 64. Vary between characteristics. Changing the transfer characteristic of the matching unit is also referred to as changing the gain of the matching unit.

  Since each of the antennas 65 and 66 and the matching part form part of the load of the amplifying transistor 1, the gain of the amplifying transistor 1 may increase when the impedance of the antenna fluctuates. As a result, the gain change detection signal S5 becomes larger than a predetermined value, the high frequency switch 64 is switched, and the high frequency switch 64 separates the influence of the impedance variation of each antenna 65, 66 by switching the switch. Therefore, the high frequency switch 64 reduces the power gain of the amplifying transistor 1 that is about to increase when the antenna impedance fluctuates by separating the antenna impedance fluctuation.

  Therefore, when the gain change detection signal S5 becomes larger than a predetermined value, the amplifying transistor 1 is stabilized using the high frequency switch 64. As a result, the amplifier output signal Pout can be controlled, and overcurrent and overvoltage at the collector terminal 1B of the amplifying transistor 1 can be avoided. Therefore, the operation of the high frequency power amplifier and the mobile device equipped with the high frequency power amplifier is stabilized.

  The comparator 6A constitutes a control unit. The high frequency switch 64 may be included in the control unit. Also in this case, the substantial operation and effect are the same as those in the sixth embodiment.

(Characteristic diagram and waveform diagram of the embodiment)
FIG. 7 shows the result of simulation based on the equivalent circuit in the first to sixth embodiments, and shows the input / output characteristics of the high-frequency power amplifier. In FIG. 7, the amplifier output signal Pout increases in proportion to the increase in the amplifier input signal Pin, and the detected powers S3P and S4P also increase. The detected power S3P and the detected power S4P are substantially equal to each other with respect to the same amplifier input signal Pin. As described above, the difference between the detected power S3P and the detected power S4P is substantially equal to zero with respect to the modulation signal in which the amplifier input signal Pin changes.

  8A, FIG. 8B, FIG. 8C, FIG. 8D, FIG. 8E, and FIG. 8F are waveform diagrams showing the operation of each part in the first to sixth embodiments. The horizontal axis represents time t. The vertical axis represents power in decibels in FIGS. 8A to 8D, and represents voltage in a linear scale in FIGS. 8E and 8F. 8A, 8C, and 8E show waveforms when a GSM (Global System for Mobile Communications) signal is used as the amplifier input signal Pin, and FIGS. 8B, 8D, and 8F use a CDMA signal. The waveform when there is. The GSM signal is a typical example of a modulated signal whose amplitude does not vary, and the CDMA signal is a typical example of a modulated signal whose amplitude varies.

  In FIGS. 8A and 8B, the amplifier output terminal P2 is terminated at 50 ohms and no load impedance variation occurs. For this reason, in both FIG. 8A and FIG. 8B, the amplification transistor output signal S1B has a waveform that is shifted upward by the power gain Ap of the amplification transistor 1 with respect to the amplification transistor input signal S1A.

  In FIG. 8C and FIG. 8D, the amplifier output terminal P2 is connected to the antenna, and the antenna approaches the metal shielding plate, for example, from the time point t1 to the time point t2, so that the load impedance fluctuation occurs. Therefore, from time t1 to time t2, the load fluctuations S1BC and S1BD appear only in the amplification transistor output signal S1B and do not appear in the amplification transistor input signal S1A. In the case of the GSM signal (FIG. 8C), the load fluctuation S1BC can be detected by the amplification transistor output signal S1B. However, in the case of the CDMA signal (FIG. 8D), the amplitude fluctuation and load of the modulation signal are included in the amplification transistor output signal S1B. The variation S1BD is included, and only the load variation S1BD cannot be distinguished.

  8E and 8F are waveforms of the gain change detection signal S5 for the GSM signal and the CDMA signal, respectively. In FIG. 8C and FIG. 8D, the amplification transistor output signal S1B is greatly lowered by the power gain Ap of the amplification transistor 1 by each of the detection circuits 3 and 4 as compared with the amplification transistor input signal S1A. Except for the period up to the time point t2, they are substantially equal. Therefore, as shown in FIGS. 8E and 8F, the gain change detection signal S5 is substantially zero except for the period from the time point t1 to the time point t2, and the load fluctuations S1BC and S1BD appear in the period from the time point t1 to the time point t2. . In this way, the load fluctuations S1BC and S1BD can be accurately detected for both the GSM signal and the CDMA signal by the detection circuits 3 and 4 and the differential amplifier circuit 5 having a gain difference by the power gain Ap. Is possible.

(Embodiment 7)
A high-frequency power amplifier according to the seventh embodiment will be described. The seventh embodiment will be described with a focus on differences from the first embodiment. Since other configurations, operations, and effects are the same as those of the first embodiment, description thereof is omitted. Here, a configuration including the detection circuit 3, the detection circuit 4, and the differential amplifier circuit 5 is referred to as a gain change detection unit 80. The high frequency power amplifier according to the seventh embodiment includes a gain change detection unit 80 as in the first embodiment.

  FIG. 9 is an equivalent circuit diagram showing a configuration of the high-frequency power amplifier according to the seventh embodiment. As shown in FIG. 9, the high-frequency power amplifier according to the seventh embodiment is largely different from the first embodiment in three points. The first point is that the adjustment stage 90 and the matching circuit 74A are inserted between the amplifier input terminal P1 and the drive stage 2. The second point is that the base bias circuit 70A is changed to a base bias circuit 70C. The third point is that a gain change detection unit 80A having the same configuration as that of the gain change detection unit 80 is provided.

  First, the adjustment stage 90 includes transistors 91, 92, 93 and resistors 90R1, 90R2, 90R3, 90R4. The amplifier input signal Pin becomes an adjustment stage input signal S90A through a matching circuit composed of an inductance and a capacitor, and is input to the base terminal 90A of the transistor 91. The emitter terminal 90C of the transistor 91 is grounded, and the collector terminal of the transistor 91 is connected to the emitter terminal of the transistor 92. The transistor 91 is grounded at the emitter, and the transistor 92 is grounded at the base. Therefore, the circuit including the transistors 91 and 92 has a cascode circuit configuration. The adjustment stage input signal S90A is amplified to an adjustment stage output signal S90B by this cascode circuit and output from the collector terminal 90B of the transistor 92. Adjustment stage 90 is also referred to as amplification stage 90, and adjustment stage input signal S90A and adjustment stage output signal S90B are also referred to as modulation signals. The base terminal 90A is also called an input terminal, the collector terminal 90B is also called an output terminal, and the emitter terminal 90C is also called a common terminal.

  The adjustment stage output signal S90B becomes the drive stage input signal S2A via the matching circuit 74A, and is input to the base terminal 2A of the transistor included in the drive stage 2. Like the matching circuit 74, the matching circuit 74A is composed of, for example, one capacitor, matches input / output impedances, and converts the adjustment stage output signal S90B into the drive stage input signal S2A. The matching circuit 74A also functions as a coupling capacitor. The drive stage input signal S2A is amplified to the drive stage output signal S2B by the transistor of the drive stage 2 with the emitter terminal 2C grounded, and is output from the collector terminal 2B. Drive stage output signal S2B is a signal similar to drive stage output signal S2 in the first embodiment. Drive stage input signal S2A and drive stage output signal S2B are also referred to as modulation signals. The base terminal 2A is also called an input terminal, the collector terminal 2B is also called an output terminal, and the emitter terminal 2C is also called a common terminal.

  Next, the base bias circuit 70C has a configuration in which a transistor 8A is added in parallel to the transistors 8 and 9 with respect to the base bias circuit 70A of the first embodiment.

  The comparison output voltage S6A is input to the base bias circuit 70C. In the base bias circuit 70C, the comparison output voltage S6A is input to the base terminal of the transistor 10, and the collector output of the transistor 10 is input to the base terminals of the transistors 8A, 8, and 9. At the same time, a predetermined voltage Vbias lower than the power supply voltage Vcc is supplied from the Vbias power supply to the base terminals of the transistors 8A, 8 and 9. A power supply voltage Vcc is supplied from the Vcc power supply to the collector terminals of the transistors 8A, 8, and 9, and base bias currents S8A, S8, and S9 are output from the emitter terminals of the transistors 8A, 8, and 9, respectively. The base bias currents S8A, S8, and S9 are input to the input terminal 90A of the adjustment stage 90, the input terminal 2A of the drive stage 2, and the input terminal 1A of the final stage 1, respectively. Supplied. Each base bias current S8A, S8, S9 is also called a bias signal.

  In the base bias circuit 70C, when the comparison output voltage S6A is in the low state, the transistors 8A, 8, and 9 are set in the active state with the base voltage set to the predetermined voltage Vbias, and the base bias currents S8A, S8, and S9 are adjusted. Fully supplied to stage 90, drive stage 2 and final stage 1. On the other hand, when the comparison output voltage S6A is in the high state, the transistor 10 is turned on. Therefore, the base voltages of the transistors 8A, 8, and 9 are in the low state, so that the base bias currents S8A, S8, and S9 are digitally cut off. The

  By the same operation as in the first embodiment, the gain change detection unit 80 detects a change in power gain in the final stage 1 based on the final stage input signal S1A and the final stage output signal S1B, and outputs the gain change detection signal S5. Generate. Therefore, in the gain change detection signal S5, the influence of the amplitude fluctuation of the modulation signal does not appear, and only the influence of the load fluctuation appears. When the load fluctuation increases, each base bias current S8A, S8, S9 is cut off or reduced. When the base bias current S8A is cut off or decreased, the signal amplitude of the adjustment stage output signal S1B decreases and the signal amplitude of the drive stage input signal S2A decreases. When the base bias current S8 is cut off or reduced, the DC component of the drive stage input signal S2A decreases. Thus, when each base bias current S8A, S8 is cut off or reduced, the signal amplitude and DC component of the drive stage input signal S2A decrease, and as a result, the signal amplitude of the drive stage output signal S2B decreases, The signal amplitude of the final stage input signal S1A decreases. Further, when the base bias current S9 is cut off or reduced, the DC component of the final stage input signal S1A decreases. In this way, when each base bias current S8A, S8, S9 is cut off or decreased (ie, decreased below a predetermined amount), the signal amplitude and DC component of the final stage input signal S1A decrease, and as a result. The signal amplitude of the final stage output signal S1B decreases. That is, the gains of the adjustment stage 90, the driving stage 2, and the final stage 1 are reduced, and the amplification operation of the final stage 1 is stabilized.

  As described above, when the high-frequency power amplifier amplifies the modulation signal including amplitude variation such as CDMA, when the shield approaches the antenna and receives load impedance variation, the output terminal 1B of the final stage 1 has Both amplitude fluctuations and load fluctuations appear. In this case, only the load fluctuation is detected in the gain change detection signal S5 generated by the gain change detector 80.

  Therefore, when the gain change detection signal S5 becomes larger than a predetermined value, the base bias circuit 70C is used to decrease the magnitudes of the base bias currents S8A, S8, and S9 to a predetermined amount or less. As a result, the final stage input signal S1A can be controlled, and overcurrent and overvoltage at the output terminal 1B of the final stage 1 can be avoided.

  In this way, the high frequency power amplifier is protected from destruction due to load fluctuations, and reliability is increased. In addition, a mobile device equipped with such a high-frequency power amplifier can prevent burning due to load fluctuations. Therefore, the operation of the high frequency power amplifier and the mobile device equipped with the high frequency power amplifier is stabilized. Furthermore, since it is not necessary to use an isolator, the mobile device can be reduced in size and weight. In addition, since there is no insertion loss of the isolator, it is possible to reduce the power consumption of the high-frequency power amplifier and extend the usage time of the mobile phone.

  In Embodiments 1 to 6, the operations and effects have been specifically described with reference to FIG. 7 and FIGS. 8A to 8F. However, the same applies to Embodiment 7 and thus the description thereof is omitted.

  Next, a configuration including the gain change detection unit 80A and the adjustment stage 90 will be described. Gain change detection unit 80A includes a detection circuit 3A, a detection circuit 4A, and a differential amplifier circuit 5A. Since the gain change detection unit 80A has the same configuration as the gain change detection unit 80, a detailed description thereof will be omitted. However, since the place where the gain change detection unit 80A is connected is different from the gain change detection unit 80, the optimum condition for detecting the gain change may be different. Therefore, the value of each element included in the gain change detection unit 80A may be different from the value of each element included in the gain change detection unit 80.

  Drive stage input signal S2A and drive stage output signal S2B are input to gain change detector 80A from input terminal 2A and output terminal 2B of drive stage 2, respectively, and gain change detection signal S5A is output from the output terminal of gain change detector 80A. Is output. The differential amplifier circuit 5A is also called a difference unit. Note that the gain change detection unit 80A may generate the gain change detection signal based on the amplification transistor input signal S1A instead of the drive stage output signal S2B. Note that the gain change detection unit may generate the gain change detection signal based on the adjustment stage output signal S90B instead of the drive stage input signal S2A.

  The output terminal of the gain change detection unit 80A is connected to the control terminal 90D of the adjustment stage 90, and the control terminal 90D is connected to the base terminal of the transistor 93 via the resistor 90R4. The emitter terminal of the transistor 93 is grounded via the resistor 90R3, and the collector terminal of the transistor 93 is connected to the Vcc power source via the resistor 90R2. A connection point between the collector terminal of the transistor 93 and the resistor 90R2 is connected to the base terminal of the transistor 92 via the resistor 90R1.

  The gain change detector 80A detects a change in the power gain of the drive stage 2 based on the drive stage input signal S2A and the drive stage output signal S2B, and generates a gain change detection signal S5A. When the power gain of the driving stage 2 increases, the voltage of the gain change detection signal S5A increases and the collector current of the transistor 93 increases, so the voltage at the connection point between the collector terminal of the transistor 93 and the resistor 90R2 decreases. Therefore, the collector current of the transistor 92 decreases and the magnitude of the adjustment stage output signal S90B decreases. That is, the power gain of the adjustment stage 90 decreases. On the other hand, when the power gain of the driving stage 2 decreases, the voltage of the gain change detection signal S5A decreases and the collector current of the transistor 93 decreases, so the voltage at the connection point between the collector terminal of the transistor 93 and the resistor 90R2 increases. To do. Therefore, the collector current of the transistor 92 increases, and the magnitude of the adjustment stage output signal S90B increases. That is, the power gain of the adjustment stage 90 increases. As described above, the power gain of the adjustment stage 90 changes monotonously as the gain change detection signal S5A increases by using the gain change detection unit 80A, and cancels the change in the power gain of the drive stage 2.

  The transistor in the driving stage 2 operates in, for example, a class B. In the case of class A operation, the operating current of the transistor is substantially constant regardless of the magnitude of the input signal, as shown by the curve CA in FIG. 11B. On the other hand, in the case of class B operation, the operating current of the transistor is sufficiently smaller than that in the case of class A operation in the range where the input signal is small, as shown by curve CB in FIG. However, as the input signal increases, the operating current increases rapidly. As a result, in class A operation, the power gain of the transistor is substantially constant regardless of the magnitude of the input signal, as shown by the curve PGA in FIG. 11A. On the other hand, in the case of class B operation, the power gain of the transistor gradually increases as the input signal increases, as shown by the curve PGB in FIG. 11A. Thus, the power gain of the driving stage 2 that operates in the class B changes according to the input signal.

  When the driving stage 2 exhibits the power gain characteristic as shown by the curve PG2 in FIG. 11C, the power gain of the adjustment stage 90 is compared with the horizontal line shown by the dotted line as shown by the curve PG1 by using the gain change detection unit 80A. And symmetric curves. As a result, the power gain of the amplifier circuit including the adjusting stage 90 and the driving stage 2 is substantially constant regardless of the magnitude of the input signal as indicated by the curve PG3. Since the gain change detection unit 80A performs based on the difference between the two signal powers at the input terminal 2A and the output terminal 2B of the drive stage 2, it is not affected by the amplitude fluctuation of the modulation signal as described in the first embodiment. Only the change in the power gain in the drive stage 2 can be detected.

  When the base bias currents S8A, S8, and S9 are controlled using the gain change detector 80, the comparator 6A, and the base bias circuit 70C, the base bias currents S8A, S8, and S9 are digitally abruptly controlled by the operation of the comparator 6A. To change. On the other hand, when the power gain of the adjustment stage 90 is controlled using the gain change detection unit 80A, since the comparator is not included in the control system, it changes in an analog manner so as to cancel the change in the power gain of the drive stage 2.

  Although the adjustment stage 90 is configured by a cascode circuit including transistors 91 and 92, a variable resistor VR1 is connected between the input terminal 90A and the output terminal 90B of the adjustment stage 90 as shown in FIG. The resistance value of the variable resistor VR1 may be changed based on the change detection signal S5A. In this case, when the magnitude of the gain change detection signal S5A is increased, the resistance value of the variable resistor VR1 is increased, and the attenuation amount of the power gain of the adjustment stage 90 is increased. On the other hand, when the magnitude of the gain change detection signal S5A is decreased, the resistance value of the variable resistor VR1 is decreased, and the attenuation amount of the power gain of the adjustment stage 90 is decreased. Further, as shown in FIG. 10B, the base terminal of the grounded transistor 91 is connected to the input terminal 90A, and the variable resistor VR2 is connected between the collector terminal and the output terminal 90B, and based on the gain change detection signal S5A. You may comprise so that the resistance value of variable resistance VR2 may be changed. In this case, when the magnitude of the gain change detection signal S5A increases, the resistance value of the variable resistor VR2 decreases and the power gain of the adjustment stage 90 decreases. On the other hand, when the magnitude of the gain change detection signal S5A decreases, the resistance value of the variable resistor VR2 increases and the power gain of the adjustment stage 90 increases.

  As described above, in the high frequency power amplifier according to the seventh embodiment, the change in power gain in the final stage 1 is detected by using the gain change detection unit 80, and further, the power gain can be increased by using the base bias circuit 70C. Based on the change, the magnitudes of the base bias currents S8A, S8, and S9 input to the adjustment stage 90, the driving stage 2, and the final stage 1 are abruptly limited. In the change of the power gain in the final stage 1, the influence of the amplitude fluctuation of the modulation signal does not appear, and only the influence of the load fluctuation of the output of the final stage 1 appears. As a result, even if a sudden load fluctuation occurs in the output of the final stage 1, it is possible to avoid the overcurrent and overvoltage of the final stage 1 and to prevent the high frequency power amplifier from being burned out or broken.

  In the high frequency power amplifier according to the seventh embodiment, the gain change detection unit 80A is used to detect a change in the power gain in the drive stage 2, and the adjustment stage 90 is used to detect the change in the power gain. The power gain of the adjustment stage 90 can be adjusted so as to cancel the change in the power gain of the drive stage 2. Thereby, the change of the power gain of the amplifier circuit combining the adjustment stage 90 and the drive stage 2 can be made substantially constant regardless of the magnitude of the input signal. Therefore, even if the drive stage 2 is operated in class B, the linearity of the power gain with respect to the input signal can be ensured, and both low power consumption by class B operation and high linearity comparable to class A operation are possible. It becomes. The configuration in which the gain change detection unit 80A detects the change in the power gain in the drive stage 2 and adjusts the power gain in the adjustment stage 90 is a negative feedback circuit. It is possible to stably achieve power gain compensation by reducing fluctuations due to variations in temperature characteristics.

  As described above, in the high frequency power amplifier according to the seventh embodiment, the degradation of the linearity of the final stage 1 due to the load fluctuation of the output of the final stage 1 and the linearity of the driving stage 2 due to the class B operation of the driving stage 2 are achieved. Can be prevented, so that the modulation accuracy of a modulation signal including amplitude fluctuations such as CDMA can be increased, and the leakage of harmonic distortion components to adjacent channels can be reduced, resulting in high transmission quality. A high frequency power amplifier can be provided.

  The comparator 6A and the base bias circuit 70C constitute a control unit. In the seventh embodiment, the adjustment stage 90, the drive stage 2, the final stage 1, the gain change detection unit 80, the gain change detection unit 80A, and the control unit are configured by one or more semiconductor chips.

(Summary of embodiment)
As described above, in the high-frequency power amplifier according to an embodiment, the detection circuit 3 and the detection circuit 4 are connected to the input terminal 1A and the output terminal 1B of the final stage 1, respectively. The detection output signals S3 and S4 respectively detected by the detection circuits 3 and 4 are input to the differential amplifier circuit 5, and a gain change detection signal S5 representing the difference between the detection output signals S3 and S4 is generated. When the high-frequency power amplifier is terminated at 50Ω, if the amplifier input signal Pin changes, the signal level of each of the detection output signals S3 and S4 changes, but as long as the power gain of the final stage 1 is constant, The gain change detection signal S5 is substantially zero.

  On the other hand, when the load terminated on the output side of the high frequency power amplifier (that is, the impedance of the antenna) fluctuates, the power gain of the final stage 1 changes. Further, a reflected wave generated when the load fluctuates is observed at the output terminal 1B. However, such a state in the output terminal 1B does not affect the input terminal 1A in the final stage 1. That is, there is no difference between the signal levels detected at the input terminal 1A and the output terminal 1B of the final stage 1 with respect to the amplitude change of the input signal, but there is a difference with respect to the load fluctuation. Can only detect.

  In the high-frequency power amplifier according to another embodiment, the comparator 6A performs level comparison with the reference voltage VrefA. In the differential amplifier circuit 5, the load variation is observed, and it is detected whether or not the gain change detection signal S5 exceeds the reference voltage VrefA. In the case of exceeding, the comparison output voltage S6A is output, and the amount of current S9 supplied from the base bias circuit 70A to the input terminal 1A of the final stage 1 is limited or cut off, whereby the excessive voltage at the output terminal 1B of the final stage 1 is exceeded. Current and overvoltage are avoided.

  In a high frequency power amplifier according to another embodiment, a current is supplied from the battery 73 to the final stage 1 via the regulator circuit 72. In the regulator circuit 72, the operation of the final stage 1 can be completely stopped by forcibly cutting off the current supplied to the final stage 1. For example, there is a case where a very large impedance fluctuation occurs due to the damage of the antenna, and there is no possibility of recovery. In such a case, the last stage 1 oscillates abnormally, a collector current exceeding the expected range flows, an overcurrent flows inside the battery, and the wiring burns out. As described above, in the base bias circuit 70A, even when the operation of the final stage 1 cannot be completely stopped, such a broken state can be prevented by using the regulator circuit 72.

  In a high-frequency power amplifier according to another embodiment, a stabilization circuit 28 capable of changing a resistance value is connected to the input terminal 1A of the final stage 1. Even when the power gain of the final stage 1 increases with the fluctuation of the load impedance, the high frequency power amplifier can be stably operated by suppressing the abnormal oscillation by changing the resistance value of the stabilization circuit 28.

  In the high frequency power amplifier according to another embodiment, when the load fluctuation is relatively small so that the standing wave ratio (VSWR) does not exceed 3: 1 when viewed from the high frequency power amplifier, the straight line of the high frequency power amplifier In order to maintain the characteristics, the signal level input to the final stage 1 can be changed by the gain control of the driving stage 2.

  In the high-frequency power amplifier according to another embodiment, when the comparison output voltage S6A is output, the impedance of the impedance conversion circuit 53 connected between the matching circuit 7 and the amplifier output terminal P2 is changed. As a result, the high-frequency power amplifier can be stably operated even when the load impedance varies.

  In the high frequency power amplifier according to another embodiment, a high frequency switch 64 that can be switched to two or more output paths is provided at the output end of the matching circuit 7, and when the comparison output voltage S6A is output, the high frequency switch 64 is switched. A path in which the terminal state of the antenna impedance is advantageous is always selected. As a result, the high-frequency power amplifier can be operated stably, and the transmission quality can be improved.

  In each of the detection circuits 3 and 4 of another embodiment, even if the power gain of the final stage 1 changes due to temperature fluctuation, the resistance value has temperature dependency in consideration of the temperature change amount in advance. Even with respect to temperature fluctuations, the fluctuation component of the load impedance can be correctly output from the differential amplifier circuit 5.

  In the stabilization circuit 28 of another embodiment, each of the sub-stabilization circuits 28A and 28B having a shunt configuration including at least two sets of resistors and capacitors is provided, and at least one set is used in a fixed manner. It is possible to mitigate the sudden change in power gain and the occurrence of noise that occur at the moment of switching.

  In another embodiment of the high-frequency power amplifier, the impedance conversion circuit 53 includes a transmission line 54 having a characteristic impedance of substantially 50 ohms, at least one set of a capacitor 55 and a switching circuit connected in series. It is comprised with the element 56. FIG. In accordance with the impedance to be converted, the electrical length of the transmission line 54, the insertion position of the capacitor 55 and the switching element 56, and the capacitance value of the capacitor 55 are determined in advance. When the comparison output voltage S6A is output, the switching element 56 can be turned on to convert it to a desired impedance.

  As described above, according to the embodiment of the present invention, as in the W-CDMA system, in the high-frequency power amplifier that amplifies the digital modulation signal accompanied by the amplitude change in the modulation signal and supplies the amplified signal to the antenna, the gain change detection unit 80 By using, it is possible to detect a change in power gain in the final stage 1. That is, it is possible to separate the fluctuation of power due to the change in amplitude of the modulation signal and the fluctuation of power due to the change in impedance of the antenna, and detect only the fluctuation in load impedance. By detecting the change in the load impedance, it is possible to control the amplification operation of the high-frequency power amplifier using the control unit, and to stabilize the operations of the final stage 1 and the high-frequency power amplifier. This protects the high-frequency power amplifier from destruction caused by large power fluctuations due to load fluctuations, and is compact, lightweight, low power consumption, and stable operation without the need for directional components such as isolators. Can provide. Furthermore, since it is possible to prevent the deterioration of modulation accuracy due to load impedance fluctuations and the adverse effect on adjacent channels due to an increase in distortion components of the signal waveform, it is possible to provide a high-frequency power amplifier with high transmission quality. As described above, it is possible to stabilize the operation of the high frequency power amplifier and the mobile device equipped with the high frequency power amplifier.

  Furthermore, according to the embodiment of the present invention, a change in the power gain in the drive stage 2 is detected by using the gain change detection unit 80A, and based on the change in the power gain by using the adjustment stage 90. The power gain of the adjustment stage 90 can be adjusted so as to cancel the change in the power gain of the drive stage 2. Thereby, the change of the power gain of the amplifier circuit combining the adjustment stage 90 and the drive stage 2 can be made substantially constant regardless of the magnitude of the input signal. Therefore, even if the drive stage 2 is operated in class B, the linearity of the power gain with respect to the input signal can be ensured, and both low power consumption by class B operation and high linearity comparable to class A operation are possible. It becomes. In addition, since deterioration of the linearity of the driving stage 2 due to the class B operation of the driving stage 2 can be prevented, the modulation accuracy of the modulation signal including amplitude variation such as CDMA is increased, and the adjacent channel is not affected. Leakage of harmonic distortion components can be reduced, and a high-frequency power amplifier with high transmission quality can be provided. The configuration in which the gain change detection unit 80A detects the change in the power gain in the drive stage 2 and adjusts the power gain in the adjustment stage 90 is a negative feedback circuit. It is possible to stably achieve power gain compensation by reducing fluctuations due to variations in temperature characteristics.

  The individual gains of the final stage 1 that is the detection target of the gain change detection unit 80 and the drive stage 2 that is the detection target of the gain change detection unit 80A are about 10 to 15 dB at most, and the detection error is made sufficiently small. It is possible. Therefore, it is possible to accurately detect load fluctuations, stabilize the operation of the mobile device, accurately detect gain changes, and improve the linearity of the high-frequency power amplifier.

  In the above-described embodiment, when the gain change detection signal S5 becomes larger than a predetermined value, at least one of the final stage input signal S1A, the final stage output signal S1B, and the amplifier output signal Pout is controlled. . That is, the modulation signal to be controlled may be any one of these three types, any two, or all three.

  In the above-described embodiment, bipolar transistors are used for the final stage 1, the drive stage 2, and the adjustment stage 90. However, the bipolar transistor may be either a silicon germanium transistor or a silicon transistor. . Further, a field effect transistor or an insulated gate bipolar transistor (IGBT) may be used instead of the bipolar transistor. Further, in the above-described embodiment, the number of these transistors included in the final stage 1 and the driving stage 2 is one, but a plurality of transistors may be included.

  When the final stage 1 and the drive stage 2 are configured using these transistors, typically, emitter ground or source ground is used. In this case, the input terminal is a base terminal or a gate terminal, the output terminal is a collector terminal or a drain terminal, and the common terminal is an emitter terminal or a source terminal.

  In the above-described embodiment, a CDMA system including W-CDMA is taken as a representative example as a digital modulation system with amplitude change. Furthermore, an Orthogonal Frequency Division Multiplex (OFDM) system that is used in wireless local area network (WLAN) and terrestrial digital broadcast receiving mobile phones and also proposed in 4th generation mobile phones. May be another representative example. Further, an EDGE (Enhanced Data GSM Environment) system mainly in Europe may be used as another representative example.

  Note that a temperature detection unit that detects the temperature of the final stage 1 and generates a temperature detection signal may be further provided. In this case, the resistor 3R included in the detection circuit 3 and the resistor 4R included in the detection circuit 4 change based on the temperature detection signal. Therefore, the change in the gain of the final stage 1 due to the temperature change is corrected by adjusting the attenuation amount of each of the detection circuits 3 and 4, and the temperature change of the gain change detection signal S5 can be made substantially zero.

  The above description of the embodiments is merely an example embodying the present invention. The present invention is not limited to these examples, and can be easily configured by those skilled in the art using the technology of the present invention. It can be expanded to various examples.

  The present invention can be used for a high-frequency power amplifier, a semiconductor device, and a high-frequency power amplification method.

1 is a circuit diagram showing a configuration of a high-frequency power amplifier according to Embodiment 1. FIG. 6 is a circuit diagram showing a configuration of a high-frequency power amplifier according to Embodiment 2. FIG. 6 is a circuit diagram showing a configuration of a high-frequency power amplifier according to Embodiment 3. FIG. FIG. 10 is a circuit diagram showing a configuration of a high frequency power amplifier according to a fourth embodiment. FIG. 9 is a circuit diagram showing a configuration of a high frequency power amplifier according to a fifth embodiment. FIG. 10 is a circuit diagram showing a configuration of a high-frequency power amplifier according to a sixth embodiment. It is a characteristic view which shows the input-output characteristic of the high frequency power amplifier in each embodiment. It is a wave form diagram which shows operation | movement of each part in each embodiment. It is a wave form diagram which shows operation | movement of each part in each embodiment. It is a wave form diagram which shows operation | movement of each part in each embodiment. It is a wave form diagram which shows operation | movement of each part in each embodiment. It is a wave form diagram which shows operation | movement of each part in each embodiment. It is a wave form diagram which shows operation | movement of each part in each embodiment. FIG. 10 is a circuit diagram showing a configuration of a high-frequency power amplifier according to a seventh embodiment. FIG. 10 is a circuit diagram showing a partial configuration of a high-frequency power amplifier according to a seventh embodiment. FIG. 10 is a circuit diagram showing a partial configuration of a high-frequency power amplifier according to a seventh embodiment. FIG. 16 is a waveform diagram showing an operation of the high frequency power amplifier according to the seventh embodiment. FIG. 16 is a waveform diagram showing an operation of the high frequency power amplifier according to the seventh embodiment. FIG. 16 is a waveform diagram showing an operation of the high frequency power amplifier according to the seventh embodiment. It is a circuit diagram of the transmission / reception circuit of the mobile telephone by a prior art example. It is a circuit diagram which shows one structural example of the high frequency power amplifier by a prior art example. It is a circuit diagram which shows one structural example of the high frequency power amplifier by a prior art example. It is a characteristic diagram which shows the input-output characteristic of the high frequency power amplifier by a prior art example. It is a wave form diagram which shows the input-output characteristic of the high frequency power amplifier by a prior art example. It is a wave form diagram which shows the input-output characteristic of the high frequency power amplifier by a prior art example. It is a wave form diagram which shows the input-output characteristic of the high frequency power amplifier by a prior art example. It is a wave form diagram which shows the input-output characteristic of the high frequency power amplifier by a prior art example.

Explanation of symbols

1 Amplifying transistor (or final stage)
1A, 2A, 90A Input terminal 1B, 2B, 90B Output terminal 1C, 2C, 90C Common terminal 2 Drive stage 3, 4 Detection circuit 5 Differential amplifier circuit 6A, 6B Comparator 7, 74, 74A Matching circuit 8, 8A, 9, 10, 91, 92, 93 Transistors 70A, 70B, 70C Base bias circuit 80, 80A Gain change detection unit 90 Adjustment stage L1, L2 Inductive load P1 Amplifier input terminal P2, P2A, P2B Amplifier output terminal VR1, VR2 Variable resistance

Claims (24)

A first amplification stage for amplifying the first modulated signal into a second modulated signal;
A second amplification stage for amplifying the second modulated signal into a third modulated signal;
A gain change detection unit that detects a gain change of the second amplification stage based on the second modulation signal and the third modulation signal, and generates a gain change detection signal;
A high-frequency power amplifier in which at least one of the first amplification stage and the second amplification stage changes in gain based on a gain change detection signal.   The high-frequency power amplifier according to claim 1, wherein the gain change detection unit generates a gain change detection signal that monotonously increases as the gain increases. further,
A matching unit that matches input / output impedances and converts the third modulated signal to a fourth modulated signal;
When the gain change detection signal becomes larger than a predetermined value, at least one of the first modulation signal, the second modulation signal, the third modulation signal, and the fourth modulation signal is controlled to stabilize the operation of the second amplification stage. And a control unit
The high frequency power amplifier according to claim 2, wherein the gain change detection unit generates a gain change detection signal based on the second modulation signal and one of the third modulation signal and the fourth modulation signal.   The high-frequency power amplifier according to claim 3, wherein the matching unit has an output terminal connectable to an antenna. The first amplification stage includes:
A first input terminal, a first output terminal, and a common terminal;
The first modulation signal is input between the first input terminal and the common terminal, the second modulation signal is output from between the first output terminal and the common terminal,
The second amplification stage includes
A second input terminal, a second output terminal, and a common terminal;
The high frequency power amplifier according to claim 3, wherein the second modulation signal is input between the second input terminal and the common terminal, and the third modulation signal is output from between the second output terminal and the common terminal. The controller is
A bias signal generation unit that generates a bias signal to be supplied to at least one of the first input terminal and the second input terminal;
The high frequency power amplifier according to claim 5, wherein when the gain change detection signal becomes larger than a predetermined value, the bias signal is cut off. The controller is
A DC power generation unit that generates DC power supplied to at least one of the first output terminal and the second output terminal;
6. The high frequency power amplifier according to claim 5, wherein the DC power is cut off when the gain change detection signal becomes larger than a predetermined value. The second amplification stage includes a resistor inserted between the second input terminal and the common terminal,
The high frequency power amplifier according to claim 5, wherein when the gain change detection signal becomes larger than a predetermined value, the control unit changes the magnitude of the resistance. The second amplification stage includes a stabilization circuit inserted between the second input terminal and the common terminal;
The high frequency power amplifier according to claim 5, wherein when the gain change detection signal becomes larger than a predetermined value, the control unit reduces the impedance of the stabilization circuit. The first amplification stage includes a variable attenuator that attenuates the gain of the first amplification stage;
The high frequency power amplifier according to claim 3, wherein the control unit attenuates the gain when the gain change detection signal becomes larger than a predetermined value. The matching unit includes an impedance setting unit connected to an output terminal of the matching unit,
The high-frequency power amplifier according to claim 3, wherein the control unit changes the impedance of the impedance setting unit when the gain change detection signal becomes larger than a predetermined value. The impedance setting unit includes:
A transmission line having a characteristic impedance of approximately 50 ohms;
A capacitor and a switching element connected to the output end of the transmission line and connected in series with each other;
The high-frequency power amplifier according to claim 11, wherein the control unit turns on the switching element when the gain change detection signal becomes larger than a predetermined value. The matching unit includes a switch unit connected to an output terminal of the matching unit,
The switch unit switches the path of the fourth modulation signal to one of at least two paths;
The high frequency power amplifier according to claim 3, wherein the control unit switches a path when a gain change detection signal becomes larger than a predetermined value.   The high-frequency power amplifier according to claim 3, wherein when the output terminal of the matching unit is impedance-matched, the gain change detection signal is substantially zero. The controller is
Comparing the gain change detection signal with a predetermined value, and when the gain change detection signal becomes larger than the predetermined value, includes a comparison unit that generates a comparison result signal,
The high frequency power amplifier according to claim 3, wherein the high frequency power amplifier is controlled based on a comparison result signal. And a third amplification stage for amplifying the third modulated signal,
The high frequency power amplifier according to claim 2, wherein the first amplification stage changes in gain based on a gain change detection signal.   17. The high-frequency power amplifier according to claim 16, wherein the gain of the first amplification stage changes monotonically in a monotonically decreasing manner as a gain change detection signal increases, and cancels the change in gain of the second amplification stage.   The high-frequency power amplifier according to claim 16, wherein the third amplification stage has an output terminal connectable to an antenna.   The high-frequency power amplifier according to claim 1, wherein the second amplification stage is configured by one transistor. The gain change detector is
A first detector for generating a first detection signal representing the magnitude of the second modulated signal;
A second detection unit that generates a second detection signal representing the magnitude of either the third modulation signal or the fourth modulation signal;
The high-frequency power amplifier according to claim 1, further comprising: a difference unit that generates a gain change detection signal representing a difference signal obtained by subtracting the first detection signal from the second detection signal. And a temperature detection unit that detects a temperature of the second amplification stage and generates a temperature detection signal;
The first detection unit includes a first resistor,
The second detection unit includes a second resistor,
The high frequency power amplifier according to claim 20, wherein the first resistor and the second resistor change based on a temperature detection signal.   A semiconductor device comprising the high-frequency power amplifier according to claim 1 formed of a semiconductor chip.   Further, when the gain change detection signal becomes larger than a predetermined value, at least one of the first modulation signal, the second modulation signal, the third modulation signal, and the fourth modulation signal is controlled, and the operation of the second amplification stage The semiconductor device according to claim 22, further comprising a control unit that stabilizes the voltage. Amplifying the first modulated signal to a second modulated signal;
Amplifying the second modulated signal to a third modulated signal;
Detecting a change in gain in the step of amplifying the third modulation signal based on the second modulation signal and the third modulation signal, and generating a gain change detection signal,
At least one of the step of amplifying to the second modulation signal or the step of amplifying to the third modulation signal is a high frequency power amplification method in which a gain changes based on a gain change detection signal.

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