JP2006014447A - Inverter device - Google Patents

Inverter device Download PDF

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JP2006014447A
JP2006014447A JP2004185949A JP2004185949A JP2006014447A JP 2006014447 A JP2006014447 A JP 2006014447A JP 2004185949 A JP2004185949 A JP 2004185949A JP 2004185949 A JP2004185949 A JP 2004185949A JP 2006014447 A JP2006014447 A JP 2006014447A
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conduction time
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JP4667771B2 (en
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Yasuhiro Nakai
靖博 中井
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Toshiba Mitsubishi Electric Industrial Systems Corp
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<P>PROBLEM TO BE SOLVED: To provide an inverter device which has the function of detecting the DC component of a device output by a method with little detection errors, using a relatively simple circuit configuration and compensating for this. <P>SOLUTION: The inverter device includes an inverter circuit 1 having semiconductor power elements connected in a bridge for converting a DC power into an AC power, a controller 4 for controlling the output voltage of the inverter circuit 1 according to a voltage command, a phase voltage detecting means 6 for detecting the phase voltage of the output of the inverter circuit 1, and a conduction time duration detecting means 7 receiving the output of this phase voltage detecting means 6 to detect the conduction times of the positive side and the negative side of the semiconductor power element for constituting the inverter circuit 1. The controller 4 corrects the voltage command, in response to the integrated value of the difference between the position conduction time and the negative-side conduction time obtained by the conduction time duration detecting means 7. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、インバータ装置に係り、特に交流出力相電圧の直流オフセット成分を自動補償するようにしたインバータ装置に関する。   The present invention relates to an inverter device, and more particularly to an inverter device that automatically compensates a DC offset component of an AC output phase voltage.

インバータ装置は、各相のインバータの出力電圧指令値にその出力電圧が追従するように電圧制御を行い、例えば三角波PWM方式により各相のゲート信号をつくり出し、各相アームを形成する半導体電力素子をスイッチングして、パルス状の正及び負の方形波を出力し、リアクトルおよびコンデンサで構成される出力フィルタでこれを正弦波に変換する方式が一般的である。   The inverter device performs voltage control so that the output voltage follows the output voltage command value of the inverter of each phase, for example, generates a gate signal of each phase by a triangular wave PWM method, and forms a semiconductor power element that forms each phase arm. A system is generally used in which switching is performed to output pulsed positive and negative square waves, and this is converted into a sine wave by an output filter composed of a reactor and a capacitor.

この従来のインバータ装置では、出力電圧が必ずしも電圧指令値のとおりにはならず、その出力に直流成分が現れる。この結果、負荷に直流成分を含んだ直流電圧を与えることになり、負荷のトランス等の電気部品が焼損する恐れがあった。   In this conventional inverter device, the output voltage does not necessarily follow the voltage command value, and a direct current component appears in the output. As a result, a DC voltage containing a DC component is applied to the load, and there is a risk that electrical components such as a transformer of the load will burn out.

この対策として、出力の直流成分を直流電流検出器で検出し、この検出値に従って出力電圧を補正するような対策が考えられるが、高精度の直流電流検出器は高価であるほか、回路が複雑になるという問題があった。このため、インバータ装置の各相のゲート信号に着目し、このゲート信号による駆動パルスの正側及び負側の実効値成分の差分を検出し、この検出信号に応じて駆動パルスのパルス幅を補正する提案が為されている(例えば特許文献1参照。)。
特開2002−272140号公報(第2−5頁、図1)
As a countermeasure, a DC current detector can be used to detect the DC component of the output, and the output voltage can be corrected according to the detected value. However, a high-precision DC current detector is expensive and the circuit is complicated. There was a problem of becoming. Therefore, paying attention to the gate signal of each phase of the inverter device, the difference between the effective value components of the positive and negative sides of the drive pulse by this gate signal is detected, and the pulse width of the drive pulse is corrected according to this detection signal (For example, refer to Patent Document 1).
JP 2002-272140 A (page 2-5, FIG. 1)

特許文献1に示された方法は、比較的簡単な回路で実現可能であるが、インバータ装置の出力電圧を直接検出していないため、その検出精度に問題が生じる恐れがある。その原因は各アームを形成する半導体電力素子のオンオフ動作が必ずしも理想的ではなく、オン及びオフのスイッチング時に遅れが生じ、しかも個々の半導体電力素子の特性のバラツキにより、これらのスイッチング時の遅れがアーム毎、または半導体電力素子毎に均一ではなくなるためである。   Although the method disclosed in Patent Document 1 can be realized with a relatively simple circuit, since the output voltage of the inverter device is not directly detected, there is a possibility that a problem may occur in the detection accuracy. The cause is that the on / off operation of the semiconductor power elements forming each arm is not necessarily ideal, and there is a delay in switching on and off, and the delay in switching due to variations in the characteristics of the individual semiconductor power elements. This is because it is not uniform for each arm or each semiconductor power element.

本発明は、上記に鑑みて為されたもので、その目的は、比較的簡単な回路構成で、且つ検出誤差の少ない方法によって装置出力の直流成分を検出し、これを補償する機能を有するインバータ装置を提供することを目的とする。   The present invention has been made in view of the above, and an object of the present invention is to provide an inverter having a relatively simple circuit configuration and a function of detecting and compensating for a DC component of a device output by a method having a small detection error. An object is to provide an apparatus.

上記目的を達成するため、本発明のインバータ装置は、ブリッジ接続した半導体電力素子で構成され、直流電力を交流電力に変換するインバータ回路と、電圧指令に応じて前記インバータ回路の出力電圧を制御する制御部と、前記インバータ回路の出力の相電圧を検出する相電圧検出手段と、この相電圧検出手段の出力を受け、前記インバータ回路を構成する半導体電力素子の正側及び負側の導通時間を検出する導通時間検出手段とを具備し、
前記制御部は、前記導通時間検出手段によって得られる正側導通時間と負側導通時間の差分の積分値に応じて前記電圧指令を補正するようにしたことを特徴としている。
In order to achieve the above object, an inverter device of the present invention comprises a bridge-connected semiconductor power element, and controls an inverter circuit that converts DC power into AC power, and controls an output voltage of the inverter circuit according to a voltage command. A control unit; phase voltage detection means for detecting a phase voltage of the output of the inverter circuit; and an output of the phase voltage detection means, and the conduction time on the positive side and the negative side of the semiconductor power element constituting the inverter circuit. A conduction time detection means for detecting,
The control unit is characterized in that the voltage command is corrected in accordance with an integrated value of a difference between a positive side conduction time and a negative side conduction time obtained by the conduction time detection means.

本発明によれば、比較的簡単な回路構成で、且つ検出誤差の少ない方法によって装置出力の直流成分を検出し、これを補償する機能を有するインバータ装置を提供することが可能となる。   According to the present invention, it is possible to provide an inverter device having a function of detecting and compensating for a DC component of a device output by a method having a relatively simple circuit configuration and a small detection error.

以下、図面を参照して本発明の実施例を説明する。   Embodiments of the present invention will be described below with reference to the drawings.

図1は本発明に係るインバータ装置の実施例1を示す回路構成図である。   FIG. 1 is a circuit configuration diagram showing Embodiment 1 of an inverter device according to the present invention.

インバータ回路1は直流電源から得られる直流を3相交流に変換し、出力フィルタ2を介して負荷3に給電している。ここで、インバータ回路1に給電する直流は、図示したような蓄電池でも良いが、商用電源からコンバータ回路を経由して直流電源を得るようにしても良い。インバータ回路1は半導体電力素子をブリッジ接続して構成されているのが普通である。   The inverter circuit 1 converts a direct current obtained from a direct current power source into a three-phase alternating current and supplies power to the load 3 through the output filter 2. Here, the direct current fed to the inverter circuit 1 may be a storage battery as shown in the figure, but a direct current power source may be obtained from a commercial power source via a converter circuit. The inverter circuit 1 is normally configured by connecting semiconductor power elements in a bridge connection.

負荷3の入力電圧は各相毎に電圧検出器5によって検出され、インバータ制御回路4にフィードバックされている。インバータ制御回路4では、このフィードバック電圧と各相の電圧指令を比較器41で夫々比較し、その差分を電圧増幅器42を介してPWM制御器43に与える。PWM制御器43は電圧増幅器42の出力をキャリア発生回路44の出力と比較し、これにより各相毎の駆動パルスを得、この駆動パルスをインバータ回路1の各アームの半導体電力素子のゲートに供給する。   The input voltage of the load 3 is detected by the voltage detector 5 for each phase and fed back to the inverter control circuit 4. In the inverter control circuit 4, the feedback voltage and the voltage command for each phase are compared by the comparator 41, and the difference is given to the PWM controller 43 via the voltage amplifier 42. The PWM controller 43 compares the output of the voltage amplifier 42 with the output of the carrier generation circuit 44, thereby obtaining a drive pulse for each phase, and supplying this drive pulse to the gate of the semiconductor power element of each arm of the inverter circuit 1. To do.

インバータ回路1の出力には相電圧分圧回路6が接続され、この相電圧分圧回路6により各相の瞬時電圧が検出される。即ち、インバータ回路1の出力を各相毎に分圧抵抗61、分圧抵抗62及び分圧抵抗63を介し、ダイオードコンバータ回路64に供給する。ダイオードコンバータ回路64の出力は、その中点が接地された電解コンデンサ65A及び電解コンデンサ65Bの直列回路に接続されている。電解コンデンサ65A及び電解コンデンサ65Bには夫々抵抗66A及び66Bが並列に接続されている。   A phase voltage dividing circuit 6 is connected to the output of the inverter circuit 1, and the instantaneous voltage of each phase is detected by the phase voltage dividing circuit 6. That is, the output of the inverter circuit 1 is supplied to the diode converter circuit 64 through the voltage dividing resistor 61, the voltage dividing resistor 62, and the voltage dividing resistor 63 for each phase. The output of the diode converter circuit 64 is connected to a series circuit of an electrolytic capacitor 65A and an electrolytic capacitor 65B whose midpoint is grounded. Resistors 66A and 66B are connected in parallel to the electrolytic capacitor 65A and the electrolytic capacitor 65B, respectively.

分圧抵抗62の両端の電圧は正/負アームオン時間検出回路7に与えられる。正/負アームオン時間検出回路7において、分圧抵抗62の両端の電圧は、正側フォトダイオード71A及び正側フォトトランジスタ72Aで構成されるフォトカップラと、負側フォトダイオード71B及び負側フォトトランジスタ72Bで構成されるフォトカップラのフォトダイオード側に並列に接続される。このように構成することにより、正側フォトトランジスタ72Aは、インバータ回路1の対象とする相の正側アームのオン時間に1を出力し、負側フォトトランジスタ72Bは、インバータ回路1の対象とする相の負側アームのオン時間に1を出力する。   The voltage across the voltage dividing resistor 62 is applied to the positive / negative arm on time detection circuit 7. In the positive / negative arm on-time detection circuit 7, the voltage across the voltage dividing resistor 62 is a photocoupler composed of a positive side photodiode 71A and a positive side phototransistor 72A, a negative side photodiode 71B, and a negative side phototransistor 72B. Are connected in parallel to the photodiode side of the photocoupler. With this configuration, the positive side phototransistor 72A outputs 1 during the on-time of the positive side arm of the target phase of the inverter circuit 1, and the negative side phototransistor 72B is the target of the inverter circuit 1. 1 is output during the on-time of the negative arm of the phase.

正側フォトトランジスタ72A及び負側フォトトランジスタ72Bの出力、即ち正/負アームオン時間検出回路7の出力はオン時間差演算回路8に与えられる。オン時間差演算回路8内の比較器81は、正/負アームオン時間検出回路7の正側及び負側の出力を受け、対象相の正側オン時間と負側オン時間の差分を抽出して積分器82に与える。積分器82で積分された出力は、オフセット補正信号としてインバータ制御回路4の比較器41に与えられる。   The outputs of the positive side phototransistor 72A and the negative side phototransistor 72B, that is, the output of the positive / negative arm on time detection circuit 7 are supplied to the on time difference calculation circuit 8. The comparator 81 in the on-time difference calculation circuit 8 receives the positive and negative outputs of the positive / negative arm on-time detection circuit 7, extracts the difference between the positive on-time and the negative on-time of the target phase, and integrates it. To the vessel 82. The output integrated by the integrator 82 is given to the comparator 41 of the inverter control circuit 4 as an offset correction signal.

以上の回路構成における本発明のインバータ装置の動作について以下説明する。   The operation of the inverter device of the present invention in the above circuit configuration will be described below.

例えば、インバータ回路1のR相出力に直結した半導体電力素子の上下アーム導通時間の均衡が崩れて、R相電圧に直流オフセットが印加された場合を想定する。この場合、相電圧分圧回路6のR相に対応する分圧抵抗62からR相電圧を分圧し、フォトダイオード71A及び71BによってR相電圧の正及び負アームのオン時間を夫々検出する。直流オフセットがある場合は、この正側アームオン時間と負側アームオン時間に差が生ずる。積分器82により、このオン時間差を積分し、R相出力相電圧が+方向にオフセットがある場合は+値を出力し、−方向にある場合は−値を出力する。インバータ制御回路4のR相の電圧指令値からこの積分値を減算することにより、R相出力相電圧オフセット補償が行われる。   For example, a case is assumed in which the balance between the upper and lower arm conduction times of the semiconductor power element directly connected to the R-phase output of the inverter circuit 1 is lost and a DC offset is applied to the R-phase voltage. In this case, the R phase voltage is divided from the voltage dividing resistor 62 corresponding to the R phase of the phase voltage dividing circuit 6, and the positive and negative arm on-times of the R phase voltage are detected by the photodiodes 71A and 71B, respectively. When there is a DC offset, a difference occurs between the positive arm on time and the negative arm on time. The integrator 82 integrates this on-time difference, and outputs a positive value when the R-phase output phase voltage has an offset in the positive direction, and outputs a negative value when it is in the negative direction. By subtracting this integral value from the R-phase voltage command value of the inverter control circuit 4, R-phase output phase voltage offset compensation is performed.

以上はR相についての説明であるが、S相及またはT相に直流オフセットがある場合も全く同様である。   The above is a description of the R phase, but the same applies when there is a DC offset in the S and T phases.

図2は本発明に係るインバータ装置の実施例2を示す回路構成図である。   FIG. 2 is a circuit configuration diagram showing Embodiment 2 of the inverter device according to the present invention.

この実施例2の各部について、図1の実施例1に係るインバータ装置の各部と同一部分は同一符号で示し、その説明を省略する。この実施例2が実施例1と異なる点は、電圧検出用として分圧抵抗62A及び分圧抵抗62Bの直列回路を形成して相電圧分圧回路6Aを構成するようにした点、またフォトダイオード71Aに直列にシャントレギュレータ73Aを、フォトダイオード71Bに直列にシャントレギュレータ73Bを設け、各々のシャントレギュレータの基準電圧端子に上述の分圧抵抗62Aと分圧抵抗62Bの中点を接続し、分圧抵抗62Aの両端の電圧が所定値以上となったときシャントレギュレータ73Aをオンさせ、分圧抵抗62Bの両端の電圧が所定値以上となったときシャントレギュレータ73BAをオンさせるように正/負アームオン時間検出回路7Aを構成するようにした点である。   About each part of this Example 2, the same part as each part of the inverter apparatus which concerns on Example 1 of FIG. 1 is shown with the same code | symbol, and the description is abbreviate | omitted. The second embodiment is different from the first embodiment in that a phase voltage dividing circuit 6A is configured by forming a series circuit of a voltage dividing resistor 62A and a voltage dividing resistor 62B for voltage detection, and a photodiode. A shunt regulator 73A is provided in series with 71A, and a shunt regulator 73B is provided in series with the photodiode 71B. The midpoint of the voltage dividing resistor 62A and the voltage dividing resistor 62B is connected to the reference voltage terminal of each shunt regulator. Positive / negative arm on time so that the shunt regulator 73A is turned on when the voltage across the resistor 62A exceeds a predetermined value, and the shunt regulator 73BA is turned on when the voltage across the voltage dividing resistor 62B exceeds a predetermined value. The detection circuit 7A is configured.

例えばR相正方向の所定の出力電圧に対し、分圧抵抗62Aを2.5V以上の電圧を背負う分圧抵抗とし、R相負方向の所定の出力電圧に対し、分圧抵抗62Bを2.5V以上の電圧を背負う分圧抵抗とすると、シャントレギュレータ73Aは分圧抵抗62Aの両端電圧が2.5V以上になったとき、カソード極からアノード極へ電流が流れ、シャントレギュレータ73Bは分圧抵抗62Bの両端電圧が2.5V以上になったとき、カソード極からアノード極へ電流が流れる。これにより、フォトダイオード71Aあるいはフォトダイオード71Bに電流が流れ、R相の正側アームオン時間またはR相の負側アームオン時間が検出可能となる。   For example, with respect to a predetermined output voltage in the R-phase positive direction, the voltage dividing resistor 62A is a voltage dividing resistor that bears a voltage of 2.5 V or more. Assuming that the voltage dividing resistor carrying a voltage of 5V or more is used, the shunt regulator 73A has a current flowing from the cathode electrode to the anode electrode when the voltage across the voltage dividing resistor 62A is 2.5V or more, and the shunt regulator 73B is a voltage dividing resistor. When the voltage at both ends of 62B becomes 2.5 V or more, a current flows from the cathode electrode to the anode electrode. As a result, a current flows through the photodiode 71A or the photodiode 71B, and the R-phase positive side arm-on time or the R-phase negative side arm-on time can be detected.

このように、正/負アームオン時間検出回路7Aが、所定の電圧レベル以上の電圧で動作するように構成すれば、より耐ノイズ性の強い、バラツキの少ない出力相電圧の正負時間を認識できるため、より信頼性の高い出力相電圧オフセット補償が実現できる。   In this way, if the positive / negative arm on time detection circuit 7A is configured to operate at a voltage higher than a predetermined voltage level, the positive / negative time of the output phase voltage with higher noise resistance and less variation can be recognized. Therefore, more reliable output phase voltage offset compensation can be realized.

本発明に係るインバータ装置の実施例1を示す回路構成図。The circuit block diagram which shows Example 1 of the inverter apparatus which concerns on this invention. 本発明に係るインバータ装置の実施例2を示す回路構成図。The circuit block diagram which shows Example 2 of the inverter apparatus which concerns on this invention.

符号の説明Explanation of symbols

1 インバータ
2 出力フィルタ
3 負荷
4 インバータ制御回路
41 比較器
42 電圧増幅器
43 PWM制御器
44 キャリア発生回路
5 電圧検出器
6 相電圧分圧回路
61、62、62A、62B、63 分圧抵抗
64 ダイオードコンバータ回路
65A、65B 電解コンデンサ
66A、66B 抵抗
7 正/負アームオン時間検出回路
71A、71B フォトダイオード
72A、72B フォトトランジスタ
73A、73B シャントレギュレータ
8 オン時間差演算回路
81 比較器
82 積分器

DESCRIPTION OF SYMBOLS 1 Inverter 2 Output filter 3 Load 4 Inverter control circuit 41 Comparator 42 Voltage amplifier 43 PWM controller 44 Carrier generation circuit 5 Voltage detector 6 Phase voltage dividing circuit 61, 62, 62A, 62B, 63 Voltage dividing resistor 64 Diode converter Circuits 65A, 65B Electrolytic capacitors 66A, 66B Resistor 7 Positive / negative arm on time detection circuits 71A, 71B Photodiodes 72A, 72B Phototransistors 73A, 73B Shunt regulator 8 On time difference calculation circuit 81 Comparator 82 Integrator

Claims (5)

ブリッジ接続した半導体電力素子で構成され、直流電力を交流電力に変換するインバータ回路と、
電圧指令に応じて前記インバータ回路の出力電圧を制御する制御部と、
前記インバータ回路の出力の相電圧を検出する相電圧検出手段と、
この相電圧検出手段の出力を受け、前記インバータ回路を構成する半導体電力素子の正側及び負側の導通時間を検出する導通時間検出手段と
を具備し、
前記制御部は、
前記導通時間検出手段によって得られる正側導通時間と負側導通時間の差分の積分値に応じて前記電圧指令を補正するようにしたことを特徴とするインバータ装置。
An inverter circuit configured by bridge-connected semiconductor power elements, which converts DC power into AC power;
A control unit for controlling the output voltage of the inverter circuit in response to a voltage command;
Phase voltage detection means for detecting the phase voltage of the output of the inverter circuit;
Receiving the output of this phase voltage detection means, comprising a conduction time detection means for detecting the conduction time of the positive side and the negative side of the semiconductor power element constituting the inverter circuit,
The controller is
An inverter device, wherein the voltage command is corrected according to an integral value of a difference between a positive side conduction time and a negative side conduction time obtained by the conduction time detection means.
前記相電圧検出手段は、
前記インバータ回路の出力電圧を整流するダイオード回路と、
前記ダイオード回路の出力電圧を平滑する2直列のコンデンサと、
前記2直列のコンデンサに夫々並列接続される抵抗器と、
前記インバータ回路の出力と前記ダイオード回路の入力の間に各相毎に直列接続される複数個の分圧抵抗とを備え、
前記複数個の分圧抵抗のうち少なくとも1個の分圧抵抗を相電圧検出用分圧抵抗とし、
この相電圧検出用分圧抵抗に印加される電圧により相電圧を検出するようにしたことを特徴とする請求項1に記載のインバータ装置。
The phase voltage detecting means includes
A diode circuit for rectifying the output voltage of the inverter circuit;
Two series capacitors for smoothing the output voltage of the diode circuit;
Resistors connected in parallel to the two series capacitors,
A plurality of voltage dividing resistors connected in series for each phase between the output of the inverter circuit and the input of the diode circuit,
At least one voltage dividing resistor among the plurality of voltage dividing resistors is used as a phase voltage detecting voltage dividing resistor,
2. The inverter device according to claim 1, wherein the phase voltage is detected by a voltage applied to the voltage dividing resistor for phase voltage detection.
前記導通時間検出手段は、
前記相電圧検出用分圧抵抗に2つのフォトカプラを逆並列に接続し、
この2つのフォトカプラの出力により前記半導体電力素子の正側及び負側の導通時間を検出するようにしたことを特徴とする請求項2に記載のインバータ装置。
The conduction time detecting means includes
Two photocouplers are connected in antiparallel to the voltage dividing resistor for phase voltage detection,
3. The inverter device according to claim 2, wherein the conduction times on the positive side and the negative side of the semiconductor power element are detected from the outputs of the two photocouplers.
前記導通時間検出手段は、
前記相電圧検出手段によって得られる前記インバータ回路の出力電圧が所定値以上のとき前記正側導通時間と見做し、前記インバータ回路の出力電圧が所定値以下のとき前記負側導通時間と見做すようにしたことを特徴とする請求項1に記載のインバータ装置。
The conduction time detecting means includes
When the output voltage of the inverter circuit obtained by the phase voltage detection means is equal to or higher than a predetermined value, the positive conduction time is considered, and when the output voltage of the inverter circuit is lower than a predetermined value, the negative conduction time is considered. The inverter device according to claim 1, wherein the inverter device is configured as described above.
前記導通時間検出手段は、
前記相電圧検出用分圧抵抗に逆並列に接続した2つのシャントレギュレータと通時間検出用フォトカプラとの直列回路を備え、
前記相電圧検出用分圧抵抗の中点を前記2つのシャントレギュレータの基準電圧端子に接続し、
前記通時間検出用フォトカプラの出力により前記半導体電力素子の正側及び負側の導通時間を検出するようにしたことを特徴とする請求項2に記載のインバータ装置。

The conduction time detecting means includes
A series circuit of two shunt regulators connected in antiparallel to the voltage dividing resistor for phase voltage detection and a photocoupler for time detection;
A midpoint of the phase voltage detecting voltage dividing resistor is connected to a reference voltage terminal of the two shunt regulators;
3. The inverter device according to claim 2, wherein the conduction time on the positive side and the negative side of the semiconductor power element is detected based on the output of the photocoupler for detecting the passage time.

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Publication number Priority date Publication date Assignee Title
WO2021234910A1 (en) * 2020-05-21 2021-11-25 三菱電機株式会社 Power conversion device

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JPS63198581A (en) * 1987-02-12 1988-08-17 Mitsubishi Electric Corp Dc component corrector for inverter output voltage
JPH07337037A (en) * 1994-06-13 1995-12-22 Tokyo Electric Power Co Inc:The Controller for voltage self-excited converter
JPH10248262A (en) * 1998-04-03 1998-09-14 Hitachi Ltd Power conversion device and its control method
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JPS61295877A (en) * 1985-06-24 1986-12-26 Toshiba Corp Pwm inverter
JPS6364574A (en) * 1986-09-02 1988-03-23 Toshiba Corp Control circuit of inverter
JPS63198581A (en) * 1987-02-12 1988-08-17 Mitsubishi Electric Corp Dc component corrector for inverter output voltage
JPH07337037A (en) * 1994-06-13 1995-12-22 Tokyo Electric Power Co Inc:The Controller for voltage self-excited converter
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JP2001286160A (en) * 2000-04-03 2001-10-12 Toshiba Corp Power converter

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021234910A1 (en) * 2020-05-21 2021-11-25 三菱電機株式会社 Power conversion device

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