JP2006012914A - 集積回路チップの製造方法及び半導体装置 - Google Patents

集積回路チップの製造方法及び半導体装置 Download PDF

Info

Publication number
JP2006012914A
JP2006012914A JP2004183961A JP2004183961A JP2006012914A JP 2006012914 A JP2006012914 A JP 2006012914A JP 2004183961 A JP2004183961 A JP 2004183961A JP 2004183961 A JP2004183961 A JP 2004183961A JP 2006012914 A JP2006012914 A JP 2006012914A
Authority
JP
Japan
Prior art keywords
support member
integrated circuit
circuit chip
semiconductor
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004183961A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006012914A5 (https=
Inventor
Kazutaka Momoi
一隆 桃井
Nobuhiko Sato
信彦 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2004183961A priority Critical patent/JP2006012914A/ja
Priority to US11/149,145 priority patent/US7473617B2/en
Publication of JP2006012914A publication Critical patent/JP2006012914A/ja
Publication of JP2006012914A5 publication Critical patent/JP2006012914A5/ja
Priority to US12/328,182 priority patent/US20090085196A1/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1922—Preparing SOI wafers using silicon etch back techniques, e.g. BESOI or ELTRAN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7412—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7422—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Landscapes

  • Recrystallisation Techniques (AREA)
  • Dicing (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
JP2004183961A 2004-06-22 2004-06-22 集積回路チップの製造方法及び半導体装置 Pending JP2006012914A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2004183961A JP2006012914A (ja) 2004-06-22 2004-06-22 集積回路チップの製造方法及び半導体装置
US11/149,145 US7473617B2 (en) 2004-06-22 2005-06-10 Integrated circuit chip manufacturing method and semiconductor device
US12/328,182 US20090085196A1 (en) 2004-06-22 2008-12-04 Integrated circuit chip manufaturing method and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004183961A JP2006012914A (ja) 2004-06-22 2004-06-22 集積回路チップの製造方法及び半導体装置

Publications (2)

Publication Number Publication Date
JP2006012914A true JP2006012914A (ja) 2006-01-12
JP2006012914A5 JP2006012914A5 (https=) 2007-08-02

Family

ID=35479776

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004183961A Pending JP2006012914A (ja) 2004-06-22 2004-06-22 集積回路チップの製造方法及び半導体装置

Country Status (2)

Country Link
US (2) US7473617B2 (https=)
JP (1) JP2006012914A (https=)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010021398A (ja) * 2008-07-11 2010-01-28 Disco Abrasive Syst Ltd ウェーハの処理方法
JP2010267639A (ja) * 2009-05-12 2010-11-25 Disco Abrasive Syst Ltd 半導体ウエーハの加工方法
JP2011243903A (ja) * 2010-05-21 2011-12-01 Disco Abrasive Syst Ltd ウエーハの加工方法
JP2012195503A (ja) * 2011-03-17 2012-10-11 Lintec Corp 薄型半導体装置の製造方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005210062A (ja) * 2003-12-26 2005-08-04 Canon Inc 半導体部材とその製造方法、及び半導体装置
JP5993845B2 (ja) 2010-06-08 2016-09-14 ヘンケル アイピー アンド ホールディング ゲゼルシャフト ミット ベシュレンクテル ハフツング 先ダイシング法を行う微細加工されたウェーハへの接着剤の被覆
TWI456012B (zh) 2010-06-08 2014-10-11 漢高智慧財產控股公司 使用脈衝式ｕｖ光源之晶圓背面塗覆方法
US9245760B2 (en) 2010-09-30 2016-01-26 Infineon Technologies Ag Methods of forming epitaxial layers on a porous semiconductor layer
JP2014511559A (ja) 2011-02-01 2014-05-15 ヘンケル コーポレイション プレカットされウェハに塗布されるアンダーフィル膜
EP2671248A4 (en) 2011-02-01 2015-10-07 Henkel Corp ON A PRECUTED WAFER APPLIED FILM ON A DICING TAPE
US9627287B2 (en) * 2013-10-18 2017-04-18 Infineon Technologies Ag Thinning in package using separation structure as stop

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1174230A (ja) * 1997-08-29 1999-03-16 Nippon Telegr & Teleph Corp <Ntt> 薄膜半導体装置の製造方法
JP2000223446A (ja) * 1998-11-27 2000-08-11 Denso Corp 半導体装置およびその製造方法
JP2001057348A (ja) * 1999-08-18 2001-02-27 Seiko Epson Corp 半導体チップの製造方法、半導体装置、回路基板ならびに電子機器
JP2001135742A (ja) * 1999-11-01 2001-05-18 Toppan Printing Co Ltd 半導体装置の製造方法
JP2002231909A (ja) * 2001-01-31 2002-08-16 Canon Inc 薄膜半導体装置の製造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998013862A1 (fr) * 1996-09-24 1998-04-02 Mitsubishi Denki Kabushiki Kaisha Dispositif a semi-conducteur et son procede de fabrication
JP3144387B2 (ja) 1998-08-17 2001-03-12 日本電気株式会社 半導体装置の製造方法
US6337228B1 (en) * 1999-05-12 2002-01-08 Amkor Technology, Inc. Low-cost printed circuit board with integral heat sink for semiconductor package
US6774010B2 (en) 2001-01-25 2004-08-10 International Business Machines Corporation Transferable device-containing layer for silicon-on-insulator applications
JP2002229473A (ja) * 2001-01-31 2002-08-14 Canon Inc 表示装置の製造方法
US6638835B2 (en) 2001-12-11 2003-10-28 Intel Corporation Method for bonding and debonding films using a high-temperature polymer
US6841413B2 (en) * 2002-01-07 2005-01-11 Intel Corporation Thinned die integrated circuit package
EP1491854A4 (en) * 2002-04-02 2006-11-02 Asahi Kasei Emd Corp INCLINATION SENSOR, METHOD FOR MANUFACTURING THE INCLINATION SENSOR, AND METHOD FOR MEASURING THE INCLINATION
JP2003323132A (ja) 2002-04-30 2003-11-14 Sony Corp 薄膜デバイスの製造方法および半導体装置
US7105448B2 (en) * 2003-02-28 2006-09-12 Semiconductor Energy Laboratory Co., Ltd. Method for peeling off semiconductor element and method for manufacturing semiconductor device
JP2005210062A (ja) * 2003-12-26 2005-08-04 Canon Inc 半導体部材とその製造方法、及び半導体装置
US20060124961A1 (en) * 2003-12-26 2006-06-15 Canon Kabushiki Kaisha Semiconductor substrate, manufacturing method thereof, and semiconductor device
JP2005191457A (ja) 2003-12-26 2005-07-14 Canon Inc 半導体基体とその作製方法、半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1174230A (ja) * 1997-08-29 1999-03-16 Nippon Telegr & Teleph Corp <Ntt> 薄膜半導体装置の製造方法
JP2000223446A (ja) * 1998-11-27 2000-08-11 Denso Corp 半導体装置およびその製造方法
JP2001057348A (ja) * 1999-08-18 2001-02-27 Seiko Epson Corp 半導体チップの製造方法、半導体装置、回路基板ならびに電子機器
JP2001135742A (ja) * 1999-11-01 2001-05-18 Toppan Printing Co Ltd 半導体装置の製造方法
JP2002231909A (ja) * 2001-01-31 2002-08-16 Canon Inc 薄膜半導体装置の製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010021398A (ja) * 2008-07-11 2010-01-28 Disco Abrasive Syst Ltd ウェーハの処理方法
JP2010267639A (ja) * 2009-05-12 2010-11-25 Disco Abrasive Syst Ltd 半導体ウエーハの加工方法
JP2011243903A (ja) * 2010-05-21 2011-12-01 Disco Abrasive Syst Ltd ウエーハの加工方法
JP2012195503A (ja) * 2011-03-17 2012-10-11 Lintec Corp 薄型半導体装置の製造方法

Also Published As

Publication number Publication date
US7473617B2 (en) 2009-01-06
US20090085196A1 (en) 2009-04-02
US20050280119A1 (en) 2005-12-22

Similar Documents

Publication Publication Date Title
JP4803884B2 (ja) 薄膜半導体装置の製造方法
JP4708577B2 (ja) 薄膜半導体装置の製造方法
US20090085196A1 (en) Integrated circuit chip manufaturing method and semiconductor device
US7691730B2 (en) Large area semiconductor on glass insulator
US9034732B2 (en) Semiconductor-on-insulator with back side support layer
CN102208438B (zh) 近乎无衬底的复合功率半导体器件及其方法
JP2004512688A (ja) ＧａＮベースの半導体デバイスを製造する方法
US9824927B2 (en) Methods for producing semiconductor devices
TW201342494A (zh) 用於半導體裝置的製造之合成晶圓
US8198172B2 (en) Methods of forming integrated circuits using donor and acceptor substrates
US9496227B2 (en) Semiconductor-on-insulator with back side support layer
JPH09312349A (ja) 薄膜半導体装置およびｉｃカードの製造方法
CN103094206B (zh) 利用材料改性分离半导体裸片的方法
CN107564857B (zh) 晶圆级切割方法、封装方法及封装结构
JP5425122B2 (ja) 薄膜半導体装置の製造方法
JP2007266044A (ja) 半導体装置の製造方法
JP2001320033A (ja) 半導体部材の製造方法およびそれを用いた半導体部材、半導体装置
JP2005347301A (ja) 基板の作製方法
JP4545449B2 (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070618

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070618

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20070618

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090903

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090911

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091110

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100205

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100405

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20100614