JP2006012903A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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JP2006012903A
JP2006012903A JP2004183848A JP2004183848A JP2006012903A JP 2006012903 A JP2006012903 A JP 2006012903A JP 2004183848 A JP2004183848 A JP 2004183848A JP 2004183848 A JP2004183848 A JP 2004183848A JP 2006012903 A JP2006012903 A JP 2006012903A
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gate electrode
resist
manufacturing
semiconductor substrate
semiconductor element
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Atsushi Hasuike
篤 蓮池
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2004183848A priority Critical patent/JP2006012903A/en
Priority to US10/986,225 priority patent/US20050282320A1/en
Publication of JP2006012903A publication Critical patent/JP2006012903A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H01L29/8124—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate with multiple gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • H01L21/28593—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T asymmetrical sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can shorten a gate length by inclining a gate electrode by a simple method. <P>SOLUTION: First, the gate electrode 15 is formed on a semiconductor substrate 11. Then, a resist 16 is so formed as to be brought into contact with only one side face of the gate electrode on the semiconductor substrate. By contracting or expanding the resist, the gate electrode is inclined. It is preferred that the gate electrode has a Γ-, T-, or Y-shaped cross section. It is also preferred that the gate electrode is inclined toward the source side. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体素子を高周波化することができる半導体素子の製造方法に関するものである。   The present invention relates to a method of manufacturing a semiconductor element that can increase the frequency of the semiconductor element.

半導体素子を高周波化するには、ゲート長を短縮し、遮断周波数を大きくすることが最も有効な手段である。しかし、現在のＥＢ（electron beam）露光技術ではゲート長の短縮には限界があり、ゲート長が0.1μｍ程度のゲート電極の製造は困難である。   In order to increase the frequency of semiconductor elements, the most effective means is to shorten the gate length and increase the cutoff frequency. However, the current EB (electron beam) exposure technique has a limit in shortening the gate length, and it is difficult to manufacture a gate electrode having a gate length of about 0.1 μm.

そのため、従来のMESFET(Metal Semiconductor Field Effect Transistor)やHEMT（High Electron Mobility Transistor）では100GHzを越える高周波化は困難であった。   Therefore, conventional MESFET (Metal Semiconductor Field Effect Transistor) and HEMT (High Electron Mobility Transistor) have been difficult to increase the frequency beyond 100 GHz.

これに対し、ゲート電極を斜めに形成することでゲート長を短縮する方法が提案されている（例えば、特許文献１〜３参照）。   On the other hand, a method of shortening the gate length by forming the gate electrode obliquely has been proposed (see, for example, Patent Documents 1 to 3).

特開平５−１２９３４３JP-A-5-129343 特開平１１−１１１７３３JP 11-1111733 A 特開平５−１４４８４７JP-A-5-144847

しかし、従来の半導体素子の製造方法では、ゲート電極を斜めに形成するために製造工程が複雑になるという問題があった。   However, the conventional method of manufacturing a semiconductor device has a problem that the manufacturing process is complicated because the gate electrode is formed obliquely.

本発明は、上述のような課題を解決するためになされたもので、その目的は、簡単な方法によりゲート電極を斜めに傾け、ゲート長を短縮することができる半導体素子の製造方法を得るものである。   The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a method of manufacturing a semiconductor device that can tilt a gate electrode obliquely and shorten a gate length by a simple method. It is.

本発明に係る半導体素子の製造方法は、半導体基板上にゲート電極を形成する工程と、半導体基板上にゲート電極の一方の側面のみに接触するようにレジストを形成する工程と、レジストを収縮又は膨張させることによりゲート電極を傾ける工程とを有する。本発明のその他の特徴は以下に明らかにする。   A method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate electrode on a semiconductor substrate, a step of forming a resist on the semiconductor substrate so as to contact only one side surface of the gate electrode, And inclining the gate electrode by expanding. Other features of the present invention will become apparent below.

本発明により、簡単な方法によりゲート電極を斜めに傾け、ゲート長を短縮することができる。また、これに伴って、遮断周波数を大きくすることができ、半導体素子を高周波化することができる。   According to the present invention, the gate length can be reduced by tilting the gate electrode by a simple method. Along with this, the cutoff frequency can be increased, and the semiconductor element can be increased in frequency.

実施の形態１．
本発明の実施の形態１に係る半導体素子の製造方法について図１〜図４を用いて説明する。 Embodiment 1 FIG.
A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.

まず、図１（ａ）に示すように、ＧａＡｓ等からなる半導体基板１１上に、ＳｉＮ等からなる絶縁膜１２を形成する。そして、ＥＢ又はフォトリソグラフィにより絶縁膜１２に開口１３を形成する。   First, as shown in FIG. 1A, an insulating film 12 made of SiN or the like is formed on a semiconductor substrate 11 made of GaAs or the like. Then, an opening 13 is formed in the insulating film 12 by EB or photolithography.

次に、図１（ｂ）に示すように、全面にＡｌ等の金属膜１４を形成して開口１３を埋め込む。そして、図１（ｃ）に示すように、フォトリソグラフィにより金属膜１４をパターニングして、断面形状がΓ型のゲート電極１５を形成する。その後、図１（ｄ）に示すように、絶縁膜１２は除去する。以上の工程により、半導体基板上にゲート電極を形成する。   Next, as shown in FIG. 1B, a metal film 14 made of Al or the like is formed on the entire surface to fill the opening 13. Then, as shown in FIG. 1C, the metal film 14 is patterned by photolithography to form a gate electrode 15 having a Γ type cross-sectional shape. Thereafter, as shown in FIG. 1D, the insulating film 12 is removed. Through the above steps, a gate electrode is formed on the semiconductor substrate.

次に、図２（ａ）に示すように、半導体基板１１上の全面にレジスト１６を形成する。そして、露光及び現像工程により、図２（ｂ）に示すように、ゲート電極１５の一方の側面に接触する部分のみ残してレジスト１６を除去する。以上の工程により、半導体基板上にゲート電極の一方の側面のみに接触するようにレジストを形成する。ただし、レジスト１６として、熱処理又は化学処理により収縮又は膨張する材料を用いる。   Next, as shown in FIG. 2A, a resist 16 is formed on the entire surface of the semiconductor substrate 11. Then, as shown in FIG. 2B, the resist 16 is removed by the exposure and development processes, leaving only the portion in contact with one side surface of the gate electrode 15. Through the above steps, a resist is formed on the semiconductor substrate so as to contact only one side surface of the gate electrode. However, as the resist 16, a material that contracts or expands by heat treatment or chemical treatment is used.

次に、熱処理又は化学処理により、図３に示すようにレジスト１６を収縮させるか、又は、図４に示すようにレジスト１６を膨張させることにより、ゲート電極１５を傾ける。   Next, the resist 16 is contracted as shown in FIG. 3 by heat treatment or chemical treatment, or the resist 16 is expanded as shown in FIG. 4 to tilt the gate electrode 15.

以上説明したように、簡単な方法によりゲート電極を斜めに傾け、ゲート長を短縮することができる。また、これに伴って、遮断周波数を大きくすることができ、半導体素子を高周波化することができる。   As described above, the gate length can be shortened by tilting the gate electrode by a simple method. Along with this, the cutoff frequency can be increased, and the semiconductor element can be increased in frequency.

上記の実施の形態１ではゲート電極の断面形状がΓ型の場合について説明したが、ゲート電極の断面形状はこれに限定されず、通常の矩形でも同様の効果を奏する。ただし、ゲート電極の断面形状がΓ型の場合は、ゲート電極の下方にレジストが入り込み、収縮又は膨張の力が入りやすく、より効果的である。   In the first embodiment described above, the case where the cross-sectional shape of the gate electrode is the Γ type has been described. However, the cross-sectional shape of the gate electrode is not limited to this, and the same effect can be obtained even with a normal rectangle. However, when the cross-sectional shape of the gate electrode is Γ type, the resist enters the lower part of the gate electrode, and the force of contraction or expansion is more easily applied, which is more effective.

実施の形態２．
実施の形態１ではゲート電極の断面形状がΓ型であった。これに対し、実施の形態２では図５に示すような断面形状がＴ型のゲート電極１７を用いるか、又は、図６に示すような断面形状がＹ型のゲート電極１８を用いる。このようにゲート電極の断面形状がＴ型又はＹ型の場合も、実施の形態１のようにΓ型の場合と同様に、ゲート電極の下方にレジストが入り込み、収縮又は膨張の力が入りやすい。従って、実施の形態２は、実施の形態１と同様の効果を奏する。 Embodiment 2. FIG.
In the first embodiment, the cross-sectional shape of the gate electrode is Γ type. In contrast, the second embodiment uses a gate electrode 17 having a T-shaped cross section as shown in FIG. 5 or a gate electrode 18 having a Y-shaped cross section as shown in FIG. Thus, even when the cross-sectional shape of the gate electrode is T-type or Y-type, as in the case of the Γ type as in the first embodiment, the resist enters the lower portion of the gate electrode, and the force of contraction or expansion is easily applied. . Therefore, the second embodiment has the same effect as the first embodiment.

実施の形態３．
実施の形態３では、半導体基板１１上にドレイン電極１９とソース電極２０を設け、ゲート電極１５をソース側へ傾ける。これにより、ゲート電極１５の露光位置をソース側へずらさなくても、ドレイン電極１９とゲート電極１５の距離を長くすることができる。従って、ゲートドレイン間容量Ｃｇｄを減少させ、ゲートドレイン間耐圧Ｖｇｄｏを増加させることができる。これにより、半導体素子を高周波化することができるだけでなく、半導体素子を高利得化及び高耐圧化することもできる。 Embodiment 3 FIG.
In the third embodiment, the drain electrode 19 and the source electrode 20 are provided on the semiconductor substrate 11, and the gate electrode 15 is inclined toward the source side. Thus, the distance between the drain electrode 19 and the gate electrode 15 can be increased without shifting the exposure position of the gate electrode 15 to the source side. Therefore, the gate-drain capacitance Cgd can be reduced and the gate-drain breakdown voltage Vgdo can be increased. Thereby, not only the frequency of the semiconductor element can be increased, but also the semiconductor element can have a high gain and a high breakdown voltage.

実施の形態４．
実施の形態４では、図８に示すように、ゲート電極１５のレジストと接触させる側面が上になるように半導体基板１１を傾けた状態でレジスト１６を形成する。これにより、ゲート電極１５の上に向けた側面に接触するようにレジスト１６を塗布又は残留させ易くなる。 Embodiment 4 FIG.
In the fourth embodiment, as shown in FIG. 8, the resist 16 is formed in a state where the semiconductor substrate 11 is tilted so that the side surface of the gate electrode 15 in contact with the resist faces upward. This makes it easier to apply or leave the resist 16 in contact with the side surface facing the gate electrode 15.

特に、ゲート電極１５の窪み部分を上方に向けることで、レジスト１６を窪み部分のみに塗布又は残留させ易くなる。   In particular, by directing the recessed portion of the gate electrode 15 upward, the resist 16 can be easily applied or left only in the recessed portion.

実施の形態５．
実施の形態５では、図９に示すように、傾けたゲート電極１５を覆うようにレジスト材２１を塗布する。そして、このレジスト材２１上にパッシベーション膜２２を形成する。 Embodiment 5. FIG.
In the fifth embodiment, as shown in FIG. 9, a resist material 21 is applied so as to cover the inclined gate electrode 15. Then, a passivation film 22 is formed on the resist material 21.

これにより、傾けたゲート電極の付着強度を向上することができる。また、レジスト材を塗布したことでパッシベーション膜を均一に形成することができる。これによりカバレッジが良くなるため、外界からのデガスや水分によるダメージを受けにくく、耐湿性及び信頼性を向上させることができる。   Thereby, the adhesion strength of the inclined gate electrode can be improved. Further, the passivation film can be uniformly formed by applying the resist material. As a result, the coverage is improved, so that it is difficult to be damaged by degas and moisture from the outside, and the moisture resistance and reliability can be improved.

なお、このレジスト材とパッシベーション膜の構造は、傾きゲート電極以外の通常のゲート電極の半導体素子にも適用することができる。   Note that the structure of the resist material and the passivation film can be applied to a semiconductor element having a normal gate electrode other than the tilted gate electrode.

実施の形態６．
実施の形態６では、図１０に示すように、デュアルゲート２３，２４の間にレジスト１６を形成し、レジスト１６を膨張させることでデュアルゲート２３，２４を外側に傾ける。または、図１１に示すように、デュアルゲート２３，２４の外側にそれぞれレジスト１６を形成し、レジスト１６を収縮させることでデュアルゲート２３，２４を外側に傾ける。 Embodiment 6 FIG.
In the sixth embodiment, as shown in FIG. 10, a resist 16 is formed between the dual gates 23 and 24, and the resist 16 is expanded to incline the dual gates 23 and 24 outward. Alternatively, as shown in FIG. 11, a resist 16 is formed on the outside of the dual gates 23 and 24, respectively, and the resist 16 is contracted to tilt the dual gates 23 and 24 outward.

このように本発明をデュアルゲートに適用した場合でも同様の効果を奏する。また、デュアルゲートを採用することで使用可能なドレイン電流が増加するため、デバイスの高利得化を実現することができる。   Thus, even when the present invention is applied to a dual gate, the same effect can be obtained. Moreover, since the drain current which can be used increases by employ | adopting a dual gate, the high gain of a device is realizable.

実施の形態７．
上記の実施の形態１〜６はレジストの収縮又は膨張によりゲート電極を傾けるものであった。これに対し、実施の形態７は、図１２に示すように、半導体基板１１上に形成された２つの配線２５，２６の間にレジスト１６を設けている。これにより、レジスト１６の収縮又は膨張により配線２５，２６間の容量を調整することができる。なお、２つの配線の代わりに２つの抵抗線の間にレジストを形成してもよい。 Embodiment 7 FIG.
In the first to sixth embodiments described above, the gate electrode is inclined by the contraction or expansion of the resist. On the other hand, in the seventh embodiment, a resist 16 is provided between two wirings 25 and 26 formed on the semiconductor substrate 11 as shown in FIG. Thereby, the capacitance between the wirings 25 and 26 can be adjusted by the contraction or expansion of the resist 16. Note that a resist may be formed between two resistance lines instead of the two wirings.

本発明の実施の形態１に係る半導体素子の製造方法において、ゲート電極を形成する方法を示す断面図である。FIG. 6 is a cross-sectional view showing a method for forming a gate electrode in the method for manufacturing a semiconductor element according to the first embodiment of the present invention. 本発明の実施の形態１に係る半導体素子の製造方法において、レジストを形成する方法を示す断面図である。It is sectional drawing which shows the method to form a resist in the manufacturing method of the semiconductor element which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体素子の製造方法において、レジストを収縮させることによりゲート電極を傾けた状態を示す断面図である。In the manufacturing method of the semiconductor element concerning Embodiment 1 of the present invention, it is a sectional view showing the state where the gate electrode was inclined by shrinking the resist. 本発明の実施の形態１に係る半導体素子の製造方法において、レジストを膨張させることによりゲート電極を傾けた状態示す断面図である。In the manufacturing method of the semiconductor element concerning Embodiment 1 of the present invention, it is a sectional view showing the state where the gate electrode was inclined by expanding the resist. 本発明の実施の形態２に係る半導体素子の製造方法において、Ｔ型のゲート電極を用いた場合を示す断面図である。It is sectional drawing which shows the case where a T-type gate electrode is used in the manufacturing method of the semiconductor element which concerns on Embodiment 2 of this invention. 本発明の実施の形態２に係る半導体素子の製造方法において、Ｙ型のゲート電極を用いた場合を示す断面図である。It is sectional drawing which shows the case where a Y-type gate electrode is used in the manufacturing method of the semiconductor element which concerns on Embodiment 2 of this invention. 本発明の実施の形態３に係る半導体素子の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor element which concerns on Embodiment 3 of this invention. 本発明の実施の形態４に係る半導体素子の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor element which concerns on Embodiment 4 of this invention. 本発明の実施の形態５に係る半導体素子の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor element which concerns on Embodiment 5 of this invention. 本発明の実施の形態６に係る半導体素子の製造方法において、レジストを膨張させることによりゲート電極を傾けた状態示す断面図である。In the manufacturing method of the semiconductor element concerning Embodiment 6 of the present invention, it is a sectional view showing the state where the gate electrode was inclined by expanding the resist. 本発明の実施の形態６に係る半導体素子の製造方法において、レジストを収縮させることによりゲート電極を傾けた状態を示す断面図である。In the manufacturing method of the semiconductor device concerning Embodiment 6 of the present invention, it is a sectional view showing the state where the gate electrode was inclined by shrinking the resist. 本発明の実施の形態７に係る半導体素子の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor element which concerns on Embodiment 7 of this invention.

符号の説明Explanation of symbols

１１ 半導体基板
１５，１７，１８ ゲート電極
１６ レジスト
１９ ドレイン電極
２０ ソース電極
２１ レジスト材
２２ パッシベーション膜
２３，２４ デュアルゲート
２５，２６ 配線
DESCRIPTION OF SYMBOLS 11 Semiconductor substrate 15, 17, 18 Gate electrode 16 Resist 19 Drain electrode 20 Source electrode 21 Resist material 22 Passivation film | membrane 23, 24 Dual gate 25, 26 Wiring

Claims (5)

半導体基板上にゲート電極を形成する工程と、
前記半導体基板上に前記ゲート電極の一方の側面のみに接触するようにレジストを形成する工程と、
前記レジストを収縮又は膨張させることにより前記ゲート電極を傾ける工程とを有することを特徴とする半導体素子の製造方法。 Forming a gate electrode on the semiconductor substrate;
Forming a resist on the semiconductor substrate so as to contact only one side surface of the gate electrode;
And a step of tilting the gate electrode by contracting or expanding the resist. 前記ゲート電極の断面形状をΓ型、Ｔ型又はＹ型とすることを特徴とする請求項１に記載の半導体素子の製造方法。   The method for manufacturing a semiconductor device according to claim 1, wherein a cross-sectional shape of the gate electrode is Γ type, T type, or Y type. 前記ゲート電極をソース側へ傾けることを特徴とする請求項１又は２に記載の半導体素子の製造方法。   The method of manufacturing a semiconductor device according to claim 1, wherein the gate electrode is inclined toward the source side. 前記ゲート電極の前記レジストと接触させる側面が上になるように前記半導体基板を傾けた状態で前記レジストを形成することを特徴とする請求項１〜３の何れか１項に記載の半導体素子の製造方法。   4. The semiconductor element according to claim 1, wherein the resist is formed in a state where the semiconductor substrate is tilted so that a side surface of the gate electrode that contacts the resist faces upward. 5. Production method. 前記傾けたゲート電極を覆うようにレジスト材を塗布する工程と、
前記レジスト材上にパッシベーション膜を形成する工程とを有することを特徴とする請求項１〜４の何れか１項に記載の半導体素子の製造方法。 Applying a resist material to cover the inclined gate electrode;
5. The method of manufacturing a semiconductor element according to claim 1, further comprising: forming a passivation film on the resist material.
JP2004183848A 2004-06-22 2004-06-22 Semiconductor device manufacturing method Pending JP2006012903A (en)

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