JP2010067691A - Compound semiconductor device and method for manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compound semiconductor device and a manufacturing method thereof by which efficiency and reliability can be enhanced by making the resistance of an RF device lower. <P>SOLUTION: The compound semiconductor device includes: a mesa 22 formed on a compound semiconductor substrate; a sidewall 16 formed on the wall surface of the mesa 22 and having a curvature surface; a gate electrode formed on the mesa 22; and a gate metal 18 integrated with the gate electrode and formed on the surface of the sidewall 16. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a compound semiconductor device used for, for example, a high-frequency power device (hereinafter referred to as an RF device) and a manufacturing method thereof.

  In recent years, with the enhancement of functions of inverter circuits and switching elements, further improvement in characteristics is required for field effect transistors (hereinafter referred to as FETs) used as RF devices.

  In such an FET, element isolation is usually performed by forming a mesa on a compound semiconductor substrate. Then, a gate electrode is formed on the mesa, and a gate metal is deposited so as to be connected to a gate pad outside the mesa through a step of the mesa. At this time, the gate metal is formed by DC (direct current) sputtering or EB (Electron Beam) vapor deposition, but there is a possibility that the gate metal may be cut off due to the step of the mesa. Further, the gate metal extends due to the step and a region having a relatively thin film thickness is formed, so that the resistance is increased due to current confinement. In addition, especially when a two-dimensional electron layer having a heterojunction in the mesa and having a high electron concentration is formed, the two-dimensional electron layer exposed on the mesa wall surface is in contact with the gate metal, increasing the leakage current from the gate. It is possible to do. Therefore, a method has been proposed in which the stepped portion is backfilled to form a stepped discontinuous portion (see, for example, Patent Document 1).

However, in order to fill only the step portion with the SiN film or the like, it is necessary to mask the upper portion of the mesa and then peel it off, which causes a problem that the number of steps increases and a step remains due to an alignment error.
Japanese Patent Application No. 2007-251171

  An object of the present invention is to provide a compound semiconductor device capable of improving efficiency and improving reliability by reducing resistance of an RF device, and a manufacturing method thereof.

  According to one aspect of the present invention, a mesa formed on a compound semiconductor substrate, a side wall having a curvature surface formed on a wall surface of the mesa, a gate electrode formed on the mesa, and the gate electrode are integrated. There is provided a compound semiconductor device comprising a gate metal formed on a surface of a side wall.

  According to one aspect of the present invention, a mesa is formed on a compound semiconductor substrate, a mask with a gate region exposed is formed on the top of the mesa, and a continuous insulating film is formed on the gate region, the mask, and the bottom of the mesa. The gate region, the mask and the mesa bottoms are exposed by anisotropically etching the insulating film, and sidewalls having a curvature surface are formed on the mask and mesa wall surfaces, and the gate is formed on the gate region and the sidewalls. There is provided a method of manufacturing a compound semiconductor device characterized by forming a metal.

  According to the compound semiconductor device of one embodiment of the present invention and the manufacturing method thereof, it is possible to achieve high efficiency and high reliability by reducing the resistance of the RF device.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1A shows a cross-sectional view of a HEMT element used in the compound semiconductor device formed according to this embodiment. As shown in the figure, a non-doped GaN layer 11 and an AlGaN layer 12 are sequentially formed on a compound semiconductor substrate (not shown) such as GaN, and has a mesa structure. A source electrode 13 and a drain electrode 14 are formed on the mesa head, and a gate electrode 15 is formed between the source electrode 13 and the drain electrode 14.

  As shown in the cross section AA ′ of FIG. 1A in FIG. 1B, a side wall 16b having a curvature is formed on the side surface of the mesa 22, and two-dimensionally formed at the GaN layer 11, the AlGaN layer 12, and their interfaces. The cross section of the electronic layer 17 is covered. A gate metal 18 integrated with the gate electrode 15 is formed on the side wall 16 and connected to a gate pad (not shown) formed outside.

  Such a HEMT element is formed as follows, for example. First, as shown in FIG. 2A and FIG. 2B, which is a cross section taken along line AA ′, a photoresist is applied on an AlGaN / GaN wafer on which a GaN layer 11 and an AlGaN layer 12 are sequentially formed, and patterning is performed by ordinary lithography. Thus, the mask 21 is formed. At this time, a SiN film, a GaN cap layer, or the like may be formed on the AlGaN layer 12 as a surface protective film.

  Next, as shown in FIG. 3A and FIG. 3B showing the A-A ′ cross section thereof, the mesa 22 is formed by anisotropic dry etching such as RIE (Reactive Ion Etching) using Cl-based gas, for example. By forming the mesa, the cross section of the GaN layer 11, the AlGaN layer 12, and the two-dimensional electron layer 17 formed at the interface between them is exposed on the side surface of the mesa.

Then, after forming the source electrode 14 and the drain electrode 15, as shown in FIG. 4A and FIG. 4B, which is a cross section taken along the line AA ′, the gate electrode is composed of a SiN film, a SiO ₂ film, etc. A mask 24 having an opening 23 for forming is formed.

  Next, as shown in FIG. 5A, an insulating film 25 such as a SiN film is formed so as to cover the opening 23, the mask 24, the side surface of the mesa 22, and the bottom of the mesa 22.

  Then, as shown in FIG. 6A and FIG. 6B which is a cross section taken along line AA ′, the insulating film 25 is etched by anisotropic dry etching such as RIE to expose the bottom of the AlGaN layer 12 and the mesa 22 in the opening 23. At the same time, side walls 16a and 16b having curvatures on the surfaces are formed on the side surfaces of the opening 23 and the mesa 22.

  Further, the gate electrode 16 and the gate metal 18 integrated with the gate electrode 16 are formed in a predetermined region on the opening 23 and the side wall 16 by DC sputtering or EB vapor deposition. At this time, since the side wall 16 has a curvature, a gate metal 18 that is smoothly continuous from the mesa head to the mesa bottom is formed. At this time, the film thickness of the gate metal 18 on the side wall 16 is clearly larger than the film thickness formed on the mesa wall surface etched at an angle of about 90 ° with the substrate surface. In this way, the HEMT element as shown in FIGS. 1 and 2 is formed.

  Thus, by forming the side wall 16 having a curvature below the gate metal 18, the thickness of the gate metal 18 on the mesa wall surface can be increased, and the current due to the disconnection or elongation of the gate metal 18 can be increased. Stenosis can be suppressed. In addition, since the two-dimensional electron layer 17 and the gate metal 18 are insulated by the side wall 16, an increase in leakage current from the gate can be suppressed.

  In this embodiment, a GaN substrate is used as the substrate, but a substrate such as SiC or diamond can be used. Furthermore, each of the GaN layer and the AlGaN layer may be composed of a plurality of compound semiconductor layers. It can also be applied to an FET element having no heterojunction. Also, the carrier is not limited to electrons, and may be holes.

  In addition, this invention is not limited to embodiment mentioned above. Various other modifications can be made without departing from the scope of the invention.

1 is a cross-sectional view illustrating a HEMT element formed according to one embodiment of the present invention. FIG. 1A is a cross-sectional view taken along the line A-A ′ of FIG. 1A. Sectional drawing which shows the manufacturing process of the HEMT element in 1 aspect of this invention. FIG. 2B is a cross-sectional view taken along the line A-A ′ of FIG. 2A. Sectional drawing which shows the manufacturing process of the HEMT element in 1 aspect of this invention. FIG. 3A is a cross-sectional view taken along the line A-A ′ of FIG. 3A. Sectional drawing which shows the manufacturing process of the HEMT element in 1 aspect of this invention. FIG. 4A is a cross-sectional view taken along the line A-A ′ of FIG. 4A. Sectional drawing which shows the manufacturing process of the HEMT element in 1 aspect of this invention. FIG. 5B is a cross-sectional view taken along the line A-A ′ of FIG. 5A. Sectional drawing which shows the manufacturing process of the HEMT element in 1 aspect of this invention. FIG. 6B is a cross-sectional view taken along the line A-A ′ of FIG. 6A.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... GaN layer 12 ... AlGaN layer 13 ... Source electrode 14 ... Drain electrode 15 ... Gate electrode 16 ... Side wall 17 ... Two-dimensional electron layer 18 ... Gate metal 21, 24 ... Mask 22 ... Mesa 23 ... Opening 25 ... Insulating film

Claims (5)

A mesa formed on a compound semiconductor substrate;
A side wall having a curvature surface formed on the wall surface of the mesa;
A gate electrode formed on the mesa;
A compound semiconductor device comprising: a gate metal integrated with the gate electrode and formed on a surface of the side wall.   The compound semiconductor device according to claim 1, wherein a two-dimensional carrier layer exposed on the wall surface of the mesa is covered with the side wall. Forming a mesa on a compound semiconductor substrate,
Forming a mask exposing the gate region on the head of the mesa,
Forming a continuous insulating film on the gate region, on the mask and on the bottom of the mesa;
By anisotropically etching the insulating film, the gate region, the mask, and the bottom of the mesa are exposed, and a sidewall having a curvature surface is formed on the wall surface of the mask and the mesa,
A method of manufacturing a compound semiconductor device, comprising forming a gate metal on the gate region and the side wall.   The method for manufacturing a compound semiconductor device according to claim 3, wherein the two-dimensional carrier layer exposed on the wall surface of the mesa is covered with the side wall.   The method for manufacturing a compound semiconductor device according to claim 3, wherein the side wall is formed in a self-aligned manner.

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