JP2004055677A - Gate electrode of field effect transistor and methodof manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a gate electrode of field effect transistor and a method of manufacturing the same which can provide high frequency characteristic thereof, having the cut-off frequency in the sub-millimeter wave band and low noise characteristics and can also improve the reliability. <P>SOLUTION: A gate electrode has a structure that a plurality of stages of over-hung regions are formed to provide the cross-sectional structure, in which the upper part becomes narrower than the lower part. The method of manufacturing the field effect transistor including the same gate electrode comprises the steps of forming an insulation film on a semiconductor substrate; coating the insulation film with a photosensitive resist used for lift-off process; forming a gate electrode pattern having the shape described above and reaching, in its depth of groove, the insulation film described above to the photosensitive resist; etching the insulation film, multilayer resist coating film and semiconductor substrate surface; forming the gate electrode layer using a beam ray of the gate electrode material; and forming the gate electrode by removing the multilayer resist coating film. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a gate of a high-frequency field effect transistor such as a HEMT (high electron mobility transistor) having a short gate length, a small gate resistance, a cut-off frequency characteristic in a submillimeter wave band, and excellent noise characteristics. The present invention relates to an electrode and a manufacturing method thereof.
[0002]
[Prior art]
HEMTs are known as field effect transistors having high frequency characteristics and excellent low noise characteristics. The cross-sectional structure of the gate electrode is usually a T-shaped structure in order to shorten the gate length and suppress an increase in gate resistance.
[0003]
FIG. 2 is a view showing a first conventional example, and an outline of a manufacturing process thereof is shown below. (For example, "Electron beam lithography process for T- and Γ-shaped gate fabrication using chemically amplified DUV resists and PMMA", Journal of Vacuum Science & Technology B, vol. 17, No. 6, pp. 2507-2511 (1999) )
1) A semiconductor substrate on which an FET or especially a HEMT can be formed is prepared, and a source electrode 5, a drain electrode 6, and a mask layer of a silicon nitride film 14 are formed thereon.
2) After applying the electron beam resist 20, after forming the cross-sectional structure of FIG.
3) As shown in FIG. 2B, the silicon nitride film 14, which is a mask layer, is etched.
4) Next, after removing the electron beam resist 20, a resist layer 21 for a lift-off process is applied, and patterning is performed by an electron beam exposure method to obtain a structure having a cross section shown in FIG.
5) Next, the semiconductor contact layer 7 is recess-etched by wet etching,
6) A thin film layer serving as the gate electrode 9 (there is no number in FIG. 2) is formed by metal vapor deposition to obtain a structure having a cross section shown in FIG. 2D.
7) Next, the transistor is manufactured by peeling off the resist 21 and the metal thin film 22 on the resist by a lift-off method to obtain a structure having a cross section shown in FIG.
In this manufacturing process, since the silicon nitride film 14 having a high relative dielectric constant remains between the gate electrode 9 and the semiconductor contact layer 7 close to the gate electrode, the parasitic capacitance related to the upper part of the gate increases, and No properties were obtained.
[0004]
For this reason, a manufacturing process including a step of removing a silicon nitride film located between a gate electrode and a source or drain electrode is disclosed in, for example, JP-A-10-135240. In a transistor formed by this manufacturing process, it was necessary to use a thin mask layer to shorten the gate length. However, when the mask layer was made thinner, the gate electrode came closer to the source or drain electrode, and the gate electrode was thinned. The parasitic capacitance (between the gate and the source or between the gate and the drain) related to the upper portion becomes large, and also in this case, sufficient frequency characteristics cannot be obtained.
[0005]
Further, a manufacturing process using a two-layer or three-layer resist has been proposed for manufacturing a T-type gate electrode. FIG. 3 is a diagram showing such a second conventional example, and its outline is shown below.
[0006]
In FIG. 3A, a source electrode 5 and a drain electrode 6 are formed on a semiconductor substrate having a structure to be a field-effect transistor, an insulating film is formed thereon as a mask layer, and a lowermost resist layer 3, The intermediate resist layer 2 and the uppermost resist layer 1 are applied respectively. Both of these resist layers are positive resist layers. At this time, a pattern having a width Lh corresponding to the size of the upper portion of the T-type gate is simultaneously exposed with a small exposure amount using an electron beam exposure method, and the uppermost resist layer 1 is exposed using a developing solution capable of high sensitivity development. After the development, the intermediate resist layer 2 is further developed under conditions that enable high-sensitivity development. Next, a pattern having a width Lg corresponding to the gate length is exposed on the lowermost resist layer 3 with a large exposure amount using an electron beam exposure method, and a groove having a width Lg is formed using a developing solution capable of low-sensitivity development. Form. FIG. 3A shows a cross section at this time.
[0007]
Next, as shown in FIG. 3B, the silicon oxide film 4 is dry-etched by RIE (reactive ion etching) with strong anisotropy using the lowermost resist layer 3 as an etching mask, and is patterned. Next, a recess structure is formed in the semiconductor contact layer 7 immediately below the silicon oxide film by isotropic etching. Next, as shown in FIG. 3C, a metal thin film for forming a gate electrode is deposited, and the respective resist layers 1, 2, 3 are removed by a lift-off process.
[0008]
Such a manufacturing process is described in, for example, materials (“Novel high-yield trilayer resist process for 0.1 μm T-gate fabrication”, Journal of Vacuum Science & Technology, Vol. 27, No. 27, Vol. 27, Vol. , (1995)).
[0009]
It is known that the gate length that can be manufactured by this manufacturing process depends on the thickness of the lowermost resist. For this reason, a fabrication process using a thin resist layer has been proposed, but has not been sufficiently effective. Japanese Patent Application Laid-Open No. 6-89907 discloses a manufacturing process in which a notch is formed in the lowermost resist by using a three-layered film of a resist layer, a mask layer, and a resist layer from the side closer to the semiconductor substrate.
[0010]
However, the conventional gate electrode of the field-effect transistor and the method for manufacturing the same have several problems in achieving higher frequency characteristics. For example, in order to realize a transistor capable of obtaining a sufficiently large gain in the sub-millimeter wave band, it is necessary to make the gate length smaller than the conventional one and smaller than 50 nm. When the lowermost resist is made thinner, as described above, there is a problem that the parasitic capacitance is generated and the frequency characteristics are not extended. Therefore, it is necessary to increase the thickness of the lowermost resist to some extent. The ratio ((resist thickness) / (gate length)) increases.
[0011]
In general, when a metal film is formed so as to be embedded in a pattern having a large aspect ratio, the substrate is formed by irradiating a metal beam perpendicular to the substrate. However, even in this case, there are some problems when a pattern having a large aspect ratio is used.
[0012]
[Problems to be solved by the invention]
When a pattern having a large aspect ratio as described above is buried by irradiating it with a metal beam, as shown in FIG. 3, the upper and lower portions of the T-type gate electrode are spatially separated or a cavity is formed therebetween. The connection was inadequate. For this reason, the high-frequency characteristics, the low-noise characteristics, the yield, and the reliability have been deteriorated due to the increase in the gate resistance.
[0013]
The present invention has been proposed in view of the above, and has a high frequency characteristic, a low noise characteristic, a high yield of a field effect transistor having a cutoff frequency in a sub-millimeter wave band, a yield, and a gate electrode of a field effect transistor capable of improving reliability. It is intended to provide a manufacturing method.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, a first aspect of the present invention relates to a gate electrode of a field effect transistor, and has a multi-stage structure in which a cross-sectional structure has a shape in which a lower portion has a narrower width than an upper portion. Is characterized by having an overhang structure.
[0015]
Further, the second invention of the present invention relates to a method for manufacturing a gate electrode of a field effect transistor, wherein an insulating film is formed on a semiconductor substrate when a gate electrode is manufactured by a lift-off method using a multilayer resist coating film. A step of applying a photo resist or an electron beam resist used for lift-off on the insulating film, and the photo resist or the electron beam resist has a cross-sectional structure at least partially lower than the upper portion. Forming a gate electrode pattern having a predetermined planar shape, wherein the gate electrode pattern has a shape having a narrower width and the depth of the groove reaches the insulating film; and a first step of etching the insulating film. An etching step, a second etching step of etching the multilayer resist coating film by an amount corresponding to a predetermined thickness, and a semiconductor substrate. A third etching step of etching the surface by an amount corresponding to a predetermined film thickness, a step of forming a gate electrode layer using a particle beam such as an atomic beam or a molecular beam of a gate electrode material, and a multi-layer resist coating film And forming a gate electrode by removing the same.
[0016]
The third invention of the present invention relates to a method for manufacturing a gate electrode of a field effect transistor. In order to obtain a structure with less disconnection, the gate length is set to Lg, the thickness of the lowermost resist is set to a, and The sum of the thickness of the insulating film formed on the semiconductor substrate and the depth of the surface of the semiconductor substrate etched in the third etching step is b, and the gate electrode formed in the second etching step is When the lateral spread of the lowermost resist in the pattern is x, x> ((a / tan75 °) -Lg / 2) and b <(tan75 ° × Lg / 2) are satisfied. I have.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. As an embodiment, an example in which a HEMT is formed on an InP substrate will be described with reference to FIGS.
[0018]
In FIG. 1A, a source electrode 5 and a drain electrode are formed on a semiconductor substrate having a multilayer structure including an InAlAs buffer layer, an InGaAs channel layer, an InAlAs spacer layer, an InAlAs electron supply layer, an InP etching stopper layer, and an InGaAs contact layer. An electrode 6 is formed, a silicon oxide film 4 having a thickness of about 20 nm is formed thereon as a mask layer, a lowermost resist layer 3 having a thickness of 200 nm, an intermediate resist layer 2 having a thickness of 450 nm, and a thickness = 200 nm of the uppermost resist layer 1 is applied. Both the lowermost resist 3 and the uppermost resist 1 are positive resist ZEPs. The intermediate layer resist 2 is a positive resist PMGI.
[0019]
To form a gate pattern using this resist structure, processing is performed in the following procedure.
1) First, the uppermost resist layer 1 and the intermediate resist layer 2 are exposed using an electron beam exposure method with a small exposure amount so as not to affect the exposure conditions of the lowermost resist 3, and a high-sensitivity development is performed. Develop with a developer that can be used. At this time, the range to be exposed has a size that determines the width of the upper part of the T-type gate.
[0020]
2) Next, the lowermost resist 3 is exposed with a large exposure amount and developed with a low-sensitivity developer. At this time, the exposure range has a size that determines the width of the lower portion of the T-type gate. FIG. 1A shows a cross section at this time.
[0021]
3) Next, as shown in FIG. 1B, the silicon oxide film 4 is dry-etched by RIE (reactive ion etching) with strong anisotropy using the lowermost resist layer 3 as an etching mask, and is patterned. The etching conditions at this time are an etching gas CF ₄ and an etching time of 1 minute.
[0022]
4) Next, as shown in FIG. 1C, a part of the resist is removed by a resist ashing process using oxygen plasma. In this process, ashing (resist etching) proceeds isotropically, so that each resist recedes. At this time, in order to favorably deposit the metal film for forming a gate later, the gate length is set to Lg, the thickness of the lowermost resist is set to a, and the total thickness of the silicon oxide film and the contact layer is set to b. When the lateral spread of the lowermost resist is x, it is preferable that x> ((a / tan75 °) −Lg / 2) and b <(tan75 ° × Lg / 2).
[0023]
5) Next, as shown in FIG. 1D, a recess structure is formed in the contact layer 7 immediately below the silicon oxide film 4 by isotropic etching. In this etching, it is desirable to perform wet etching so that no etching damage remains. The etching condition at this time is a citric acid-based etching solution for 5 minutes.
[0024]
Then, a gate forming metal (Ti (titanium), Pt (platinum), or Au (gold) film is deposited by a highly anisotropic deposition method. And a deposition method using electron beam evaporation, laser ablation, evaporation by heating with a heater, sputtering using a collimator, or the like, and any of these methods may be used.
[0025]
Next, each resist layer is dissolved by an organic solvent and removed. This removal of the gate metal layer deposited on the resist layer and separation from the semiconductor substrate is already well known as a lift-off process.
[0026]
FIG. 4A shows an example of a cross-sectional structure of the gate electrode obtained by the above process. It can be seen that the first overhang 10 and the second overhang 11 are formed. For comparison, FIG. 4B shows an example of a cross-sectional structure of the gate electrode according to the second conventional example.
As described above, the embodiment has been described with respect to the HEMT using InP as a substrate. However, other than the above, GaAs, GaN, SiC, sapphire, Si, Ge, InAs, or the like can be used as the substrate. It is easy to apply the present invention to a field effect transistor such as a MISFET, a MOSFET, and the like.
[0028]
The gate electrode formed as described above has the following characteristics. 1) A structure in which the upper part of the gate electrode and the semiconductor surface are charged and separated can be provided, and the parasitic gate capacitance related to the upper part of the gate can be kept small. 2) Even when the contact portion between the gate electrode and the semiconductor substrate is formed to have a thickness of 50 nm or less, since the width gradually increases upward, the narrowing of the narrowed portion can be suppressed. For this reason, the reliability of the element is improved, and the frequency characteristic and the low noise characteristic are improved by reducing the parasitic resistance value of the gate electrode.
[0029]
【The invention's effect】
Since the present invention has the above-described configuration, the following effects can be obtained.
[0030]
First, in the first invention, the cross-sectional structure of the gate electrode of the field-effect transistor is formed such that the lower portion has a narrower width than the upper portion and has a multistage overhang structure. The parasitic gate capacitance associated with the upper portion can be kept small, the reliability of the device is improved, and the frequency characteristics and low noise characteristics are improved by reducing the gate resistance value.
[0031]
According to a second aspect, in the method for manufacturing a gate electrode of a field effect transistor, a step of forming an insulating film on a semiconductor substrate when manufacturing the gate electrode by a lift-off method using a multilayer resist coating film; A step of applying a photo resist or an electron beam resist to be used for lift-off on the insulating film, and a cross-sectional structure of the photo resist or the electron beam resist, in which at least part of the lower part is narrower at the lower part than at the upper part. A step of forming a gate electrode pattern having a predetermined planar shape, the depth of the groove reaching the insulating film, and a first etching step of etching the insulating film; A second etching step of etching the multi-layer resist coating film by an amount corresponding to a predetermined film thickness; A third etching step of etching corresponding to the thickness of the gate electrode layer, a step of forming a gate electrode layer using a particle beam such as an atomic beam or a molecular beam of a gate electrode material, and a step of removing the multilayer resist coating film. Since the step of forming the gate electrode is included, the cross-sectional structure of the gate electrode can be formed to have a shape in which the lower portion has a smaller width than the upper portion, and has a multi-stage overhang structure.
[0032]
Further, in the third invention, in addition to the second invention, the gate length is Lg, the film thickness of the lowermost resist is a, and the thickness of the insulating film formed on the semiconductor substrate is the same as that of the third invention. When the sum of the depth and the thickness of the semiconductor substrate surface etched in the etching step is b, and the lateral spread of the lowermost resist in the gate electrode pattern formed in the second etching step is x, Since x> ((a / tan75 °) -Lg / 2) and b <(tan75 ° × Lg / 2) are satisfied, the occurrence of disconnection in the gate electrode is suppressed, and the yield is improved. The gate resistance is reduced and the frequency characteristics and low noise characteristics are improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a method for manufacturing a gate electrode of a field-effect transistor of the present invention.
FIG. 2 is a sectional view showing a first conventional example.
FIG. 3 is a sectional view showing a second conventional example.
FIG. 4 is a cross-sectional transmission electron micrograph of a manufactured gate electrode.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 uppermost resist 2 intermediate resist 3 lowermost resist 4 silicon oxide film 5 source electrode 6 drain electrode 7 contact layer 8 semiconductor substrate 9 gate electrode 10 first overhang 11 second overhang 14 silicon nitride film 20 electron beam Resist 21 Resist layer 22 Metal thin film

Claims (3)

A gate electrode of a field-effect transistor having a multi-stage overhang structure such that its cross-sectional structure has a shape in which a lower portion has a narrower width than an upper portion. When manufacturing a gate electrode by a lift-off method using a multilayer resist coating film,
Forming an insulating film on the semiconductor substrate;
A step of applying a photo resist or an electron beam resist used for lift-off on the insulating film;
The above-mentioned optical resist or electron beam resist has a cross-sectional structure in which at least a part thereof has a shape in which the lower part has a narrower width than the upper part, and the depth of the groove reaches the insulating film. Forming a gate electrode pattern having a given planar shape;
A first etching step of etching the insulating film,
A second etching step of etching the multilayer resist coating film by an amount corresponding to a predetermined thickness;
A third etching step of etching the semiconductor substrate surface by an amount corresponding to a predetermined film thickness;
Forming a gate electrode layer using a particle beam such as an atomic beam or a molecular beam of the gate electrode material;
Removing the multi-layer resist coating film to form a gate electrode. The gate length is Lg, the thickness of the lowermost resist is a, and the thickness of the thickness of the insulating film formed on the semiconductor substrate and the depth of the surface of the semiconductor substrate etched in the third etching step are described. When the total is b and the lateral spread of the lowermost resist in the gate electrode pattern formed in the second etching step is x,
x> ((a / tan75 °) -Lg / 2) and b <(tan75 ° × Lg / 2),
3. The method for manufacturing a gate electrode of a field effect transistor according to claim 2, wherein:

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