JP2005327890A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a dual gate transistor including two gate electrodes having different thresholds without increasing a processing load compared with conventional manufacturing methods by forming a source, a drain, and a first gate electrode with a capping layer, and further forming a second gate electrode with a metal gate electrode by making use of an oblique deposition method. <P>SOLUTION: The semiconductor device includes a channel layer 12, a Schottky barrier layer 13, and a capping layer 14 laminated in sequence on a substrate 10. In the semiconductor device, a source 15 and a drain 16 are formed in an electrically isolated manner using the capping layer 14, and a first gate electrode 17 electrically isolated from the source 15 and the drain 16 is formed between the source 15 and the drain 16. Further, there is formed a second gate electrode 18 between the source 15 and the gate electrode 17. The second gate electrode is electrically isolated from the source 15 and the first gate electrode 17, and is embedded partly in an upper portion of the Schottky barrier layer 13. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device and a method for manufacturing the semiconductor device in which a dual gate HEMT (High Electron Mobility Transistor) can be easily manufactured.

  A field effect transistor (FET) having two gates between a source and a drain is called a dual gate FET. As an example, an n-GaAs layer is formed on a semi-insulating GaAs substrate as shown in the schematic configuration perspective view and the plan layout diagram of FIG. 11, and the first is formed between the source and drain formed in the n-GaAs layer. A dual gate field effect transistor (dual gate FET) in which a gate and a second gate are formed is disclosed (for example, see Non-Patent Document 1).

  Since the dual gate FET has two control electrodes (first gate and second gate), two systems of signals can be independently applied, and it is effective in increasing the efficiency and withstanding voltage. Furthermore, if each of the gate electrodes has different threshold values for enhancement and depletion, a high-efficiency and high-voltage amplifier capable of operating with a single power source can be obtained. However, in order to form two gate electrodes having different threshold values, since the metals constituting the gate electrode in contact with the semiconductor are different, it is necessary to form each gate electrode in a separate process, and the process is complicated. There was a problem of becoming.

Yoichiro Takayama “Microwave Transistor” The Institute of Electrical, Information and Communication Engineers 1998 p. 36

  The problem to be solved is that in order to form two gate electrodes having different threshold values, the metal constituting the gate electrode in contact with the semiconductor is different, so that each gate electrode must be formed in a separate process. The process is complicated.

  The semiconductor device of the present invention includes a channel layer formed on a substrate, a Schottky barrier layer formed on the channel layer, a source including a cap layer formed on the Schottky barrier layer, and the shot A drain made of the same layer as the cap layer formed on the key barrier layer and formed in a state of being electrically separated from the source, and the same cap layer as the cap layer formed on the Schottky barrier layer A first gate electrode formed between the source and the drain in a state of being electrically separated from the source and the drain; and between the source and the first gate electrode. A second gate electrode formed in a state of being electrically separated from the source and the first gate electrode and partially embedded in the upper part of the Schottky barrier layer. And most important, comprising the and.

  The method for manufacturing a semiconductor device according to the present invention includes a step of sequentially forming a channel layer, a Schottky barrier layer, and a cap layer on a substrate, and an upper portion of the substrate, the channel layer, the Schottky barrier layer, and the cap. Forming the transistor region by processing the layer into a convex shape, forming the insulating film covering the transistor region, and the insulation between the region serving as the first gate electrode and the region serving as the drain Forming a single or a plurality of rows of holes in the film, and forming a long hole parallel to the row of holes in the insulating film between the region serving as the first gate electrode and the region serving as the source; The cap layer is etched from the holes and the long holes, and a source made of the cap layer and a gate made of the cap layer and electrically separated from the source are formed. And a step of forming a first gate electrode made of the cap layer and electrically isolated from the source and the drain between the source and the drain; and the Schottky barrier layer through the slot And the step of forming a second gate electrode electrically isolated from the source and the first gate electrode between the source and the first gate electrode. And

  In the semiconductor device of the present invention, the first gate electrode that is electrically separated from the source and the drain is formed in the cap layer that forms the source and the drain. There is an advantage that one gate electrode can be formed simultaneously. In addition, since the second gate electrode is formed in a state of being partially buried above the Schottky barrier layer, the gate-channel distance is shortened even for a thin film structure designed in a depletion type. A depletion type HEMT can be easily realized.

  According to the method of manufacturing a semiconductor device of the present invention, a cap layer for forming a source and a drain forms a first gate electrode that is electrically separated from the source and the drain. There is an advantage that the first gate electrode can be formed simultaneously. In addition, since the second gate electrode is formed in a state where the Schottky barrier layer is partially embedded, the enhancement type HEMT can be formed by shortening the distance between the gate and the channel even for the thin film structure designed for the depression type. It can be easily realized.

  In addition, one or a plurality of rows of holes are formed in the insulating film between the region serving as the first gate electrode and the region serving as the drain, and the region serving as the first gate electrode and the region serving as the source Since a long hole is formed in the insulating film between the hole and the cap layer is etched from the hole and the long hole, the cap layer is etched in the plane direction along with the depth direction from the hole line, and adjacent to the hole layer. The portions etched from the holes to be connected are connected, and are etched so as to be linear and parallel to each other in the same manner as the portion where the cap layer is etched from the long holes. Accordingly, it is possible to form the source made of the cap layer, the first gate electrode, and the drain in a state where they are electrically separated from each other.

  In addition, since the second gate electrode is formed in a state where a part of the Schottky barrier layer is buried, the depletion type HEMT is formed by shortening the distance between the gate and the channel even for the thin film structure designed for the depletion type. It can be easily realized.

  Therefore, in the dual gate HEMT semiconductor device, the enhancement type HEMT using the second gate electrode and the depletion type HEMT using the first gate electrode made of the cap layer are formed without increasing the patterning layer. Therefore, the dual gate HEMT can be manufactured by a simple method.

  For the purpose of realizing a dual gate transistor having two gate electrodes having different threshold values by an easy manufacturing process, a source, a drain, and a first gate electrode are formed with a cap layer, and a first deposition is performed using an oblique deposition method. By forming the two gate electrodes with a metal gate electrode, it was realized without increasing the process load.

  One embodiment of the semiconductor device of the present invention will be described with reference to FIG. FIG. 1 (1) is a schematic sectional view, and FIG. 1 (2) is a plan layout view.

As shown in FIG. 1, the substrate 10 is formed by forming an indium aluminum arsenic (InAlAs) layer on an indium phosphide (InP) substrate. A channel layer 12, a Schottky barrier layer 13, and a cap layer 14 are laminated on the substrate 10 in order from the lower layer. The channel layer 12 is made of, for example, an indium gallium arsenide (i-InGaAs) layer, and has a thickness of, for example, 15 nm. The Schottky barrier layer 13 is made of, for example, an indium aluminum arsenic (i-InAlAs) layer, and has a thickness of, for example, 18 nm (6 nm + 12 nm). Between the 6 nm and 12 nm InAlAs layers is a delta doped layer of silicon. The cap layer 14 is made of, for example, an n ⁺ indium gallium arsenide (InGaAs) layer doped with silicon (Si), and has a thickness of 50 nm, for example. The doping concentration of silicon is, for example, 9 × 10 ¹⁸ cm ⁻³ .

  On the Schottky barrier layer 13, a source 15 made of the cap layer 14, a drain made of the cap layer 14 and electrically isolated from the source 15, and a cap layer 14. Thus, a first gate electrode 17 is formed between the source 15 and the drain 16 so as to be electrically separated from the source 15 and the drain 16. Further, an insulating film 31 is formed on the cap layer 14, and an opening 32 is formed in the insulating film 31 between the source 15 and the first gate electrode 17. The second gate electrode 18 is formed so as to reach the Schottky barrier layer 13 through the opening 32 and is electrically insulated from the source 15 and the first gate electrode 17.

  The second gate electrode 18 has at least a platinum layer, and is made of, for example, an electrode in which a platinum (Pt) layer, a titanium (Ti) layer, a platinum (Pt) layer, and a gold (Au) layer are stacked from the lower layer. Specifically, as an example, a platinum layer (thickness = 2.5 nm), a titanium layer (thickness = 30 nm), a platinum layer (thickness = 30 nm), and a gold layer (thickness = 1500 nm) are stacked from the lower layer. It consists of electrodes. Further, at least a part of the platinum layer on the Schottky barrier layer 13 side is diffused into the Schottky barrier layer 13, and the second gate electrode 18 is partially embedded in the Schottky barrier layer 13.

  The reason why the second gate electrode 18 has a multilayer electrode structure will be described below. The lowermost layer (first layer) platinum (Pt) layer reacts with InAlAs of the Schottky barrier layer 13 by annealing to form a buried electrode. The embedding depth is related to the thickness of the lowermost platinum layer. When the film thickness is increased, the embedding depth becomes deeper as the annealing time and the annealing temperature are increased. It is necessary to set an appropriate platinum layer thickness according to the thickness of the Schottky barrier layer 13 made of InAlAs and the carrier concentration. In the case of the device structure shown in this embodiment, a platinum layer is deposited to a thickness of 5 nm to 6 nm, and after that, annealing is performed at 290 ° C. for 5 minutes to form an enhancement type gate electrode. Can do.

  The second titanium (Ti) layer is a block material that prevents the diffusion of platinum (Pt) in the third platinum (Pt) layer. In order to prevent the third layer platinum from reaching the semiconductor surface by the annealing. belongs to. The same effect can be obtained by using a refractory metal such as molybdenum (Mo) or tungsten (W) instead of titanium.

  The third platinum (Pt) layer is a block material that prevents the diffusion of the fourth gold (Au) layer, and prevents the fourth gold from reaching the semiconductor surface by the annealing. The same effect can be obtained by using a refractory metal such as molybdenum (Mo) or tungsten (W) instead of platinum.

  The fourth gold (Au) layer is for increasing the thickness of the gate electrode and reducing the gate resistance. Copper (Cu), aluminum (Al), or the like can be used instead of Au.

  The reason for using a buried gate formed by forming a platinum layer in the lowermost layer of the second gate electrode 18 and diffusing the platinum layer is that a depletion type HEMT is formed by shortening the distance between the gate and the channel by a platinum filling operation. It is for realizing. As a result, an enhancement type HEMT can be configured with respect to a thin film structure designed as a depression type.

  As shown in the drawing, the second gate electrode 18 can be formed as a T-type gate electrode. By using the T-type gate electrode, it is possible to reduce the gate resistance of the enhancement type HEMT, thereby improving the high-frequency characteristics of the device.

  Openings 33, 34 and 35 are formed in the insulating film 31 on the source 15, the drain 16, and the first gate electrode 17, and the openings 33, 34 and 35 are connected to the source 15, respectively. A source electrode 21, a drain electrode 22 connected to the drain 16, and an electrode pad 23 connected to the first gate electrode 17 are formed. The insulating film 31 is formed with an opening 36 formed of a plurality of holes formed when the cap layer 14 is processed.

  In the semiconductor device 1 composed of a dual gate type HEMT (High Electron Mobility Transistor) having the above configuration, the transistor portion having the first gate electrode 17 operates in a depletion type, and the transistor portion having the second gate electrode 18 is an enhancement type. It will work with.

  In the semiconductor device 1 of the present invention, since the first gate electrode 17 that is electrically separated from the source 15 and the drain 16 is formed by the cap layer 14 that forms the source 15 and the drain 16, one layer of the cap layer 14 is formed. By processing, there is an advantage that the source 15, the drain 16, and the first gate electrode 17 can be formed simultaneously. In addition, since the second gate electrode 18 is formed in a state where a part thereof is embedded in the upper part of the Schottky barrier layer 13, the distance between the gate and the channel is shortened even in a thin film structure designed as a depletion type. Therefore, a depletion type HEMT can be easily realized.

  Next, a first embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to manufacturing process diagrams of FIGS. 2, 4, 5, 7, and 8, the upper diagram shows a plan layout diagram, and the lower diagram shows a cross-sectional view taken along line AA in the plan layout diagram of the lower diagram. FIG. 3 shows an example of an epitaxial structure from the substrate to the cap layer. FIG. 6 shows a cross-sectional view taken along the line AA in the plan layout view and the plan layout view and a cross-sectional view taken along the line BB in the plan layout view.

As shown in FIG. 2, the substrate 10 is formed by forming an indium aluminum arsenic (InAlAs) layer 11 on a (001) indium phosphide (InP) substrate. A channel layer 12, a Schottky barrier layer 13, and a cap layer 14 are stacked on the substrate 10 in this order from the lower layer. The channel layer 12 is formed of, for example, an indium gallium arsenide (i-InGaAs) layer, and has a thickness of, for example, 15 nm. The Schottky barrier layer 13 is formed of, for example, an indium aluminum arsenic (i-InAlAs) layer, and has a thickness of, for example, 18 nm (6 nm + 12 nm). Between the 6 nm and 12 nm InAlAs layers is a delta doped layer of silicon. The cap layer 14 is formed of, for example, an n ⁺ indium gallium arsenide (InGaAs) layer doped with silicon (Si), and has a thickness of, for example, 50 nm. The doping concentration of silicon is, for example, 9 × 10 ¹⁸ cm ⁻³ .

  Specifically, as an example of the epitaxial structure from the substrate to the cap layer, the film structure shown in FIG. 3 can be used.

  When the transistor region 2 is formed, the side portion of the channel layer 12 is located inside the convex side portion of the substrate 10, the side portion of the Schottky barrier layer 13, and the side portion of the cap layer 14. To be formed. That is, the undercut portion 12 u is formed on the side portion of the channel layer 12.

  By forming the undercut portion 12u, it is possible to prevent a source electrode and a drain electrode to be formed later from coming into contact with the channel layer 12. As a result, the gate leakage current can be reduced. This method is a conventionally known technique, for example, IEEE Electron Device Lett. Vol13, No.4 (1992) p.195. Is disclosed.

  Next, the transistor region 2 is formed by processing the upper portion of the substrate 10, the channel layer 12, the Schottky barrier layer 13, and the cap layer 14 into a convex shape by using a normal lithography technique and an etching technique. Next, an insulating film 31 that covers the transistor region 2 is formed.

  Next, as shown in FIG. 4, after a resist is applied on the insulating film 31 to form a resist film 41, a lithography technique is used between the region serving as the first gate electrode and the region serving as the drain. One or more holes 42 are formed in the resist film 41, and long holes are formed in the resist film 41 between the region serving as the first gate electrode and the region serving as the source in parallel with the row of the holes 42. 43 is formed. For the lithography technique, for example, an electron beam lithography technique is preferably used, but an optical lithography technique such as an ultraviolet lithography technique can also be used. The hole 42 is formed in a rectangular pattern, for example. Moreover, the said long hole 43 is formed in the long rectangular pattern, for example.

  Next, as shown in FIG. 5, the insulating film 31 is etched from the hole 42 and the long hole 43 using the resist film 41 as an etching mask. As a result, openings 36 made of one or a plurality of rows of holes are formed in the insulating film 31 between the region serving as the first gate electrode and the region serving as the drain, and on the region serving as the first gate electrode. An opening 32 made of a long hole is formed in parallel with the row of the holes 36 in the insulating film 31 between the source region and the source region.

  Further, the cap layer 14 is etched using the resist film 41 and the insulating film 31 as an etching mask. As a result, the source 15 made of the cap layer 14, the drain 16 made of the cap layer 14 and electrically separated from the source 15, and the source 15 made of the cap layer 14 between the source 15 and the drain 16. A first gate electrode 17 electrically isolated from the drain 16 is formed. In the above etching, InAlAs is performed by immersing it in an etching solution that is not etched. As a specific example of the etching solution, a mixed solution of a carboxylic acid such as adipic acid, succinic acid, and citric acid and a hydrogen peroxide solution may be used.

  Next, as shown in FIG. 6, the Schottky barrier layer 13 is reached through the opening 32 made of the long hole by an oblique deposition method from the longitudinal direction of the opening 32 (long hole). A source 15 and a second gate electrode 18 electrically isolated from the first gate electrode 17 are formed between the first gate electrode 17 and the first gate electrode 17. At this time, the deposited material 51 adheres to the side wall of the opening 36 formed of a plurality of holes, but the deposited material 51 does not reach the Schottky barrier layer 13 because it is behind the resist film 41 or the like. Therefore, the second gate electrode 18 can be formed by selectively depositing the vapor deposition material only on the opening 32.

  The deposition angle in the oblique deposition method needs to be set to an appropriate value depending on the thickness of the resist film 41 and the size of the opening. For example, considering the case where an opening 36 made of a 200 nm rectangular pattern is opened in a resist film 41 having a thickness of 300 nm, the incident direction of the evaporation source is, for example, θ = 55 with respect to the normal of the substrate 10. Incident from a tilted direction.

  As the material of the second gate electrode 18, a gate electrode material capable of forming an enhancement type HEMT is selected. For example, a platinum (Pt) layer, a titanium (Ti) layer, a platinum (Pt) layer, and a gold (Au) layer are stacked from the lower layer. Specifically, as an example, a platinum layer (thickness = 2.5 nm), a titanium layer (thickness = 30 nm), a platinum layer (thickness = 30 nm), and a gold layer (thickness = 1500 nm) are stacked from the lower layer. .

  Thereafter, the resist film 41 is removed by a lift-off method, and the deposited material 51 adhering to the resist film 41 is also removed. As a result, as shown in FIG. 7, the second gate electrode 18 is selectively formed only in the opening 32. Next, annealing is performed at about 300 ° C. for 1 minute in a mixed gas atmosphere of hydrogen and nitrogen. By this annealing, platinum (Pt) in the platinum layer formed in the lowermost layer constituting the second gate electrode 18 reacts with InAlAs in the Schottky barrier layer 13, and between the second gate electrode 18 and the channel layer 12. The distance becomes shorter by several nm. That is, at least a part of the platinum layer on the Schottky barrier layer 13 side is diffused in the Schottky barrier layer 13, and the second gate electrode 18 is partially embedded in the Schottky barrier layer 13. This technique is disclosed in IEEE Transactions on Electron Devices, vol. 45, No. 12, (1998) p. As a result, an enhancement type HEMT having the second gate electrode 18 between the source 15 and the first gate electrode 17 is formed.

  Next, the reason why the second gate electrode 18 is formed as a multilayer electrode structure will be described below. The bottom layer (first layer) platinum layer reacts with InAlAs of the Schottky barrier layer 13 by the annealing to form a buried electrode. The embedding depth of the second gate electrode 18 thus formed is related to the thickness of the lowermost platinum layer, and the embedding depth is increased by increasing the annealing time and annealing temperature by increasing the film thickness. The depth can also be increased. The lowermost platinum layer needs to be set to an appropriate thickness according to the thickness of the Schottky barrier layer 13 made of InAlAs and the carrier concentration. At least, it should not penetrate through the Schottky barrier layer 13. In the manufacturing method shown in the present embodiment, the bottom platinum layer is formed to a thickness of 2 nm to 3 nm, and the annealing is performed at 290 ° C. for 5 minutes, thereby forming an enhancement type buried gate electrode. be able to.

  The second titanium layer is a block material that prevents diffusion of the third platinum layer, and is intended to prevent the third platinum layer from reaching the semiconductor surface by the annealing. The same effect can be obtained by using a refractory metal such as molybdenum (Mo) or tungsten (W) instead of titanium.

  The third platinum layer is a block material that prevents diffusion of the fourth gold layer, and prevents the fourth gold layer from reaching the semiconductor surface by the annealing. The same effect can be obtained by using a refractory metal such as molybdenum (Mo) or tungsten (W) instead of platinum.

  The fourth gold layer is for increasing the thickness of the gate electrode and reducing the gate resistance. Copper (Cu), aluminum (Al), or the like can be used instead of gold.

  The reason why the platinum layer is formed in the bottom layer of the second gate electrode 18 and the buried platinum layer is formed by diffusing the platinum layer is that the depletion type HEMT is formed by shortening the distance between the gate and the channel by the platinum filling operation. It is for realizing. As a result, an enhancement type HEMT can be configured with respect to a thin film structure designed as a depression type.

  The second gate electrode 18 can be formed as a T-type gate electrode. By using the T-type gate electrode, it is possible to reduce the gate resistance of the enhancement type HEMT, thereby improving the high-frequency characteristics of the device. Details of the manufacturing method for forming the T-type gate will be described later.

  Next, as shown in FIG. 8, a resist is applied on the insulating film 31 to form a resist film (not shown), and then a hole is formed in the resist film on the first gate electrode 17 by lithography. To do. For example, an electron beam lithography technique is preferably used as the lithography technique, but an ultraviolet lithography technique or the like can also be used as an optical lithography technique. Next, the insulating film 31 is etched using the resist film as an etching mask. As a result, an opening 35 is formed in the insulating film 31 on the first gate electrode 17.

  Next, an electrode material is deposited on the first gate electrode 17 from the opening 35 by vapor deposition, and the electrode pad 23 connected to the first gate electrode 17 is formed in the opening 34. Thereafter, the resist film is removed by a lift-off method, and the deposited material adhering to the resist film is also removed.

  Further, after the source 15 and the drain region 16 are exposed by a normal lithography technique and an etching technique, the source electrode 21 and the drain electrode 22 to be ohmic electrodes connected to the source 15 and the drain 16 are formed by a normal electrode forming technique. Form.

  In the dual gate HEMT semiconductor device 1 formed as described above, the transistor portion having the first gate electrode 17 is a depletion type, and the transistor portion having the second gate electrode 18 is an enhancement type.

  Next, the reason why the second gate electrode 18 including the platinum layer in the lowermost layer in the above embodiment is formed will be described below. This is because it is necessary to make an enhancement type HEMT with respect to a thin film structure designed as a depletion type. In this embodiment, the platinum layer is reacted (diffusion reaction) in the Schottky barrier layer 13 to obtain the second. A depletion type HEMT is realized with a transistor having the second gate electrode 18 by embedding the gate electrode 18 to reduce the distance between the second gate electrode 18 and the channel layer 12. In addition, when the thin film structure is designed in the enhancement type, there is an idea that there is no need to use the buried gate and the selection range of the electrode material may be expanded, but if the thin film structure is designed in the enhancement type from the beginning, the following reasons Thus, a desired transistor element structure cannot be obtained. In other words, the cap layer 14 has a high resistance, and the transistor characteristics cannot be obtained or are significantly deteriorated.

  The reason is that a depletion type HEMT part (a gate electrode part using a semiconductor cap layer) cannot be produced. This is because even if there is a cap layer on the Schottky barrier layer made of InAlAs, it is presumed that the position of the Fermi level does not change and it becomes a depletion type as designed in the thin film structure.

  Therefore, in this embodiment, it is judged that the best method is to design the thin film structure in a depletion type and to produce the second gate electrode 18 of the enhancement type HEMT part with a buried gate structure of platinum (Pt). .

  In the method of manufacturing a semiconductor device according to the present invention, the first gate electrode 17 electrically isolated from the source 15 and the drain 16 is formed by the cap layer 14 that forms the source 15 and the drain 16. By processing, there is an advantage that the source 15, the drain 16 and the first gate electrode 17 can be formed simultaneously. In addition, since the second gate electrode 18 is formed in a state where a part thereof is embedded in the upper part of the Schottky barrier layer 13, the enhancement-type structure can be obtained by shortening the distance between the gate and the channel even for a thin film structure designed as a depression type. HEMT can be easily realized.

  In addition, an opening 36 formed of one or more rows of holes is formed in the insulating film 31 between the region serving as the first gate electrode 17 and the region serving as the drain 16, and the region serving as the first gate electrode 17. Since the opening 32 made of a long hole is formed in the insulating film 31 between the top and the region to be the source 15 in parallel with the row of holes, and the cap layer 14 is etched from the opening 36 and the opening 32, The cap layer 14 is etched in the plane direction along with the depth direction from the row of the openings 36, and the portions etched from the adjacent openings 36 are connected, and are linear like the portions where the cap layer 14 is etched from the openings 36. And etching so that they are parallel to each other. Therefore, the source 15, the first gate electrode 17, and the drain 16 made of the cap layer 14 can be formed in a state of being electrically isolated from each other.

  In addition, the second gate electrode is partially embedded in the upper part of the Schottky barrier layer 13 while being electrically separated from the source 15 and the first gate electrode 17 between the source 15 and the first gate electrode 17. Since 18 is formed, the second gate electrode 18 can be easily formed of a material having a threshold value different from that of the first gate electrode 17. In addition, since the second gate electrode 17 is formed in a state where a part thereof is embedded in the upper part of the Schottky barrier layer 13, the second gate electrode 17 and the channel layer 12 are formed even for a thin film structure designed as a depletion type. By shortening the length, a depletion type HEMT can be easily realized.

  Therefore, in the dual gate HEMT semiconductor device 1, the enhancement type HEMT using the second gate electrode 18 and the depletion type HEMT structure using the first gate electrode 17 formed of the cap layer 14 are used as a patterning layer. Therefore, the dual gate HEMT can be manufactured by a simple method.

  Next, a second embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the manufacturing process sectional views of FIGS. In the second embodiment, a method of forming a second gate electrode on a T-type gate electrode will be described. Processes other than the process of forming the second gate electrode are the same as those in the manufacturing method of the first embodiment.

  As shown in FIG. 9A, as described with reference to FIG. 2, the channel layer 12, the Schottky barrier layer 13, and the cap layer 14 are formed on the substrate 10 and processed into a convex shape to form the transistor region 2. Form. Thereafter, an insulating film 31 covering the transistor region 2 is formed. Next, a resist is applied to form a first-layer resist film 61 (similar to the resist film 41 of the first embodiment). Subsequently, a hole 62 (similar to the hole 42 of the first example) and a long hole 63 (similar to the long hole 43 of the first example) are formed in the resist film 61 by the lithography technique as in the first example. Examples of the first resist film 61 include polymethyl methacrylate and PMMA.

  Next, as shown in FIG. 9 (2), a second resist film 64 is formed later with the first resist film 61 so that the hole 62 and the long hole 63 are embedded on the resist film 61. A different type of resist from the third layer resist film is applied and formed. For the second-layer resist film 64, for example, PMGI (polymethylglutarimide) can be used. As the resist material for the second layer, a material that does not dissolve the resist film 61 of the first layer at the time of applying the resist of the second layer and is not dissolved at the time of application and development of the third layer is selected. Next, a third-layer resist film 65 is formed on the resist film 64.

  Next, as shown in FIG. 10 (3), the third-layer resist film 65 is patterned by lithography to form openings 66 and 67 larger than those on the hole 62 and the long hole 63. .

  After developing and patterning the third layer resist film 65 as described above, the resist film 64 is etched using a solution that dissolves only the second layer resist film 64, and the holes 62 and the long holes 63 are formed again. Open. Further, the resist film 64 is etched to be larger than the widths of the holes 62 and the long holes 63 to form openings 68 and 69. For this etching, for example, an aqueous tetramethylammonium hydroxide solution can be used.

  Thereafter, although not shown, after the source, drain, and first gate electrodes are formed in the same manner as described with reference to FIGS. 5 and 6 of the first embodiment, the second gate is formed by oblique deposition and lift-off. An electrode may be formed. As a result, a second gate electrode having a T-type structure that reaches the Schottky barrier layer in the opening 63 and the opening 69 can be obtained.

  As described in the second embodiment, by using a multilayer (three-layer) resist structure, the second gate electrode constituting the enhancement type transistor can be formed on the T-type gate electrode. By using a T-type gate in this way, the gate resistance of the enhancement type HEMT can be reduced, and the high-frequency characteristics of the element can be improved.

  The semiconductor device and the manufacturing method thereof of the present invention are preferably applied to the dual gate HEMT and the manufacturing method thereof.

1A and 1B are a schematic configuration cross-sectional view and a plan layout diagram illustrating an embodiment of a semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS It is a manufacturing process figure which shows 1st Example concerning the manufacturing method of the semiconductor device of this invention, an upper figure shows a plane layout figure, and a lower figure shows the AA sectional view taken on the plane layout figure of the lower figure. It is drawing which shows an example of the epitaxial structure from a board | substrate to a cap layer. BRIEF DESCRIPTION OF THE DRAWINGS It is a manufacturing process figure which shows 1st Example concerning the manufacturing method of the semiconductor device of this invention, an upper figure shows a plane layout figure, and a lower figure shows the AA sectional view taken on the plane layout figure of the lower figure. BRIEF DESCRIPTION OF THE DRAWINGS It is a manufacturing process figure which shows 1st Example concerning the manufacturing method of the semiconductor device of this invention, an upper figure shows a plane layout figure, and a lower figure shows the AA sectional view taken on the plane layout figure of the lower figure. BRIEF DESCRIPTION OF THE DRAWINGS It is a manufacturing-process figure which shows 1st Example which concerns on the manufacturing method of the semiconductor device of this invention, and shows the AA line sectional drawing in a plane layout figure and a plane layout figure, and the BB line sectional view in a plane layout figure Show. BRIEF DESCRIPTION OF THE DRAWINGS It is a manufacturing process figure which shows 1st Example concerning the manufacturing method of the semiconductor device of this invention, an upper figure shows a plane layout figure, and a lower figure shows the AA sectional view taken on the plane layout figure of the lower figure. BRIEF DESCRIPTION OF THE DRAWINGS It is a manufacturing process figure which shows 1st Example concerning the manufacturing method of the semiconductor device of this invention, an upper figure shows a plane layout figure, and a lower figure shows the AA sectional view taken on the plane layout figure of the lower figure. It is manufacturing process sectional drawing which shows 2nd Example which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which shows 2nd Example which concerns on the manufacturing method of the semiconductor device of this invention. It is the schematic structure perspective view and plane layout figure which show the conventional dual gate FET.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 10 ... Board | substrate, 12 ... Channel layer, 13 ... Schottky barrier layer, 14 ... Cap layer, 15 ... Source, 16 ... Drain, 17 ... 1st gate electrode, 18 ... 2nd gate electrode

Claims (13)

A channel layer formed on the substrate;
A Schottky barrier layer formed on the channel layer;
A source comprising a cap layer formed on the Schottky barrier layer;
A drain formed of the same layer as the cap layer formed on the Schottky barrier layer and formed in a state of being electrically separated from the source;
A first gate electrode made of the same layer as the cap layer formed on the Schottky barrier layer and formed between the source and the drain so as to be electrically separated from the source and the drain When,
A second gate formed between the source and the first gate electrode and being electrically isolated from the source and the first gate electrode and partially embedded in the upper part of the Schottky barrier layer A semiconductor device comprising: an electrode. The semiconductor device according to claim 1, wherein the second gate electrode has a platinum layer at least on the Schottky barrier layer side. The semiconductor device according to claim 2, wherein the second gate electrode includes an electrode in which a platinum layer, a titanium layer, a platinum layer, and a gold layer are stacked from a lower layer. The semiconductor device according to claim 2, wherein at least a part of the platinum layer on the Schottky barrier layer side is diffused in the Schottky barrier layer. The transistor portion having the first gate electrode operates in a depletion type,
The semiconductor device according to claim 1, wherein the transistor portion having the second gate electrode operates in an enhancement type. The substrate is formed in a convex shape at the top,
The channel layer, the Schottky barrier layer, and the cap layer are formed on the convex-formed substrate portion,
The side part of the channel layer is formed so as to be inside the side part of the substrate portion formed in the convex shape, the side part of the Schottky barrier layer, and the side part of the channel layer. The semiconductor device according to claim 1. A step of sequentially laminating a channel layer, a Schottky barrier layer and a cap layer on a substrate;
Processing the upper part of the substrate, the channel layer, the Schottky barrier layer, and the cap layer into a convex shape to form a transistor region;
Forming an insulating film covering the transistor region;
One or more holes are formed in the insulating film between the region serving as the first gate electrode and the region serving as the drain, and between the region serving as the first gate electrode and the region serving as the source. Forming a long hole in the insulating film parallel to the row of holes;
The cap layer is etched from the holes and the long holes, the source is made of the cap layer, the drain is made of the cap layer and is electrically separated from the source, and the cap layer is made of Forming a first gate electrode electrically isolated from the source and the drain between the source and the drain;
Forming a second gate electrode that reaches the Schottky barrier layer through the elongated hole and is electrically separated from the source and the first gate electrode between the source and the first gate electrode; A method for manufacturing a semiconductor device, comprising: The step of forming the second gate electrode includes:
Using the resist mask used when forming the hole and the long hole in the insulating film,
Depositing a material for forming the second gate electrode on the Schottky barrier layer through the long hole by oblique vapor deposition from the longitudinal direction of the long hole;
The method for manufacturing a semiconductor device according to claim 7, further comprising: removing the resist mask and removing a material for forming the second gate electrode attached to the resist mask. The method of manufacturing a semiconductor device according to claim 7, wherein in the step of forming the second gate electrode, a platinum layer is formed at least on the Schottky barrier layer side. The method for manufacturing a semiconductor device according to claim 9, wherein the second gate electrode is formed by stacking a platinum layer, a titanium layer, a platinum layer, and a gold layer from a lower layer. The method for manufacturing a semiconductor device according to claim 9, wherein at least a part of the platinum layer on the Schottky barrier layer side diffuses into the Schottky barrier layer. The side portion of the channel layer is formed so as to be inside the side portion of the substrate portion formed in the convex shape, the side portion of the Schottky barrier layer, and the side portion of the cap layer. A method for manufacturing a semiconductor device according to claim 7. Processing the insulating film to expose at least a portion of the source, the drain, and the first gate electrode;
The method of manufacturing a semiconductor device according to claim 7, further comprising: forming a source electrode, a drain electrode, and a pad electrode connected to the source, the drain, and the first gate electrode.

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