JP2006011194A - Display device and driving method of display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein defects in image quality, called "horizontal crosstalks" appear due to a leakage current leaking from a horizontal switch when there is such a leakage. <P>SOLUTION: A dot sequential drive type active matrix liquid crystal display positively uses leakages in precharge switches 141-1 to 141-n to make leakage quantities of the precharge switches 14-1 to 141-n in a writing period of a video signal Vsig larger than the leakage quantities of sampling switches 135-1 to 135-n, when a black level is written, and consequently, image display which is blacker than horizontal crosstalks due to leaks of the sampling switches 135-1 to 135-n is performed over the entire screen so as to make the horizontal crosstalks not appear on the display screen. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display device and a display device driving method, and more particularly to a display device in which pixels including electro-optic elements are two-dimensionally arranged in a matrix and a method for driving the display device.

  A display device in which pixels including electro-optical elements are two-dimensionally arranged in a matrix, for example, a liquid crystal cell is used as an electro-optical element, and pixels including the liquid crystal cells are two-dimensionally arranged in a matrix, and a matrix arrangement of these pixels On the other hand, a scanning line for each row and a signal line for each column are arranged, a vertical driving circuit for selecting each pixel of this pixel array unit in units of rows, and this vertical driving circuit. In an active matrix liquid crystal display device having a horizontal drive circuit for writing a video signal to each pixel in a row (hereinafter also referred to as a “selected row”), the dot sequential drive method is serially input through a video line, for example. The analog video signal is sequentially sampled over one horizontal scanning period by a horizontal switch connected between the video line and each of the signal lines. To the pixels of the selected row of the video signal is of the type written sequentially through the corresponding signal line.

  In this dot matrix driving type active matrix liquid crystal display device, a horizontal switch corresponding to each pixel in the horizontal direction is connected to a common video line, and the self-signal potential (the image sampled by itself) is connected to the horizontal switch. Since a video signal potential other than (signal potential) is also given, it is known that when there is a leak in the horizontal switch, an image quality defect called lateral crosstalk appears due to the leak current (see, for example, Patent Document 1). Here, the horizontal crosstalk is, for example, in the normally black mode, and when the black window 101 is displayed on the gray raster as shown in FIG. 10, the black is displayed before and after the black window 101 in the horizontal scanning direction (lateral direction). Or the phenomenon which draws white belts 102 and 103 is said.

JP 2000-305533 A

  The lateral crosstalk includes a band 102 (hereinafter referred to as front lateral crosstalk) 102 that exits in front of the window 101 in the horizontal scanning direction, and a band (hereinafter referred to as rear lateral crosstalk) 103 that exits behind the window 101. It is divided into. Here, the front side crosstalk 102 is considered. The generation principle of the front side crosstalk 102 will be described with reference to FIG.

  As described above, the video signal potential that is not its own signal potential, that is, the video signal potential that does not need to be sampled, is constantly given to the horizontal switch. In general, as the horizontal switch 201, an analog switch in which an Nch transistor Qn201 and a Pch transistor Qp201 are connected in parallel is used as shown in FIG. There is always a leak. The amount of leakage current Iback is determined by the characteristics of the transistor, the video signal potential, the gate potential of the transistor, and the potential of the signal line 202, but the potential leaks from the horizontal switch 201 more or less.

  Specifically, the black level is (1) 12.5 V → (2) 2.5 V → (3) 12.5 V → (4 with the video signal potential Vsig as a reference to the common potential Vcom (for example, 7.5 V). ) If the horizontal switch 201 is not sampled, the gate potential of the Nch transistor Qn201 becomes 0V when the horizontal switch 201 does not perform sampling. The gate potential V of the Pch transistor Qp201 becomes 13.5V.

  When the video signal potential Vsig is 12.5 V, that is, (1), (3),..., The potential of the positive gray raster (about 9.5 V) is held on the signal line 202, and Nch Since the gate potential of the transistor Qn201 is 0V and the source potential is 12.5V, the gate-source voltage Vgs of the transistor Qn201 is -9.5V, the gate potential of the Pch transistor Qp201 is 13.5V, and the source potential is Since the voltage is 12.5 V, the gate-source voltage -Vgs of the transistor Qp201 is 1.0 V, so that the leakage of the Nch transistor Qn201 becomes dominant.

  Further, when the video signal potential Vsig is 2.5 V, that is, (2), (4),..., The negative gray potential (about 5.5 V) is held on the signal line 202, and Nch Since the gate potential of the transistor Qn201 is 0V and the source potential is 2.5V, the gate-source voltage Vgs of the transistor Qn201 is -2.5V, the gate potential of the Pch transistor Qp201 is 13.5V, and the source potential is Since the voltage is 5.5 V, the gate-source voltage -Vgs of the transistor Qp201 becomes 8.0 V, so that the leakage of the Nch transistor Qn201 becomes dominant.

  Due to the leakage current Iback of these transistors Qn201 and Qp201, the potential of the signal line 202 that is originally maintained at its own signal potential is pulled up to the potential on the black level side. At this time, a scan pulse is applied to the pixel 210 in the selected row through the scan line 203 and the pixel transistor 211 is in an on state, so that the potential of the pulled up signal line 202 is changed by the pixel transistor 211 to the pixel capacitance. 212 is written. As a result, a black image appears as horizontal crosstalk. The potential change of the signal line 202 due to the leakage of the horizontal switch 201 occurs before and after the window 101. However, since the self signal potential is written after the black potential leaks behind the window 101, it does not appear as horizontal crosstalk. Therefore, the horizontal crosstalk due to the leakage of the horizontal switch 201 appears only in front of the window 101 in the horizontal scanning direction.

  Lateral crosstalk caused by leakage of the horizontal switch 201 becomes worse as the channel length L of the transistors Qn101 and Qp101 forming the horizontal switch 201 is smaller and the channel width W is larger. This is because the leakage current Iback is proportional to the channel length L and channel width W of the transistors Qn201 and Qp201. Therefore, it can be seen that the channel length L of the transistors Qn201 and Qp201 should be large and the channel width WL length should be small in order to suppress lateral crosstalk due to leakage of the horizontal switch 201. However, this means that the capabilities of the transistors Qn201 and Qp201 are reduced. When the capabilities of the transistors Qn201 and Qp201 are reduced, the ability to write the video signal potential Vsig to the signal line 102 is reduced, which causes other defects such as vertical stripes and ghosts.

  The present invention has been made in view of the above-described problems, and the object of the present invention is to provide a display that can eliminate the horizontal crosstalk due to the leakage of the horizontal switch while keeping the capability of the horizontal switch large to some extent. An object of the present invention is to provide a device and a display device driving method.

  In order to achieve the above object, in the present invention, a pixel array unit in which pixels including electro-optic elements are two-dimensionally arranged in a matrix, and vertical driving means for selecting pixels of the pixel array unit in units of rows, A horizontal switch group for writing a video signal in a pixel unit to pixels in a row selected by the vertical driving means, and a precharge signal of a predetermined level in advance in a pixel unit prior to the writing of the video signal by the horizontal switch group In the display device including the precharge switch group to be written in, the leakage amount of the precharge switch group during the writing period of the video signal by the horizontal switch group is set to the black level in the normally black mode and in the normally white mode. The amount of leakage of the horizontal switch group when writing the white level is made larger.

  In the active matrix type display device of the dot sequential drive system, the leakage of each switch of the horizontal switch group is unavoidable. For example, when a black window is displayed on the gray raster, the leakage of the horizontal switch causes the horizontal scanning direction (horizontal direction). Lateral crosstalk occurs before and after the black window. During the writing period of the video signal by the horizontal switch group, a leak also occurs in each switch of the precharge switch group. At this time, the amount of leakage at the time of writing the black level in the normally black mode and the white level in the normally white mode is written. Since the amount of leakage is greater than the horizontal switch group, a black image is displayed in the normally black mode and a white image is displayed in the normally white mode over the entire screen. No longer appears.

  According to the present invention, during the writing period of the video signal by the horizontal switch group, the leakage amount of the precharge switch group is set to the horizontal switch group when writing the black level in the normally black mode and the white level in the normally white mode. By making it larger than the leak amount, a black image display is displayed in the normally black mode and a white image display in the normally white mode over the entire screen, and horizontal crosstalk due to the leak of the horizontal switch appears on the display screen. Therefore, the horizontal crosstalk due to the leakage of the horizontal switch can be eliminated while keeping the capability of the horizontal switch large to some extent.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing an outline of the configuration of a display device according to an embodiment of the present invention. Here, a dot sequential drive type active matrix liquid crystal display device using a liquid crystal cell as an electro-optical element of a pixel will be described as an example. As is apparent from FIG. 1, the active matrix liquid crystal display device according to this embodiment includes a pixel array unit 11, for example, two vertical drive circuits 12A and 12B, a horizontal drive circuit 13, a precharge circuit 14, and a display drive circuit 15. It has composition which has.

  In the pixel array unit 11, pixels 20 including liquid crystal cells that are electro-optic elements are two-dimensionally arranged in a matrix on a transparent insulating substrate, for example, a first glass substrate (not shown). The scanning lines 16-1 to 16-m are wired for each row in the pixel array of n columns, and the signal lines 17-1 to 17-n are wired for each column. The first glass substrate is disposed opposite to the second glass substrate with a predetermined gap, and a liquid crystal material is sealed between the second glass substrate to constitute the liquid crystal panel 18. .

  FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of the pixel (pixel circuit) 20. As apparent from FIG. 2, the pixel 20 includes a pixel transistor, for example, a TFT (Thin Film Transistor) 21, a liquid crystal cell 22 in which the pixel electrode is connected to the drain electrode of the TFT 21, and one of the drain electrode of the TFT 21. And a storage capacitor 23 to which the electrodes are connected. Here, the liquid crystal cell 22 means a liquid crystal capacitance generated between a pixel electrode and a counter electrode formed opposite to the pixel electrode.

  The TFT 21 has a gate electrode connected to the scanning line 15 (15-1 to 15-m) and a source electrode connected to the signal line 16 (16-1 to 16-n). Further, for example, the counter electrode of the liquid crystal cell 22 and the other electrode of the storage capacitor 23 are connected to the common line 19 in common for each pixel. A common voltage (counter electrode voltage) Vcom is applied to the common electrode of the liquid crystal cell 22 via the common line 19.

  The two vertical drive circuits 12A and 12B are arranged on both the left and right sides with the pixel array unit 11 in between. Here, the vertical drive circuits 12A and 12B are arranged on both the left and right sides of the pixel array unit 11. However, a configuration in which one vertical drive circuit 12 is arranged only on one of the left and right sides of the pixel array unit 11 may be adopted. Is possible. The vertical drive circuits 12A and 12B are configured by shift registers, buffer circuits, and the like.

  In these vertical drive circuits 12A and 12B, each shift register starts a shift operation in response to the vertical start pulse VST, and the vertical start pulse VST is converted into a vertical clock pulse VCK (generally, clock pulses having opposite phases to each other). By sequentially shifting in synchronization with (VCK, VCKX), the transfer pulses transferred at each transfer stage are sequentially output as scan pulses V1 to Vm. The scanning pulses V1 to Vm are applied to the scanning lines 16-1 to 16-m of the pixel array unit 11 to select the pixels 20 in units of rows.

  The horizontal drive circuit 13 includes a shift register 131, clock extraction circuits 132-1 to 132-n, anti-phase pulse generation circuits 133-1 to 133-n, and phase adjustment circuits (APCs) 134-1 to 134-. n, sampling switches (horizontal switches) 135-1 to 135-n, and the like, and the video signal Vsig is written in units of pixels to each pixel 20 in the pixel row selected by the vertical drive circuits 12A and 12B. The horizontal drive circuit 13 includes a horizontal start pulse HST, horizontal clock pulses HCK. HCKX and two single-phase clock pulses DCK1, DCK2 are provided.

  The clock pulse DCK1 is a clock pulse whose pulse width is narrower than the horizontal clock pulse HCK with reference to the rising timing of the horizontal clock pulse HCK, and is supplied to, for example, even stages of the clock sampling circuits 132-1 to 132-n. The The clock pulse DCK2 is a clock pulse whose pulse width is narrower than that of the horizontal clock pulse HCKX with reference to the rising timing of the horizontal clock pulse HCKX, and is supplied to, for example, the odd-numbered stages of the clock extracting circuits 132-1 to 132-n. The

  In the horizontal drive circuit 13, the shift register 131 includes unit circuits (transfer stages / shift stages) cascaded by the number n of pixels in the horizontal direction of the pixel array unit 11, and performs a shift operation in response to a horizontal start pulse HST. Start and sequentially shift the horizontal start pulse HST in synchronization with the horizontal clock pulses HCK and HCKX to sequentially output the transfer pulses H1 to Hn transferred at each transfer stage. These transfer pulses H1 to Hn are sequentially given to the clock extraction circuits 132-1 to 132-n.

  In the clock sampling circuits 132-1 to 132-n, the even-numbered clock sampling circuits 132-2, 132-4,... Are odd-numbered transfer pulses H1, H3,. In synchronization with the first-phase clock pulse DCK2, the single-phase clock pulse DCK2 is extracted and supplied as sampling pulses SP1, SP3,... To the odd-phase reverse-phase pulse generation circuits 133-1, 133-2,. The clock sampling circuits 132-1, 132-3,... Extract the single-phase clock pulse DCK1 in synchronization with the even-numbered transfer pulses H2, H4,. SP2, SP4,... Are supplied to the even-numbered anti-phase pulse generation circuits 133-2, 133-4,.

  The anti-phase pulse generation circuits 133-1 to 133-n generate two-phase sampling pulses SP 1, SP 1 X to SPn, SPnX having opposite phases from the single-phase sampling pulses SP 1 to SPn, and the phase adjustment circuit 134-1 ~ 134-n. In the phase adjustment circuits 134-1 to 134-n, the phases of the two-phase sampling pulses SP1, SP1X to SPn, SPnX generated by the anti-phase pulse generation circuits 133-1 to 133-n are completely in anti-phase. Thus, the phase adjustment of these sampling pulses SP1, SP1X to SPn, SPnX is performed.

  The sampling switches 135-1 to 135-n are, for example, CMOS analog switches in which an Nch MOS transistor and a Pch MOS transistor are connected in parallel, and each one end side is commonly connected to the video line Lv for inputting the video signal Vsig. The end side is connected to one end of each of the signal lines 17-1 to 17-n of the pixel array unit 11. These sampling switches 135-1 to 135-n are turned on (closed) in response to sampling pulses SP1, SP1X to SPn, SPnX having opposite phases, and sequentially sample the video signal Vsig input through the video line Lv. As a result, the video signal Vsig is written to the signal lines 17-1 to 17-n. As a result, dot-sequential driving in which the video signal Vsig is written in units of pixels can be realized for each pixel 20 in the pixel row selected by the vertical drive circuits 12A and 12B.

  FIG. 3 shows the timing relationship between the horizontal start pulse HST, horizontal clock pulses HCK, HCKX, two clock pulses DCK1, DCK1X and DCK2, DCK2X, transfer pulses H1-H4, and sampling pulses SP1, SP1X-SP4, SP4X. It is a chart. As is apparent from this timing chart, the clock pulses DCK1, DCK1X, DCK2, and DCK2X that are synchronized with the horizontal clock pulses HCK and HCKX and narrower than the transfer pulses H1 to H4 are sequentially output from the shift register 131. By sampling in synchronization with the pulses H1 to H4 and sequentially outputting them as sampling pulses SP1, SP1X to SP4, SP4X, the sampling pulses SP1, SP1X to SP4, SP4X have non-overlapping (non-overlapping) waveforms. It becomes.

  The precharge circuit 14 includes precharge switches 141-1 to 141-n arranged for each pixel 20 in the horizontal direction of the pixel array unit 11, and precharges in synchronization with precharge pulses PCK and PCKX having opposite phases. All of the charge switches 141-1 to 141-n are simultaneously turned on at the same time, and a configuration of a collective precharge drive system in which a predetermined precharge signal Psig is collectively written in units of rows is adopted.

  In the precharge circuit 14, precharge switches 141-1 to 141-n are, for example, CMOS analog switches in which an Nch MOS transistor and a Pch MOS transistor are connected in parallel, and are connected to a precharge line Lp for inputting the precharge signal Psig. Each one end side is connected in common, and each other end side is connected to each other end of the signal lines 17-1 to 17-n of the pixel array unit 11. These precharge switches 141-1 to 141-n are simultaneously turned on in response to the precharge pulses PCK and PCKX, and sample the precharge signal Psig in a lump, so that the horizontal drive circuit 13 performs the pixel unit. Prior to writing the video signal Vsig, the precharge signal Psig is written to the signal lines 17-1 to 17-n.

  FIG. 4 is a timing chart showing the timing relationship between the horizontal start pulse HST, the precharge pulses PCK and PCKX having opposite phases to each other, and the precharge signal Psig. As is apparent from this timing chart, the precharge pulses PCK and PCKX for collectively sampling the precharge signal Psig are generated in the blanking period before the horizontal start pulse HST is generated.

  Here, as precharge switches 141-1 to 141-n, transistors having a size smaller than sampling switches (horizontal switches) 135-1 to 135-n are usually used. This is because the precharge switches 141-1 to 141-n are open (on) for a long time. If the precharge switches 141-1 to 141-n are open for a long time, a desired potential is applied to the signal line within the open time of the precharge switches 141-1 to 141-n even if the write capability is somewhat poor. 17-1 to 17-n can be written.

  In the above-described precharge circuit 14, the case where the precharge signal Psig is collectively written in units of rows is adopted as an example. However, the precharge circuit of the precharge circuit method is used. The present invention is not limited to the above, and the present invention can be similarly applied to a case where a dot sequential precharge driving method in which the precharge signal Psig is sequentially written in units of pixels is adopted. In the case of a precharge circuit adopting this dot sequential precharge drive system, a circuit configuration in which the precharge switches 141-1 to 141-n are sequentially opened (turned on) is adopted.

  The display drive circuit 15 is arranged outside the liquid crystal panel 18, supplies the video signal Vsig to the horizontal drive circuit 13 through the video line Lv wired in the liquid crystal panel 18, and pre-wired in the liquid crystal panel 18. A precharge signal Psig is supplied to the precharge circuit 14 through the charge line Lp.

  Here, when the liquid crystal display device according to the present embodiment is in a normally black mode, for example, when the 1H (H is a horizontal period) inversion driving method is adopted, the display driving circuit 15 is shown in the waveform diagram of FIG. As shown, a video signal Vsig whose polarity is inverted every 1H with respect to the common potential Vcom is output. Here, as an example, the case where the common potential Vcom is 7.5V and the black level is 2.5V and 13.5V is shown.

  Further, as shown in the waveform diagram of FIG. 6, the display driving circuit 15 outputs a gray level intermediate potential as the precharge signal Psig during the precharge period in which the precharge pulse PCG is at the “H” level. As a result, the precharge circuit 14 collectively writes the precharge signal Psig of the gray level in advance prior to the writing of the video signal Vsig to the signal lines 17-1 to 17-n. By this precharge operation, the signal level when the video signal Vsig is written to the signal lines 17-1 to 17-n can be reduced, and the charge / discharge current when the video signal Vsig is written can be suppressed. Generation of vertical stripes due to current can be suppressed.

  In the active matrix type liquid crystal display device of the dot sequential drive system configured as described above, the horizontal drive circuit 13 cannot use the transfer pulses H1 to Hn themselves of the shift register 131 as the sampling pulses SP1 to SPn. This is because, as is apparent from the timing chart of FIG. 3, the transfer pulses H1 to Hn of the shift register 131 overlap in adjacent stages, and the transfer pulses H1 to Hn themselves are used as the sampling pulses SP1 to SPn. Since the same video signal Vsig is sampled at adjacent stages (pixel columns), a normal image cannot be displayed.

  Therefore, as shown in FIG. 7, independent video lines Lvo and Lve are wired in the odd-numbered stage and the even-numbered stage where the transfer pulses H1 to Hn overlap each other to perform display driving (in FIG. 1, For simplification of the drawing, it is shown as one video line Lv). In this case, N sampling switches are grouped in units of N pixels (dots) in the horizontal direction, and N sampling switches (units (phases)) are driven simultaneously by one sampling pulse. In the case of N sampling (for example, 12 dots, 24 dots, 48 dots, etc.) simultaneous sampling driving system in which writing is performed in units)). This N-dot simultaneous sampling driving method is also included in the concept of the dot sequential driving method in which the video signal Vsig and the precharge signal Psig are written in units of pixels.

  Specifically, in FIG. 7, for example, a set of 24 odd-numbered video lines Lvo and even-numbered video lines Lve, each of which is a set of 24 video signals Vsig supplied via a total of 48 video lines Lvo and Lve. Are divided into two systems of 24 dots (odd and even stages) and simultaneously sampled (24 dots + 24 dots simultaneously sampled) and written to the pixels 20 in the selected row. In FIG. 7, for simplification of the drawing, the sampling pulses SP1 to SPn are single-phased, and the anti-phase pulse generation circuits 133-1 to 133-n and the phase adjustment circuits 134-1 to 134-n are omitted. It shows.

  Furthermore, if only the independent video lines Lvo and Lve are wired in the odd-numbered stage and the even-numbered stage, the adjacent sampling pulses in the odd-numbered stage and the adjacent sampling pulses in the even-numbered stage can be made completely non-overlapping. Since the ghost is not generated, the clock pulses DCK1 and DCK2 having a narrower pulse width than the transfer pulses H1 to Hn are extracted and used as the sampling pulses SP1 to SPn. Sampling pulses SP1 to SPn having non-overlapping waveforms in which adjacent sampling pulses of the stage do not overlap are generated.

  In the active matrix type liquid crystal display device of the dot sequential drive system described above, in the present invention, in order to remove the lateral crosstalk due to the leakage of the sampling switches (horizontal switches) 135-1 to 135-n, the precharge switch 141- Similarly to the sampling switches 135-1 to 135-n, the reference numerals 1-141-n are also CMOS analog switches. Focusing on the occurrence of leakage due to transistor characteristics, the images by the sampling switches 135-1 to 135-n During the writing period of the signal Vsig, the leak amount of the precharge switches 141-1 to 141-n is set larger than the leak amount of the sampling switches 135-1 to 135-n when writing the black level.

  In order to make the leak amount of the precharge switches 141-1 to 141-n larger than the leak amount of the sampling switches 135-1 to 135-n when writing the black level during the writing period of the video signal Vsig In the embodiment, as shown in the waveform diagram of FIG. 6, after the precharge switches 141-1 to 141-n are turned off and the video signal Vsig is written from the precharge period, the display drive circuit 15 starts vertical stripes. A black level is output instead of the gray level for removal, and the potential of the precharge line Lp is set to a black potential during the writing period of the video signal Vsig. At this time, the polarity of the black level may be on the “H” level side or the “L” level side. Here, it is assumed that the video signal Vsig has the same polarity. Incidentally, conventionally, as shown in the waveform diagram of FIG. 8, even after shifting to the writing period of the video signal Vsig, the gray level is supplied to the precharge line Lp as it is.

  As described above, the leakage of the precharge switches 141-1 to 141-n is positively utilized, and the leakage amount of the precharge switches 141-1 to 141-n is set to the black level during the writing period of the video signal Vsig. Leakage based on the black level from the sampling switches 135-1 to 135-n to all the signal lines 17-1 to 17-n is made larger than the leakage amount of the sampling switches 135-1 to 135-n at the time of writing. Therefore, black image display is performed over the entire screen rather than horizontal crosstalk due to leakage of the sampling switches 135-1 to 135-n, and the horizontal crosstalk does not appear on the display screen.

  Accordingly, since the size of the transistor is not changed for the sampling switches 135-1 to 135-n which are horizontal switches, the capability of the sampling switches 135-1 to 135-n is kept large to some extent. Lateral crosstalk due to leakage of the sampling switches 135-1 to 135-n can be reliably removed. Moreover, by displaying a black image over the entire screen, not only horizontal crosstalk due to leakage of the sampling switches 135-1 to 135-n but also vertical crosstalk due to leakage of the pixel transistor (TFT21 in FIG. 2). First, all of the crosstalk relations can be removed and the contrast can be improved.

  In the waveform diagram of FIG. 6, the video signal Vsig (here, the black level) having the same polarity as the gray level is written before the gray level is written to all the signal lines 17-1 to 17-n in the precharge period. Although writing is performed, as shown in the waveform diagram of FIG. 9, a video signal Vsig having a polarity opposite to the gray level (Vcom reference) may be written. By adopting such a drive timing, as is clear from the comparison between FIG. 6 and FIG. 9, the latter (FIG. 9) requires fewer times of level switching in the 1H period. There is an advantage that it becomes easy.

  In the present embodiment, the leakage amount of the precharge switches 141-1 to 141-n is larger than the leakage amount of the sampling switches 135-1 to 135-n when writing the black level during the writing period of the video signal Vsig. In order to increase the size, the method of setting the potential of the precharge line Lp to a black potential during the off period of the precharge switches 141-1 to 141-n, that is, the writing period of the video signal Vsig is taken as an example. However, the same function can be realized by adopting the following method.

  For a transistor forming an analog switch, leakage is more likely when the channel width W is larger and when the channel length L is smaller, and the gate potential when the transistor is off is lower in the Nch transistor, and Pch It is known that the higher the transistor, the easier it is to leak.

  Therefore, the channel width Wp of the transistors of the precharge switches 141-1 to 141-n is set to be larger than the channel width Wh of the transistors of the sampling switches 135-1 to 135-n, or the precharge switches 141-1 to 141-141. The channel length Lp of the -n transistor is set to be smaller than the channel width Lh of the transistors of the sampling switches 135-1 to 135-n, or when the transistors forming the transistors of the precharge switches 141-1 to 141-n are turned off Is set to be lower for the Nch transistor and higher for the Pch transistor than the gate potential when the transistors of the sampling switches 135-1 to 135-n are turned off, so that the precharge switch is set during the writing period of the video signal Vsig. The leak amount of 41-1 to 141-n can be made larger than the leak amount of the sampling switches 135-1 to 135-n when writing the black level, and the same effect as the above embodiment can be obtained. it can.

  In the above-described embodiment, the case where the present invention is applied to a normally black mode liquid crystal display device has been described as an example. However, the present invention can also be applied to a normally white mode liquid crystal display device. When applied to a normally white mode liquid crystal display device, during the writing period of the video signal Vsig, the leak amount of the precharge switches 141-1 to 141-n is changed to the sampling switches 135-1 to 135 when writing the white level. By making it larger than the leak amount of −n, it is possible to obtain the same effect as when applied to a normally black mode liquid crystal display device.

  In the above embodiment, CMOS analog switches are used as the sampling switches 135-1 to 135-n. However, this is only an example, and an analog switch including only Nch or Pch transistors can be used. In this case, the single-phase clock pulses DCK1 and DCK2 may be extracted and used as they are as the sampling pulses SP1 to SPn. Therefore, the anti-phase pulse generation circuits 133-1 to 133-n and the phase adjustment circuits 134-1 to 134- n becomes unnecessary. The same applies to the precharge switches 141-1 to 141-n. By using the transfer clocks H1 to Hn as the single-phase precharge pulses P1 to Pn, the anti-phase pulse generation circuits 142-1 to 142-n and the phase The adjustment circuits 143-1 to 143-n are not necessary.

  In the above embodiment, the case where the present invention is applied to a liquid crystal display device using a liquid crystal cell as an electro-optical element of the pixel has been described as an example. However, the present invention is not limited to this application example, and the electric The present invention can be applied to all display devices in which pixels including electro-optical elements are two-dimensionally arranged in a matrix, such as an organic EL display device using organic EL (electro luminescence) elements as optical elements.

  The dot matrix driving type active matrix liquid crystal display device according to the present embodiment can be used as a general video display device, and for example, as a liquid crystal light valve in a projection type liquid crystal display device (liquid crystal projector device). be able to.

1 is a block diagram illustrating an outline of a configuration of a dot sequential drive type active matrix liquid crystal display device according to an embodiment of the present invention. FIG. It is a circuit diagram which shows an example of a circuit structure of a pixel (pixel circuit). It is a timing chart showing a timing relationship between a horizontal start pulse HST, horizontal clock pulses HCK and HCKX, two systems of clock pulses DCK1, DCK1X and DCK2, DCK2X, transfer pulses H1 to H4 and sampling pulses SP1, SP1X to SP4 and SP4X. 4 is a timing chart showing a timing relationship between a horizontal start pulse HST, precharge pulses PCK and PCKX, and a precharge signal Psig. It is a wave form diagram which shows an example of the video signal Vsig. It is a wave form diagram which shows an example of the precharge signal Psig. It is a block diagram which shows the more concrete structural example of a horizontal drive circuit. It is a wave form diagram which shows the prior art example of the precharge signal Psig. It is a wave form diagram which shows the other example of the precharge signal Psig. It is a figure which shows the state which the horizontal crosstalk generate | occur | produced. It is a figure where it uses for description of the generation | occurrence | production principle of a horizontal crosstalk.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Pixel array part, 12A, 12B ... Vertical drive circuit, 13 ... Horizontal drive circuit, 14 ... Precharge circuit, 15 ... Display drive circuit, 16 (16-1 to 16-m) ... Scanning line, 17 (17- 1 ... 17-n) ... Signal line, 18 ... Liquid crystal panel, 20 ... Pixel (pixel circuit), 21 ... TFT (pixel transistor), 22 ... Liquid crystal cell, 23 ... Retention capacitor, 135-1 to 135-n ... Sampling Switch (horizontal switch), 141-1 to 141-n ... precharge switch, Lv ... video line, Lp ... precharge line, Psig ... precharge signal, Vsig ... video signal

Claims (6)

A pixel array unit in which pixels including electro-optic elements are two-dimensionally arranged in a matrix;
Vertical driving means for selecting pixels of the pixel array section in units of rows;
A horizontal switch group for writing a video signal in units of pixels to pixels in a row selected by the vertical driving unit;
Prior to the writing of the video signal by the horizontal switch group, a precharge switch group that writes a precharge signal of a predetermined level in units of pixels in advance,
The leakage amount of the precharge switch group during the writing period of the video signal by the horizontal switch group is greater than the leakage amount of the horizontal switch group when writing the black level in the normally black mode and the white level in the normally white mode. And a control means for increasing the size of the display device. The control means sets the potential of the precharge line for transmitting the precharge signal to the precharge switch group during the writing period of the video signal by the horizontal switch group, in the normally black mode, the black potential, normally white The display device according to claim 1, wherein the white potential is set in the mode. The control unit sets a channel width of a transistor forming each switch of the precharge switch group to be larger than a channel width of a transistor forming each switch of the horizontal switch group. Display device. The control means sets a channel length of a transistor forming each switch of the precharge switch group to be smaller than a channel length of a transistor forming each switch of the horizontal switch group. Display device. The control means is configured such that the gate potential when the transistors forming the switches of the precharge switch group are off is lower in the Nch transistor than the gate potential when the transistors forming the switches of the horizontal switch group are off, The display device according to claim 1, wherein the Pch transistor is set to be high. A pixel array unit in which pixels including electro-optic elements are two-dimensionally arranged in a matrix;
Vertical driving means for selecting pixels of the pixel array section in units of rows;
A horizontal switch group for writing a video signal in units of pixels to pixels in a row selected by the vertical driving unit;
Prior to writing of the video signal by the horizontal switch group, a driving method of a display device comprising a precharge switch group that writes a precharge signal of a predetermined level in units of pixels in advance,
The leakage amount of the precharge switch group during the writing period of the video signal by the horizontal switch group is greater than the leakage amount of the horizontal switch group when writing the black level in the normally black mode and the white level in the normally white mode. The method for driving the display device is characterized by:

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