JP2007206465A - Active matrix type display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix type display device in which a time deviation of writing timing of an image signal due to propagation delay of selection pulse is compensated and, thereby, the image quality of the active matrix type display device of a line sequential scanning type is improved. <P>SOLUTION: The active matrix type display device comprises: a pixel array part 1; a scanning part 2 which drives the pixel array part 1; and a signal part 3. The selection pulses applied to respective scanning lines WS by the scanning part 2 cause the delay while being propagated through the scanning lines WS and, therefore, causes the time deviation of writing timing when the image signal is written into respective pixels 6 selected in a row unit. On the other hand, the signal part 3 preliminarily gives a relative retardation to the image signal supplied to respective signal lines SIG in accordance with the propagation delay of the selection pulses and, thereby, the time deviation of writing timing of an image signal due to propagation delay of selection pulse is compensated. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an active matrix display device. More specifically, the present invention relates to a technique for compensating a temporal shift in video signal writing timing caused by a propagation delay of a line sequential scanning pulse in a line sequential scanning type active matrix display device.

  In general, an active matrix display device includes a pixel array section, a scanning section that drives the pixel array section, and a signal section. The pixel array section includes row-like scanning lines, column-like signal lines, and matrix-like pixels arranged at portions where each scanning line and each signal line intersect. The signal unit supplies a video signal that changes in a horizontal scanning period to the column-shaped signal lines in parallel. The scanning unit sequentially applies a selection pulse to the row-shaped scanning lines (lines) in synchronization with the horizontal scanning cycle to select pixels in units of rows, and thus each pixel in the selected row (line) Write video signals in parallel from the corresponding signal lines. In one horizontal scanning cycle, video signals for one line are collectively written into pixels of one line. In this specification, this scanning method is called line sequential scanning.

  In general, a row-like scanning line is made of a metal wiring and has a resistance component. In addition, a parasitic capacitance is provided at a portion intersecting with the columnar signal line. Due to such a resistance component and parasitic capacitance, the selection pulse applied to each scanning line by the scanning unit is delayed during propagation through the scanning line. Due to this propagation delay, a time lag occurs in the timing at which the video signal is written to each pixel selected in units of rows. Due to this temporal shift, there is a problem that the video signal assigned to each pixel is not correctly written and the image quality is impaired.

  In view of the above-described problems of the prior art, the present invention compensates for the time lag of the video signal writing timing due to the propagation delay of the selection pulse, and thus the image quality of the active matrix display device of the line sequential scanning method. The purpose is to improve. In order to achieve this purpose, the following measures were taken. That is, the present invention includes a pixel array unit, a scanning unit and a signal unit for driving the pixel array unit, and the pixel array unit includes a row-shaped scanning line, a column-shaped signal line, each scanning line, and each signal line. And the signal unit supplies the video signal changing at a predetermined cycle in parallel to the column-shaped signal line, and the scanning unit In synchronization with the cycle, a selection pulse is sequentially applied to the row-like scanning lines to select pixels in units of rows, and video signals are then sent in parallel from the corresponding signal lines to each pixel in the selected row. The selection pulse applied to each scanning line by the scanning unit is delayed while propagating through the scanning line, so that an image is displayed on each pixel selected in units of rows. While there is a time lag in the timing at which signals are written, the signal section Corresponding to the propagation delay of the selection pulse, a relative phase difference is given to the video signal supplied to each signal line, so that the writing timing of the video signal due to the propagation delay of the selection pulse is reduced. It is characterized by canceling the time lag.

  In one aspect, the scanning unit is connected to one end of a row-shaped scanning line, and the selection pulse applied from one end of each scanning line increases in delay while propagating through each scanning line toward the other end. When the signal section supplies video signals to the column-shaped signal lines arranged between one end side and the other end side of the scanning line, the phase difference between them is different from the one end side of the scanning line. The video signal is supplied so as to increase relatively toward the end side. In another aspect, the scanning unit is connected to both ends of a row-shaped scanning line, and the selection pulses applied simultaneously from both ends of each scanning line increase in delay while propagating toward the center of each scanning line. When the signal unit supplies the video signal to the column-shaped signal lines arranged between both ends of the scanning line, the phase difference between them is relatively increased from both ends of the scanning line toward the center. Video signals are supplied so as to increase. Preferably, in the pixel array unit, each pixel includes at least a sampling transistor, a pixel capacitor, a light emitting element, and a drive transistor, and the sampling transistor has a gate connected to a corresponding scanning line and a source corresponding to a signal line. The drain is connected to the pixel capacitor, the transistor is turned on in response to a selection pulse applied to the scan line, the video signal supplied from the signal line is taken in and written to the pixel capacitor, and the drive transistor Causes the light emitting element to emit light with a luminance corresponding to the video signal written in the pixel capacitor, and the pixel array unit is configured such that a power line connected to the light emitting element included in each pixel intersects each scanning line. A parasitic capacitance that causes an increase in propagation delay of the selection pulse exists between the power supply line and the scanning line.

  According to the present invention, in the line-sequential scanning type active matrix display device, the phase of the video signal input line-sequentially to the column-shaped signal line is adjusted in accordance with the time lag of the timing of writing the video signal to the pixel. The pixel array portion (panel) is delayed along the left-right direction. Thereby, it is possible to cancel the time lag of the video signal writing timing due to the propagation delay of the selection pulse. In general, when the panel is increased in size, increased in definition, and driven at a higher frequency, the wiring resistance and parasitic capacitance causing the propagation delay increase, and the time lag of the video signal writing timing becomes significant. In the present invention, a time lag of this timing is canceled by giving a relative phase difference to the video signal input to each signal line in sequence. This makes it possible to easily improve the image quality of panels that have been increased in size, increased in definition, and driven at higher frequencies.

  In general, in a line sequential drive type active matrix display device, a signal portion samples and holds a video signal input from the outside line by line in accordance with a line sequential scanning period, and then distributes it to column-shaped signal lines. It is necessary to precisely sample and hold the video signal in synchronization with the line sequential scanning on the scanning unit side. In this regard, in the present invention, the relative phase of the video signal supplied to the signal line is adjusted to absorb the deviation in the video signal writing timing. Since there is a margin for this error, a large margin can be provided for the adjustment range of the sample hold on the signal unit side. According to the present invention, a large sample signal hold adjustment margin can be obtained even in a large panel, a high-definition panel, a double-speed scan panel, etc., and the display setting of these panels can be made very easy. is there. In particular, the present invention can exert a greater effect in an organic EL panel or the like in which the number of pixel wirings is multiplexed and a parasitic capacitance that causes a propagation delay of a selection pulse is included.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of an active matrix display device according to the present invention. As shown in the figure, the present active matrix display device basically comprises a pixel array unit 1, a scanning unit and a signal unit for driving the pixel array unit 1. The pixel array unit 1 is arranged at a portion where the row-shaped scanning lines WS1, WS2..., The column-shaped signal lines SIG1, SIG2, SIG3... SIGn, and each scanning line WS and each signal line SIG intersect. Matrix-shaped pixels 6. In the present embodiment, RGB three primary colors are assigned to each pixel 6, which is an active matrix display device capable of color display. However, the present invention is not limited to this, and may be an active matrix display device for monochrome display.

  The signal unit is composed of a signal driver 3 and a sample hold circuit (S / H) 4. The sample hold circuit 4 samples and holds a video signal input from the outside in a horizontal scanning cycle, and supplies it to the signal driver 3. The signal driver 3 distributes the video signal sampled and held in the horizontal scanning cycle to the respective signal lines SIG1 to SIGn, so that the video signal changing in the horizontal scanning cycle is parallel to the column signal lines ISG1 to SIGn. To supply. In general, the sample and hold circuit 4 samples and holds the video signal by digital processing, and the signal driver 3 converts the sampled and held digital video signal to analog and supplies it to each signal line SIG.

  The scanning unit is composed of a write scanner 2. The write scanner 2 sequentially applies a selection pulse to the row-like scanning lines WS1, WS2,... In synchronization with the horizontal scanning cycle to select the pixels 6 in units of rows, and thus to each pixel 6 in the selected row. The video signals are written in parallel from the corresponding signal lines SIG1 to SIGn. As a result, video signals are written into the pixel array unit 1 in a line sequential manner, and a desired image is displayed. In order to synchronize the write scanner 2, the signal driver 3, and the sample hold circuit 4, a timing generator (TG) 5 supplies a reference clock signal to each unit.

  The selection pulse applied to each scanning line WS by the light scanner 2 is delayed while propagating through the scanning line WS. This propagation delay is caused by the wiring resistance and parasitic capacitance of each scanning line WS. The parasitic capacitance is generated between the row-shaped scanning line WS and the column-shaped wiring (for example, the signal line SIG) intersecting with the scanning line WS. Due to the propagation delay of the selection pulse, a time lag occurs in the timing at which the video signal is written to each pixel 6 selected in units of rows (that is, line sequential). On the other hand, the signal section composed of the signal driver 3 and the sample hold circuit 4 gives a relative phase difference to the video signal supplied to each signal line SIG in advance corresponding to the propagation delay of the selection pulse. . As a result, it is possible to cancel the time lag in the video signal writing timing caused by the propagation delay of the selection pulse. In this embodiment, when the sample hold circuit 4 samples and holds a video signal input from the outside, a relative phase difference is given to the video signal supplied to each signal line in advance by adjusting the timing. Yes. In some cases, when the video signal sampled and held by the sample and hold circuit 4 is distributed to the signal lines SIG1 to SIGn by the signal driver 3, a relative phase difference may be given to each video signal.

  In this embodiment, the light scanner 2 constituting the scanning unit is connected to one end (the left end in the drawing) of the row-like scanning lines WS1, WS2,..., And the selection pulse applied from one end of each scanning line WS is The delay increases while propagating each scanning line WS toward the other end (the right end in the figure). On the other hand, when the signal driver 3 supplies video signals to the columnar signal lines SIG1 to SIGn arranged between one end side (left end side) and the other end side (right end side) of the scanning line WS, The video signal is supplied so that the phase difference relatively increases from one end side (left end side) to the other end side (right end side) of the scanning line WS. As a result, it is possible to cancel the time lag in the video signal writing timing caused by the propagation delay of the selection pulse.

  FIG. 2 is a timing chart for explaining the operation of the active matrix display device shown in FIG. This timing chart represents the waveform of the selection pulse and the video signal along the time axis T. In order to facilitate understanding, the selection pulses are indicated using the same reference numerals as the corresponding scanning lines WS1, WS2, WS3. Similarly, video signals are also denoted by the same reference numerals as the corresponding signal lines SIG1 to SIGn.

  The upper part of the timing chart shown in FIG. 2 shows the waveforms of the video signal SIG1 and selection pulses WS1, WS2, and WS3 observed on the signal line SIG1 side. The signal potential of the video signal SIG1 changes every horizontal period (1H), which is represented by V1, V2, V3. On the other hand, the selection pulse WS1 applied to the scanning line WS1 is substantially rectangular, and is applied to the scanning line WS1 in the first horizontal period. In synchronization with the fall of the selection pulse WS1, the signal potential V1 of the video signal SIG1 is taken and written in the pixels 6 arranged at the intersection of the scanning line WS1 and the signal line SIG1. The selection pulse WS2 is applied to the scanning line WS2 in the next horizontal cycle. The signal potential V2 of the video signal SIG1 is taken in at the falling timing T2 of the selection pulse WS2 and written into the pixel 6 at the intersection of the signal line SIG1 and the scanning line WS2. Similarly, at the next horizontal period, the selection pulse WS3 is applied to the scanning line WS3, and the signal potential V3 is written to the corresponding pixel 6 at the falling timing T3. In this way, the line sequential scanning of all the scanning lines WS1, WS2, WS3... Is completed over one field (1f), and an image for one field is displayed on the pixel array section.

  The lower part of the timing chart in FIG. 2 represents a video signal and a selection pulse that are observed on the rightmost signal line SIGn side. In the figure, for easy understanding, the waveform of the video signal applied to the leftmost signal line SIG1 is the same as the waveform of the video signal applied to the rightmost signal line SIGn. However, the present invention is not limited to this, and the video signal waveform varies depending on the pattern of the image displayed on the pixel array unit (panel). As a feature of the present invention, the video signal SIGn supplied to the right end side of the panel is given a predetermined phase difference ΔT to the video signal SIG1 supplied to the left end side of the panel. In other words, the video signal SIGn on the right end side is delayed by ΔT compared to the video signal SIG1 on the left end side.

  On the other hand, the selection pulses WS1, WS2, and WS3 observed on the signal line SIGn side at the right end have a propagation delay due to the influence of the wiring resistance and parasitic capacitance of each signal line, and the selection pulse observed on the left end side of the panel. The waveforms are also duller than WS1, WS2, WS3 (shown in the upper part of FIG. 2). For example, focusing on the selection pulse WS1, its fall timing is shifted backward from T1 to T1 ′ due to propagation delay. Similarly, the falling timing T2 of the second selection pulse WS2 is also shifted backward to T2 ′. Similarly, the fall timing T3 of the selection pulse WS3 is also shifted backward to T3 ′. Thus, a propagation delay occurs on the left end side and the right end side of the panel, and the amount thereof is approximately ΔT. In order to correspond to this, a phase difference ΔT is given between the video signals SIG1 and SIGn. As a result, even if the falling timing T1 ′ of the selection pulse WS1 shifts backward, the phase of the video signal SIGn is shifted backward by that amount, so that the signal voltage V1 can be correctly captured and written into the corresponding pixel 6. I can do it. Similarly, even if the falling timing T2 ′ of the selection pulse WS2 is shifted backward, the video signal SIGn is shifted later by that amount, so that the correct signal potential V2 can be written in the corresponding pixel 6. Similarly, even if the falling timing T3 ′ of the selection pulse WS3 is shifted backward, the video signal SIGn is shifted backward by that amount, so that the correct signal potential V3 can be written in the corresponding pixel 6. In this way, the display device of the line sequential drive system according to the present invention can write video signals from the signal lines SIG1 to SIGn to the pixels in each row in a line sequential manner in response to the selection pulse WS. At that time, the phase of the output of the signal driver 3 on the left and right of the panel is shifted in the sample and hold circuit 4. By aligning this shift amount ΔT with the delay amount of each scanning line WS, the video signal writing timings on the left and right sides of the panel can be made the same. As a result, even a panel having a large number of pixel wirings such as an organic EL can sufficiently cope with an increase in the size, definition, and double speed scanning of the panel.

  FIG. 3 is a schematic block diagram showing a second embodiment of the active matrix display device according to the present invention. In order to facilitate understanding, parts corresponding to those in the first embodiment shown in FIG. In the present embodiment, the scanning unit includes a pair of light scanners 2L and 2R. One write scanner 2L is arranged on the left side of the pixel array unit 1 and is connected to the row-shaped scanning line WS. The other write scanner 2R is arranged on the right side of the pixel array unit 1 and is also connected to each scanning line WS. As described above, the write scanners 2L and 2R are connected to both ends of the row-shaped scanning line WS, and the selection pulses applied simultaneously from both ends of each scanning line WS are delayed while propagating toward the center of each scanning line. Will increase. In accordance with this, when the signal driver 3 supplies video signals to the column-shaped signal lines SIG1 to SIGn arranged between the left and right ends of the scanning line WS, the phase difference between the signals from the left and right ends of the scanning line WS. A video signal is supplied so as to increase relatively toward the center. In this way, it is possible to cancel the time lag in the video signal writing timing due to the propagation delay of the selection pulse. In the case of the double-sided scanning method in which line-sequential scanning is performed from both the left and right sides of the pixel array unit 1 as in the present embodiment, the selection pulse at both ends of the panel changes sharply, but the pulse delay is most severe at the center of the panel. Therefore, in the double-sided drive panel as in this embodiment, the phase of the pre-sequential video signal is delayed at the center of the panel with respect to the left and right ends of the panel and input to each signal line. As a result, the same effect as in the first embodiment can be obtained.

  FIG. 4 is a block diagram showing a third embodiment of an active matrix display device according to the present invention. For ease of understanding, parts corresponding to those of the previous embodiment shown in FIGS. 1 and 3 are given corresponding reference numerals. This embodiment is a self-luminous display device in which a light emitting element such as an organic EL element is incorporated in a pixel. A signal driver 3 is arranged at the upper end with the pixel array unit 1 at the center, a drive scanner 7 is arranged at the right end, and a write scanner 2 is arranged at the left end. For simplicity of illustration, the sample hold circuit and the timing generator are omitted. In the pixel array section 1, row-like scanning lines WS and column-like signal lines SIG are arranged, and RGB three primary color pixels 6 are arranged at each intersection. Each pixel 6 includes a light emitting element such as an organic EL that emits light in any of the three primary colors of RGB. The scanning line WS is line-sequentially scanned by the write scanner 2. Video signals are supplied from the signal driver 3 to each signal line SIG in synchronization with line sequential scanning.

  In the pixel array unit 1, another row-like scanning line DS is arranged in parallel with the row-like scanning line WS. A drive scanner 7 is connected to each scanning line DS, and line-sequential scanning is thereby performed. The write scanner 2 and the drive scanner 7 are common in that the pixel array unit 1 is line-sequentially scanned, but the operation timing is different. The write scanner 2 performs line sequential scanning of the scanning lines WS in order to sample the video signal, while the drive scanner 7 scans the scanning lines DS in order to control the light emission time of the light emitting elements included in each pixel.

  In the pixel array section 1, the power supply line Vcc is arranged in parallel with the signal line SIG and intersects with the scanning lines WS and DS. The power supply line Vcc is arranged to supply power to the light emitting elements included in each pixel 6. Here, paying attention to the scanning line WS, since it intersects with the signal line SIG, there is a parasitic capacitance between them. Further, since the scanning line WS also intersects with the power supply line Vcc, a parasitic capacitance exists between them. In the figure, these parasitic capacitances are schematically represented by capacitor symbols. As described above, in the display device including the light emitting element in the pixel, since the wiring intersects in the pixel array unit 1 in a complicated manner, the parasitic capacitance causing the propagation delay of the selection pulse becomes large, and a countermeasure is indispensable.

  FIG. 5 is an enlarged circuit diagram of one pixel of the display device shown in FIG. As illustrated, the pixel circuit 6 includes a sampling transistor Tr1, a drive transistor Tr2, a switching transistor Tr3, a pixel capacitor Cs, and a light emitting element EL. The source of the sampling transistor Tr1 is connected to the signal line SIG, the drain is connected to one end of the pixel capacitor Cs, and the gate is connected to the scanning line WS. The other end of the pixel capacitor Cs is connected to the power supply line Vcc. The gate of the drive transistor Tr2 is connected to one end of the pixel capacitor Cs, the source is connected to the power supply line Vcc, and the drain is connected to the anode of the light emitting element EL via the switching transistor Tr3. The cathode of the light emitting element EL is connected to the ground line. The gate of the switching transistor Tr3 is connected to the scanning line DS.

  In this configuration, the sampling transistor Tr1 is turned on in response to the selection pulse applied from the write scanner 2 to the scanning line WS, and takes in the video signal supplied from the signal line SIG and writes it into the pixel capacitor Cs. The drive transistor Tr2 causes the light emitting element EL to emit light with luminance according to the video signal written in the pixel capacitor Cs. Specifically, the drive transistor Tr2 causes a drain current to flow from the power supply Vcc to the light emitting element EL in accordance with the potential Vgs of the video signal written in the pixel capacitor Cs. The light emitting element EL emits light with a luminance corresponding to the drain current. The switching transistor Tr3 inserted between the drive transistor Tr2 and the light emitting element EL is turned on / off by the drive scanner 7 in order to control the duty of the light emission time.

  FIG. 6 is a timing chart for explaining the operation of the third embodiment shown in FIGS. In order to facilitate understanding, the same notation as the timing chart of the first embodiment shown in FIG. 2 is adopted. The upper part of this timing chart shows the waveforms of the video signal SIG1 and selection pulses WS1, WS2, WS3 observed on the signal line SIG1 side closest to the write scanner 2. As shown in the figure, the selection pulses WS1, WS2, and WS3 have a steep fall without propagation delay or waveform dullness. The signal potential V1 of the video signal SIG1 is correctly sampled at the falling timing T1 of the selection pulse WS1. Similarly, the signal potential V2 is correctly sampled at the falling timing T2 of the selection pulse WS2. Further, the signal potential V3 is correctly sampled at the falling timing T3 of the selection pulse WS3.

  The lower part of the timing chart represents the waveform of the video signal and the selection pulse observed on the signal line SIGn side farthest from the write scanner 2. Note that the timing chart of FIG. 6 is a case where the phase shift of the video signal is not particularly performed, and the video signal SIG1 shown in the upper stage and the video signal SIGn shown in the lower stage are in phase. On the other hand, the selection pulses WS1, WS2 and WS3 have propagation delays and their waveforms are greatly dull. Therefore, the falling timing T1 ′ of the selection pulse WS1 is shifted backward. Nevertheless, since the amount of deviation is relatively small, the normal signal potential V1 can be sampled. Similarly, the falling timing T2 ′ of the selection pulse WS2 is shifted backward, but the normal signal potential V2 is barely sampled. Similarly, the falling timing T3 ′ of the selection pulse WS3 is also shifted backward, but the normal signal potential V3 is still sampled.

  As shown in the timing chart of FIG. 6, the output of the selection pulse is steep on the pulse input side, but on the opposite side, the pulse is delayed by the resistance and parasitic capacitance of the scanning line, and the time constant becomes longer. End up. Therefore, the sampling timing of the video signal shifts on the left and right sides of the panel. In the example of FIG. 6, it is possible to sample the signal at the same level on the left and right sides of the panel. However, when the video signal supplied from the outside is processed by the sample hold circuit, if the sample hold position shifts, Since different signal potentials are sampled on the left and right, the optimum sample hold position cannot be obtained. The situation during this time is shown in the timing chart of FIG. Unlike the timing chart of FIG. 6, in the timing chart of FIG. 7, the hold timing in the sample hold circuit is shifted backward as a whole. In this case, since the falling timing T1 of the selection pulse WS1 is still within the range of the signal potential V1 in the signal line SIG1 close to the write scanner 2, the normal signal potential V1 can be written to the pixel. Similarly, the normal signal potential V2 can be written to the corresponding pixel at the next falling timing T2. Further, the normal signal potential V3 can be written to the corresponding pixel at the next timing T3. On the other hand, as shown in the lower stage, on the signal line SIGn side far from the write scanner 2, it is impossible to capture a correct signal potential due to the propagation delay of the selection pulse. The falling timing T1 ′ of the selection pulse WS1 is beyond the range of the signal potential V1 and is applied to the next signal potential V2. For this reason, the signal potential V2 which is not regular is captured at the falling timing T1 ′. Similarly, an incorrect signal potential V3 is captured at the next timing T2 ′. Further, a different signal potential V4 is not taken in at the next falling timing T3 ′. In display devices using light-emitting elements as pixels, the number of scanning lines and power supply lines is increasing. For this reason, the parasitic capacitance of the scanning line also increases, and the left / right delay amount of the selection pulse becomes significant. For this reason, as described with reference to FIGS. 6 and 7, the margin of the sample hold position decreases. Further, when the panel is enlarged, the parasitic capacitance and the wiring resistance are further increased, and this problem becomes remarkable. In addition, when double speed scanning or the like is adopted, the drive frequency is doubled, and this problem becomes very remarkable. Therefore, in the present invention, a relative phase difference is given to the video signal supplied to each signal line in advance corresponding to the propagation delay of the selection pulse, so that the timing of writing the video signal due to the propagation delay of the selection pulse is reduced. The time lag is canceled out. As a result, the margin of the sample hold position in the sample hold circuit can be increased.

  FIG. 8 is a block diagram showing a fourth embodiment of the active matrix display device according to the present invention. For ease of understanding, parts corresponding to those in the previous embodiment are given corresponding reference numbers. In the present embodiment, a liquid crystal element is used for the pixel 6. That is, this embodiment is an active matrix type liquid crystal display device. In the pixel array section 1, row-like scanning lines WS and column-like signal lines SIG are arranged, and RGB three primary color pixels 6 are arranged at the intersection of the two. There is a stray capacitance between the scanning line WS and the signal line SIG, which causes a delay of the selection pulse propagating through the scanning line WS. .. Are sequentially supplied from the signal driver 3 to the signal lines SIG1, SIG2, SIG3.

  FIG. 9 is a circuit diagram showing one pixel of the liquid crystal display device shown in FIG. As shown in the figure, the pixel 6 formed in the pixel array section 1 is composed of a sampling transistor Tr1, a pixel capacitor Cs, and a liquid crystal element LC. The source of the sampling transistor Tr1 is connected to the signal line SIG, the gate is connected to the scanning line WS, and the drain is connected to one end of the pixel capacitor Cs. The other end of the pixel capacitor Cs is connected to the counter potential Vcom. The liquid crystal element LC is arranged in parallel with the pixel capacitor Cs. The liquid crystal element LC includes a pixel electrode connected to the drain of the sampling transistor Tr1, a counter electrode connected to the counter potential Vcom, and a liquid crystal held between the two electrodes. The sampling transistor Tr1 operates in accordance with the selection pulse WS applied from the write scanner 2 to the scanning line WS, samples the video signal SIG supplied from the signal driver 3 to the signal line SIG, and writes it to the pixel capacitor Cs. The potential of the video signal written in the pixel capacitor Cs is applied to both ends of the liquid crystal element LC, and the transmittance changes. A desired image is displayed on the pixel array unit 1 due to the change in transmittance. Also in the liquid crystal display device having such a configuration, a time lag occurs in the timing at which the video signal is written in each pixel 6 due to the propagation delay of the selection pulse. To compensate for this, the signal unit composed of the sample hold circuit 4 and the signal driver 3 gives a relative phase difference to the video signal supplied to each signal line SIG in advance corresponding to the propagation delay of the selection pulse. Therefore, a time lag in the video signal writing timing due to the propagation delay of the selection pulse is offset.

1 is a block diagram showing a first embodiment of an active matrix display device according to the present invention. It is a timing chart with which it uses for operation | movement description of 1st Embodiment. It is a block diagram which shows 2nd Embodiment of the active matrix type display apparatus concerning this invention. It is a block diagram which shows 3rd Embodiment of the active-matrix type display apparatus concerning this invention. It is a circuit diagram of a pixel included in a third embodiment. It is a timing chart used for operation | movement description of 3rd Embodiment. It is a timing chart similarly provided for operation | movement description of 3rd Embodiment. It is a block diagram which shows 4th Embodiment of the active matrix type display apparatus concerning this invention. It is a timing chart used for operation | movement description of 4th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pixel array part, 2 ... Write scanner, 3 ... Signal driver, 4 ... Sample hold circuit, 5 ... Timing generator, 6 ... Pixel

Claims (4)

It consists of a pixel array unit, a scanning unit and a signal unit for driving the pixel array unit,
The pixel array unit includes row-shaped scanning lines, column-shaped signal lines, and matrix-shaped pixels arranged at portions where each scanning line and each signal line intersect,
The signal unit supplies video signals that change at a predetermined cycle in parallel to the column-shaped signal lines,
The scanning unit sequentially applies a selection pulse to the row-shaped scanning lines in synchronization with the cycle to select pixels in units of rows, and each signal line corresponding to each pixel in the selected row is selected. An active matrix display device for writing video signals in parallel from
The selection pulse applied to each scanning line by the scanning unit is delayed while propagating through the scanning line, so that there is a time lag in the timing at which the video signal is written to each pixel selected in units of rows. While
The signal unit gives a relative phase difference to the video signal supplied to each signal line in advance corresponding to the propagation delay of the selection pulse,
Accordingly, an active matrix display device characterized in that the time lag in the writing timing of the video signal due to the propagation delay of the selection pulse is cancelled. The scanning unit is connected to one end of a row-shaped scanning line, and the selection pulse applied from one end of each scanning line increases in delay while propagating each scanning line toward the other end,
When the signal section supplies a video signal to a column-shaped signal line arranged between one end side and the other end side of the scanning line, the phase difference between the signal line is changed from one end side to the other end side of the scanning line. 2. The active matrix display device according to claim 1, wherein the video signal is supplied so as to relatively increase toward the front. The scanning unit is connected to both ends of a row-shaped scanning line, and the selection pulses applied simultaneously from both ends of each scanning line increase in delay while propagating toward the center of each scanning line,
When the signal section supplies video signals to the column-shaped signal lines arranged between both ends of the scanning line, the phase difference thereof relatively increases from both ends of the scanning line toward the center. 2. The active matrix display device according to claim 1, wherein a video signal is supplied in a similar manner. In the pixel array unit, each pixel includes at least a sampling transistor, a pixel capacitor, a light emitting element, and a drive transistor,
The sampling transistor has a gate connected to a corresponding scanning line, a source connected to a corresponding signal line, a drain connected to the pixel capacitor, and is turned on in response to a selection pulse applied to the scanning line. , Taking the video signal supplied from the signal line and writing it to the pixel capacitor;
The drive transistor causes the light emitting element to emit light with a luminance according to a video signal written to the pixel capacitor,
The pixel array section is arranged such that a power line connected to a light emitting element included in each pixel intersects each scanning line, and a parasitic capacitance that causes an increase in propagation delay of the selection pulse is connected to the power line. 2. The active matrix display device according to claim 1, wherein the active matrix display device exists between the scanning lines.

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