JP2010160492A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device which can be simplified in circuit constitution and control without providing a dedicated circuit and which can achieve reduction in power consumption without causing deterioration of image quality. <P>SOLUTION: The display device includes wide and down switch groups 1022 and 1024. For wide display, a plurality of scanning lines wired at an effective pixel part 101 are driven after a blank transfer circuit 103 performs blank transfer of a vertical start pulse VST to write a video signal. Then, the vertical start pulse VST is transferred to transfer lines corresponding to the first and the second mask regions 1012 and 1013 of the effective pixel part 101. The vertical start pulse VST transferred through the transfer lines is shifted in sequentially to drive the scanning lines one after another against each scanning part connected to a plurality of scanning lines arrayed at the first and the second mask regions 1012 and 1013 of the effective pixel part 101. By doing these, the wide and down switch groups 1022 and 1024 have the first and the second mask regions perform a black mask display simultaneously in parallel. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an active matrix display device capable of switching a plurality of screen displays having different aspect ratios (horizontal and vertical dimension ratios of a screen).

In recent years, with the development of high definition (HD) television system, so-called high vision system, it has a display screen of Japanese standard television system (NTSC system) with an aspect ratio of 4: 3 and an aspect ratio of 16: 9. A first display device capable of displaying a high-definition screen or a second display device having a high-definition display screen having an aspect ratio of 16: 9 and capable of displaying a high-definition screen having an aspect ratio of 4: 3 Is in practical use.
As this type of display device, for example, an active matrix liquid crystal display device in which liquid crystal cells are arranged in a matrix in a display region using a feature of being thin and having low power consumption, for example, is provided. Applied.

In this active matrix display device, a plurality of pixels are arranged in a matrix in the display area. The display device can be switched between screen display with an aspect ratio of 4: 3 (hereinafter referred to as normal display) and screen display with an aspect ratio of 16: 9 (hereinafter referred to as wide display).
Various proposals have been made regarding the switching system between the normal display and the wide display (see, for example, Patent Document 1 and Patent Document 2).

FIG. 13 is a block diagram illustrating a configuration example of the first display device.
The display device 1 includes an effective pixel portion 2, a vertical drive circuit 3, and a horizontal drive circuit 4 that form a display area.

In the effective pixel portion 2, a plurality of pixel circuits are arranged in a matrix.
For example, in the case of a liquid crystal display device, each pixel circuit includes a thin film transistor (TFT) as a switching element, a liquid crystal cell in which a pixel electrode is connected to a drain electrode (or source electrode) of the TFT, and a drain electrode of the TFT. It is constituted by a storage capacitor to which one electrode is connected.
For each of these pixel circuits, a scanning line is wired for each row along the pixel arrangement direction, and a signal line is wired for each column along the pixel arrangement direction.
The gate electrode of the TFT of each pixel circuit is connected to the same scanning line for each row. Further, the source electrode (or drain electrode) of each pixel circuit is connected to the same signal line for each column.
Each scanning line is driven by a vertical driving circuit, and each signal line is driven by a horizontal driving circuit 4.

The vertical drive circuit 3 basically performs a process of scanning in the vertical direction (row direction) for each field period and sequentially selecting each pixel circuit connected to the scan line in units of rows.
That is, when the scanning pulse SP1 is applied from the vertical driving circuit 3 to the first scanning line, the pixels in each column of the first row are selected, and the scanning pulse is applied to the second scanning line. When SP2 is given, the pixels in each column of the second row are selected. Similarly, scanning pulses SP3,..., SPm are sequentially applied to the third scanning line,..., The mth scanning line.
At the time of wide display, among the scanning lines wired to the effective pixel portion 2, as shown in FIG. 13, a plurality of scanning lines in the center in the figure, for example, 28 upper and lower scanning lines excluding 164 out of 220 in total. Are collectively driven to display a black mask. In this case, wide display with an aspect ratio of 16: 9 is performed over the center of the effective pixel portion 2 in the vertical direction.

As shown in FIG. 13, the vertical drive circuit 3 includes a wide control signal generation circuit (V WIDEGen) 31, vertical shift register group (VS / R) 32, central gate buffer group (GTBUFC) 33C, upper gate buffer group (GTBUFU) 33U, lower gate buffer group (GTBUFB) 33B, upper side Wide control circuit (WDCLU) 34U, lower wide control circuit (WDCLB) 34B, and a down switch group for switching whether the vertical start pulse VST is propagated from the upper side or the lower side of the effective pixel portion 2 (DWN · SW) 35.

The wide control signal generation circuit 31 activates the gate selection timing signal S31 based on each pulse signal of the wide pulse signal PWIDE, the enable signal EN, and the vertical clock VCK supplied from a control system (not shown) during wide display. Output to the wide control circuit 34U on the side and the wide control circuit 34B on the lower side.
The wide control signal generation circuit 31 holds the gate selection timing signal S31 in an inactive state during normal display when the wide pulse signal PWIDE is not received.

The vertical shift register group 32 includes a plurality of shift registers. The plurality of shift registers are provided corresponding to the gate buffers to which the scanning lines arranged for each row corresponding to the pixel arrangement are connected. Each shift register is supplied with a vertical start pulse VST for instructing the start of vertical scanning generated by a clock generator (not shown) and a vertical clock VCK (or vertical clocks VCK and VCKX having opposite phases to each other) as a reference for vertical scanning. .
For example, the shift register performs a shift operation in synchronization with the vertical clock VCK and supplies the vertical start pulse VST to the corresponding gate buffer.
Further, the vertical start pulse VST is propagated from the upper side or the lower side of the effective pixel portion 2 by the down switch group 34, and is sequentially shifted into each shift register.
Therefore, basically, each scanning line is sequentially driven through each gate buffer by the vertical clock supplied from the shift register.

When the upper side wide control circuit 34U and the lower side wide control circuit 34B configured by NAND circuits or the like receive the gate selection timing signal S31 in an active state, they are regarded as wide display, and each of the gate buffer groups 33U and 33B. Control is performed so that the scanning lines connected to the gate buffer are collectively driven.
As a result, the precharge black signal Psig set separately from the video signal by the horizontal drive circuit 4 is written to the pixel circuits arranged in a matrix on the upper side and the lower side of the effective pixel unit 2. That is, in order to perform wide display, black mask display is performed.

The wide control circuit 34U on the upper side and the wide control circuit 34B on the lower side are connected to the gate buffers of the gate buffer groups 33U and 33B as normal display when the gate selection timing signal S31 is received inactive. The scanning lines are controlled so as to be driven in order as usual.
In this case, when the scanning pulse SP1 is applied to the first scanning line from the gate buffer groups 33U, 33C, 33B of the vertical driving circuit 3, the pixels in each column of the first row are selected, and the second When the scanning pulse SP2 is applied to the scanning line in the row, the pixels in each column in the second row are selected. Similarly, scanning pulses SP3,..., SPm are sequentially applied to the third scanning line,..., The mth scanning line.

The horizontal drive circuit 4 receives an input video signal Vsig based on a horizontal start pulse HST for instructing the start of horizontal scanning and a horizontal clock HCK (or vertical clocks HCK and HCKX having opposite phases to each other) as a reference for horizontal scanning. Sampling is sequentially performed every 1H (H is a horizontal scanning period), and writing processing is performed on each pixel circuit selected in units of rows by the vertical driving circuit 3.
Further, the horizontal driving circuit 4 matrixes the precharge black signal Psig set separately from the video signal at the upper side and the lower side of the effective pixel unit 2 selectively driven by the vertical driving circuit 3 during wide display. The pixel circuits arranged in a pattern are written together.

  As shown in FIG. 13, the horizontal drive circuit 4 uses a horizontal shift register group (HS / R) 41, a wide control switch group (PSW) 42, a horizontal sampling switch group (HSW) 43, and a horizontal start pulse HST as effective pixels. A switch group (RGT / SW) 44 for switching between propagating from the left side or right side of the unit 2 is provided.

  The horizontal shift register group (HS / R) 41 has a plurality of shift registers corresponding to the pixel columns of the effective pixel unit 2, and when a horizontal start pulse HST is given by a clock generator (not shown), the horizontal clock HCK (or each other) The shift operation is performed in synchronization with the opposite-phase horizontal clocks HCK and XHCK). Thus, sample pulses synchronized with the horizontal clock are sequentially output from each shift register.

The wide control switch group 42 operatively operates a supply line of the precharge black signal Psig set separately from the video signal Vsig for wide display and a signal line arranged corresponding to the pixel column of the pixel unit 2. It has a plurality of switches to be connected.
When the wide control switch group 42 actively receives a wide pulse PWIDE during wide display, as shown in FIGS. 14A to 14C, all the switches are turned on collectively and the precharge black signal Psig is vertically applied. The pixel circuits arranged in a matrix on the upper side and the lower side of the effective pixel portion 2 selectively driven by the driving circuit 3 are collectively written.

The horizontal sampling switch group (HSW) 43 includes a plurality of switches that operatively connect the video signal Vsig and signal lines arranged corresponding to the pixel columns of the pixel unit 2.
The horizontal sampling switch group (HSW) 43 receives the sample pulses sequentially supplied from the horizontal shift register group (HS / R) 41 and sequentially turns on the switches to sequentially sample the video signal Vsig. Supply to each signal line.

JP-A-2-244880 Japanese Patent No. 3329009

  As described above, various proposals have been made for the switching system between the normal display and the wide display. However, in the configurations described in Patent Document 1 and Patent Document 2, a circuit for driving an area to be masked is provided. There is a disadvantage that it must be provided exclusively, and the circuit configuration is complicated and the control is complicated.

In the display device 1 shown in FIG. 13, in the vertical drive circuit 3, a wide selection signal for generating a gate selection timing signal S31 based on each pulse signal of the wide pulse signal PWIDE, the enable signal EN, and the vertical clock VCK at the time of wide display. When the control signal generation circuit 31 and the gate selection timing signal S31 are actively received, the scanning lines connected to the gate buffers of the gate buffer groups 33U and 33B are collectively driven, assuming that wide display is performed. It is necessary to provide a dedicated wide control circuit 34U on the upper side and a wide control circuit 34B on the lower side, which complicates the circuit configuration.
Further, since the wide control circuits 34U and 34B require a complicated logic circuit such as a NAND circuit as described above, the circuit configuration of the scanning unit (driving unit) of the scanning line becomes complicated and the power consumption increases. There is a disadvantage of inviting.

  Further, since the precharge black signal Psig is collectively written in the pixel circuits arranged in a matrix on the upper side and the lower side of the effective pixel portion 2 selectively driven by the vertical drive circuit 3, There is a restriction on the timing of driving and the signal Psig, horizontal stripes appear at the time of wide display, there is a problem in image quality, and a large capacity is equivalently driven, and there is a disadvantage that power consumption increases. .

As a solution to this problem, instead of writing all the pixel circuits arranged in a matrix on the upper side and the lower side of the effective pixel unit 2 in a lump, for example, as shown in FIGS. 14D and 14E, The upper side wide control circuit 34U and the lower side wide control circuit 34B of the vertical drive circuit 3 are divided into odd-numbered (even) scan lines and even-numbered (even) scan lines. Such a system is also known.
In this case, although the occurrence of lateral stripes can be prevented, the vertical drive circuit 3 selects and drives a plurality of scanning lines at once even if divided into two, and the precharge black signal Psig is sent to the upper side of the effective pixel portion 2 and Since the pixel circuits arranged in a matrix on the lower side are collectively written, it is difficult to sufficiently reduce the capacity to be driven, and as a result, there is still a disadvantage that the power consumption increases.

  An object of the present invention is to provide a display device that can simplify circuit configuration and control without providing a dedicated circuit, and can realize low power consumption without causing deterioration of image quality. It is in.

In order to achieve the above object, a first aspect of the present invention is a display device having at least a first display mode and a second display mode having different aspect ratios, wherein a pixel circuit for writing pixel data through a switching element is provided. A plurality of rows are arranged in a matrix and assigned as a mask area in the first display mode. In the first display mode, mask pixel data is written to each pixel circuit in the mask area, and Video pixel data is written to each pixel circuit in an area excluding the mask area, and in the second display mode, a pixel unit in which video pixel data is written to each pixel circuit in the entire area including the mask area;
A plurality of scanning lines arranged to correspond to the row arrangement of the pixel circuits, a plurality of scanning lines for controlling the conduction of the switching elements, and a plurality of scanning lines arranged to correspond to the column arrangement of the pixel circuits to propagate the pixel data. And a plurality of scanning units that selectively scan the scanning lines by applying a scanning signal to the connected scanning lines in response to a start pulse. A vertical drive circuit, and the vertical drive circuit includes a transfer line through which the start pulse is forwardly transferred in one direction, and a plurality of lines arranged in an area excluding the mask area in the first display mode. For each scanning unit connected to the scanning line, the start pulse transferred through the transfer line is sequentially shifted in, and then the start pulse is masked in the pixel unit. The start pulse transferred through the transfer line is sequentially shifted into each of the scanning units connected to the plurality of scanning lines arranged in the mask region of the pixel unit. And a switch circuit that sequentially shifts in the start pulse transferred from the transfer line to all the scanning units in the second display mode.

  Preferably, in addition to a normal transfer mode in which the transfer line is transferred in one direction, the start pulse has an inversion transfer mode in which the start pulse is transferred in a direction opposite to the one direction. In the mode, in the first display mode, the transfer line is transferred in the reverse direction to each scanning unit connected to a plurality of scanning lines arranged in an area excluding the mask area. The pulses are sequentially shifted in, and then the start pulse is transferred in the reverse direction to the transfer line corresponding to the mask area of the pixel portion, and is connected to a plurality of scanning lines arranged in the mask area of the pixel portion. For each scanning unit, the start pulse transferred in the reverse direction on the transfer line is shifted in order, and in the second display mode, the upper scanning is performed on all scanning units. The transfer line is sequentially shifted in the start pulse which is transferred to the opposite direction.

  Preferably, there is provided an empty transfer circuit that performs idle transfer for a predetermined period before transferring the start pulse to the transfer line corresponding to the area excluding the mask area.

  Preferably, there is provided an empty transfer circuit that performs idle transfer for a predetermined period before transferring the start pulse to the transfer line corresponding to the area excluding the mask area.

  Preferably, in the first display mode, the video pixel data is written to a pixel circuit connected to one scanning line that is scanned in the order of the areas excluding the mask area, and the plurality of signals The mask pixel data is sequentially transferred to a line, and the mask pixel data is written to a pixel circuit connected to a scan line that is scanned in the order of the mask area. In the second display mode, The image pixel data is sequentially transferred to the plurality of signal lines, and the image pixel data is transferred to a pixel circuit connected to a scan line that is scanned in the order of the entire region including the mask region. A horizontal drive circuit for writing is provided.

  A second aspect of the present invention is a display device having at least a first display mode and a second display mode having different aspect ratios, wherein pixel circuits for writing pixel data through switching elements are arranged in a matrix, Two regions are assigned as a first mask region and a second mask region in the first display mode with a predetermined display region including a plurality of lines, and in the first display mode, the first region And mask pixel data is written in each pixel cell in the second mask region, and video pixel data is written in each pixel circuit in the display region sandwiched between the first and second mask regions. In the second display mode, a pixel portion in which video pixel data is written to each pixel circuit in the entire region including the first and second mask regions, and the pixel A plurality of scanning lines arranged to correspond to the row arrangement of the paths, a plurality of scanning lines for controlling the conduction of the switching elements, and a plurality of signals arranged to correspond to the column arrangement of the pixel circuits to propagate the pixel data And a plurality of scanning lines connected to each other, and having a plurality of scanning units for selectively scanning the scanning lines by applying a scanning signal to the connected scanning lines in response to a start pulse. The vertical drive circuit in a display line excluding the first and second mask areas in the first display mode, and a transfer line in which the start pulse is positively transferred in one direction. For each scanning unit connected to the plurality of arranged scanning lines, the start pulse transferred on the transfer line is shifted in order, and then the start pulse is transferred to the scanning line. Transferred to transfer lines corresponding to the first mask region and the second mask region of the pixel portion, respectively, and connected to a plurality of scanning lines arranged in the first mask region and the second mask region of the pixel portion. The start pulse transferred through the transfer line is sequentially shifted in for each scanning unit, and the start pulse transferred through the transfer line is sequentially shifted for all the scanning units in the second display mode. A switch circuit to be turned on.

  Preferably, in addition to a normal transfer mode in which the transfer line is transferred in one direction, the start pulse has an inversion transfer mode in which the start pulse is transferred in a direction opposite to the one direction. In the mode, in the first display mode, the transfer line is reversed with respect to each scanning unit connected to a plurality of scanning lines arranged in a region excluding the first and second mask regions. The start pulse transferred in the direction is sequentially shifted in, and then the start pulse is transferred in the reverse direction to the transfer lines corresponding to the first mask region and the second mask region of the pixel portion, For each scanning unit connected to a plurality of scanning lines arranged in the first mask region and the second mask region, the start line is transferred in the reverse direction through the transfer line. Scan sequentially shifted in the, above the second display mode, the transfer line is sequentially shifted in the start pulse is transferred to the opposite direction with respect to the entire scanning unit.

  Preferably, the start pulse transferred on the transfer line corresponding to the first mask area of the pixel portion is transferred to the transfer line corresponding to the area excluding the first and second mask areas. A transfer blocking circuit for blocking;

  Preferably, the start pulse transferred on the transfer line corresponding to the second mask area of the pixel portion is transferred to the transfer line corresponding to the area excluding the first and second mask areas. A transfer blocking circuit for blocking;

  Preferably, there is provided an empty transfer circuit that performs idle transfer for a predetermined period before transferring the start pulse to the transfer line corresponding to an area excluding the first and second mask areas.

  Preferably, in the first display mode, the video pixel data is written to a pixel circuit connected to a scanning line that is scanned in the order of the areas excluding the first and second mask areas, The mask pixel data is sequentially transferred to the plurality of signal lines, and the mask pixel is connected to a pixel circuit connected to a scan line that is scanned in the order of the first mask region and the second mask region. In the second display mode, the video pixel data is sequentially transferred to the plurality of signal lines and is scanned in the order of the entire area including the mask area in the second display mode. A horizontal driving circuit for writing the pixel data for video to the pixel circuit connected to the line;

According to the present invention, for example, in the first display mode, the transfer line is transferred to each scanning unit connected to the plurality of scanning lines arranged in the area excluding the mask area by the vertical drive circuit. The start pulse is shifted in sequentially, and each scanning line is driven in turn.
At this time, the image pixel data is sequentially transferred to a plurality of signal lines, and the image pixel data is written to the pixel circuit connected to one scanning line that is scanned in the order of the areas excluding the mask area. .
Subsequently, the start pulse is transferred to the transfer line corresponding to the mask area of the pixel portion. Then, the vertical drive circuit sequentially shifts in the start pulse transferred through the transfer line to each scanning unit connected to the plurality of scanning lines arranged in the mask region of the pixel unit, Driven in order.
At this time, the pixel data for masking is sequentially transferred from the horizontal driving circuit to the plurality of signal lines, and is masked to the pixel circuit connected to one scanning line that is selectively scanned for each divided group of the mask region. Pixel data is written.
As a result, an image having the first aspect ratio is displayed on the pixel portion excluding the mask area.
In the second display mode, the vertical drive circuit sequentially shifts in the start pulse transferred from the transfer line to all the scanning units, and drives each scan line in turn.
At this time, the pixel data for video is written into the pixel circuit connected to one scanning line scanned in the order of the entire area including the mask area by the horizontal drive circuit.
As a result, an image having the second aspect ratio is displayed on all the pixel portions including the mask area.

  According to the present invention, there is an advantage that the circuit configuration and control can be simplified and low power consumption can be realized without deteriorating the image quality.

It is a figure which shows the structural example of the active matrix type display apparatus which concerns on one Embodiment of this invention. FIG. 2 is a circuit diagram illustrating a specific configuration example of a pixel portion of the circuit of FIG. 1. It is a figure which shows the specific example about the scanning line allocated to a display area and the 1st and 2nd mask area | region at the time of a wide display. It is a figure which shows typically the video signal and black mask writing procedure at the time of the wide display of the liquid crystal display device which concerns on this embodiment. It is a figure for demonstrating the specific structural example of the idle transfer circuit which concerns on this embodiment, an upper side down and wide switch group, a down switch group, and a lower side down and wide switch group. It is a circuit diagram which shows the structural example of each transfer switch which comprises the empty transfer circuit which concerns on this embodiment, an upper side down and wide switch group, a down switch group, and a lower side down and wide switch group. It is a figure which shows four display modes, the setting level of a wide signal and a down signal, and the ON (ON) / OFF (OFF) state of each A-SW-H-SW. It is a figure which shows the operating state of the empty transfer circuit, the wide and down switch group on the upper side, the down switch group, and the wide and down switch group on the lower side in the wide display mode and in the normal transfer mode. It is a figure which shows the black mask write-in timing with respect to the 1st and 2nd mask area | region at the time of a wide display mode. It is a figure which shows the operating state of the empty transfer circuit, the wide and down switch group on the upper side, the down switch group, and the wide and down switch group on the lower side in the wide display mode and in the upside down transfer mode. It is a figure which shows the operating state of the empty transfer circuit, the upper side wide and down switch group, the down switch group, and the lower side wide and down switch group in the normal transfer mode in the normal display mode. It is a figure which shows the operating state of the empty transfer circuit, the upper side wide and down switch group, the down switch group, and the lower side wide and down switch group in the normal display mode and the upside down transfer mode. It is a circuit diagram which shows the structural example of the conventional active matrix type display apparatus. It is a timing chart of the main signals of the circuit of FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram illustrating a configuration example of an active matrix display device according to an embodiment of the present invention using, for example, a liquid crystal cell as a pixel display element (electro-optical element).
The display device 100 according to the present embodiment has an NTSC display screen with an aspect ratio of 4: 3, and is configured to be able to display an HDTV screen with an aspect ratio of 16: 9. In other words, the display device 100 can switch between screen display (normal display) with an aspect ratio of 4: 3 in the second display mode and screen display (wide display) with an aspect ratio of 16: 9 in the first display mode. Composed.

  As shown in FIG. 1, the display device 100 includes an effective pixel unit 101, a vertical drive circuit (VDRV) 102, an empty (pseudo) transfer circuit 103, and a horizontal drive circuit (HDRV) 104.

In the effective pixel unit 101, as shown in FIG. 2, a plurality of pixel circuits PXLC are arranged in an m × n matrix. Specifically, for example, 220 (= m) × 560 (= n) pixel circuits are arranged so that normal display is possible as a whole.
The effective pixel portion 101 corresponds to the wide display which is the first display mode, and a first mask region 1012 including a plurality of scanning lines on the upper side and the lower side in the figure with the central display region 1011 in between. And a second mask area 1013 is allocated.
For example, 164 out of the total 220 scan lines are assigned to the central display area 1011, and the upper and lower 28 scan lines excluding the 164 lines are assigned as the first mask area 1012 and the second mask area 1013, respectively. It has been.
As shown in FIG. 2, each pixel circuit PXLC includes a TFT (thin film transistor) 101 as a switching element, a liquid crystal cell LC101 having a pixel electrode connected to a drain electrode (or source electrode) of the TFT 101, and a TFT 101 The storage capacitor Cs101 includes one electrode connected to the drain electrode.
For each of these pixel circuits PXLC, scanning lines 105-1 to 105-m are wired along the pixel arrangement direction for each row, and signal lines 106-1 to 106-n are arranged for each column. It is wired along the direction.
The gate electrode of the TFT 101 of each pixel circuit PXLC is connected to the same scanning line 105-1 to 105-m in each row unit. In addition, the source electrode (or drain electrode) of each pixel circuit PXLC is connected to the same signal line 106-1 to 106-n for each column.
Further, in a general liquid crystal display device, the storage capacitor line Cs is independently wired, and the storage capacitor Cs101 is formed between the storage capacitor line and the connection electrode, and Cs has a common voltage VCOM and an in-phase pulse. It is input and used as a holding capacity.
The other electrode of the storage capacitor Cs101 of each pixel circuit PXLC is connected to the supply line 107 of the common voltage VCOM whose polarity is inverted during the DC or one horizontal scanning period (1H).

  The scanning lines 105-1 to 105-m are driven by the vertical driving circuit 102, and the signal lines 106-1 to 106-n are driven by the horizontal driving circuit 103.

The vertical drive circuit 102 basically scans in the vertical direction (row direction) for each field period and sequentially selects each pixel circuit PXLC connected to the scan lines 105-1 to 105-m in units of one row. Perform the process.
That is, the vertical drive circuit 102 applies the scan pulse SP1 to the scan line 105-1, selects the pixels in each column of the first row, and applies the scan pulse SP2 to the scan line 105-2. A pixel in each column in the second row is selected. In the same manner, scanning pulses SP3,..., SPm are sequentially applied to the scanning lines 105-3,.

At the time of wide display, the vertical drive circuit 102, among the scanning lines wired to the effective pixel unit 101, as shown in FIG. A video signal is written to each scanning unit connected to 164 scanning lines by sequentially shifting in the vertical start pulse VST transferred through a predetermined transfer line and sequentially driving the scanning lines.
Subsequently, the vertical drive circuit 102 transfers the vertical start pulse VST to the transfer lines corresponding to the first mask region 1012 and the second mask region 1013 of the effective pixel unit 101, respectively, and the first pixel of the effective pixel unit 101 is transferred. The vertical start pulse VST transferred through the transfer line is sequentially shifted in for each scanning section connected to a plurality (28 each) of scanning lines arranged in the mask area 1012 and the second mask area 1013 By sequentially driving the scanning lines, 28 mask lines for 28 scanning lines in the first mask region 1012 and the second mask region 1013 are written in parallel at the same time, thereby displaying a black mask. To do.
In this case, wide display with an aspect ratio of 16: 9 is performed over the center of the effective pixel portion 101 in the vertical direction.
At this time, the polarity of the common voltage VCOM is inverted every constant DC voltage or every horizontal scanning period (1H).

  Further, the vertical drive circuit 102 applies the vertical start pulse VST transferred from the central display region 1011 to the second mask region 1013 which is the lower wide black mask portion in the drawing at the time of wide display. And the transfer pulse by the first mask region 1011 which is the upper wide black mask portion is the lower end of the upper black mask portion, that is, the central display region. A transfer blocking circuit having a function of stopping transfer at a position where the boundary with 1011 is reached is provided.

Note that the liquid crystal display device 100 according to the present embodiment starts the video display in the effective display area 1011 in the central portion in the vertical drive circuit 102 at the time of wide display. An empty transfer circuit 103 having a function of empty transferring the vertical start pulse VST only during a black mask period (for example, 9H period) is provided.
Here, idle transfer refers to transferring only pulses without performing actual writing.

FIG. 4 is a diagram schematically showing a video signal and black mask writing procedure during wide display of the liquid crystal display device 100 according to the present embodiment.
As shown in FIG. 4, at the time of wide display, the vertical start pulse VST is first empty-transferred for the wide black mask period in the empty transfer circuit 103, and then input and transferred to a transfer line corresponding to the effective display area 1011 in the central portion. After the video signal is written to the display area 1011, the vertical start pulse VST transferred from the central display area 1011 to the second mask area 1013 which is the lower wide black mask part is Black mask writing for 28 scanning lines of 28 lines in the first mask area 1012 and the second mask area 1013 is simultaneously performed in parallel in the first mask area 1011 which is the black mask portion. The black mask display is performed.

  Hereinafter, the configurations and functions of the vertical drive circuit 102 and the idle transfer circuit 103 will be described in more detail.

As shown in FIG. 1, the vertical drive circuit 102 according to the present embodiment includes a vertical shift register group (VS / R) 1021, an upper side down and wide switch group (DWN + WIDE SW) 1022, a central down switch group ( DWN · SW) 1023, a lower down and wide switch group (DWN + WIDE SW) 1024, and a gate buffer group (GTBUF) 1025.
Among these components, the down and wide switch group (DWN + WIDE SW) 1022 at the upper side, the down switch group (DWN / SW) 1023 at the center, and the down and wide switch group (DWN + WIDE SW) 1024 at the lower side of the present invention. The switch circuit concerning is comprised.
The vertical shift register group (VS / R) 1021 and the gate buffer group (GTBUF) 1025 constitute a scanning unit according to the present invention by the shift register and the gate buffer corresponding to each scanning line.

The vertical shift register group 1021 has a plurality of shift registers VSR. The plurality of shift registers are provided corresponding to the gate buffers to which the scanning lines arranged for each row corresponding to the pixel arrangement are connected.
Each shift register VSR is supplied with a vertical start pulse VST for instructing the start of vertical scanning generated by a clock generator (not shown) and a vertical clock VCK (or vertical clocks VCK and VCKX having opposite phases to each other) as a reference for vertical scanning. The
For example, the shift register shifts the vertical start pulse VST in synchronization with the vertical clock VCK and supplies it to the corresponding gate buffer.
Further, the vertical start pulse VST is propagated from the upper side or the lower side of the effective pixel unit 101 by the down switch groups 1022 to 1024, and is sequentially shifted into each shift register.
Therefore, basically, each scanning line is sequentially driven through each gate buffer of the gate buffer group 1025 by the vertical clock supplied from the shift register VST.

The down and wide switch group 1022 on the upper side receives a wide signal wd at a low level (a level indicating a normal display mode) and receives a down signal dn at a high level (a level indicating a normal transfer mode). The vertical start pulse VST is applied to the shift registers arranged in order from the upper side to the lower side of the effective pixel portion 101 and also from the upper side to the lower side, specifically from the first to the first. The data is input to the 28th shift register VSR28, input to the lowermost shift register and the 28th shift register VSR28, and then transferred to the down switch group 1023 in the next stage.
The down and wide switch group 1022 functions as a normal down switch when the wide signal wd is received at a low level and the down signal dn is received at a low level (a level indicating the upside down transfer mode). The vertical start pulse VST propagated from the lowermost side of the effective pixel unit 101 in order from the lower side to the upper side, and similarly to the shift registers arranged from the lower side to the upper side, specifically from the 28th. The data is input to the first shift register VSR1.

On the other hand, when the down and wide switch group 1022 on the upper side receives the wide signal wd at a high level (level indicating the wide display mode) and receives the down signal dn at a high level, it functions as a wide and down switch. The vertical start pulse VST distributed from the boundary between the down switch group 1022 and the down switch group 1023 of the wide switch group 1024 is sequentially directed from the upper side to the lower side of the effective pixel unit 101 and from the upper side to the lower side. Specifically, the shift registers arranged in this manner are input to the first to 27th shift registers VSR27 and are prevented from being transferred to the down switch group 1023 in the next stage.
The down and wide switch group 1022 on the upper side functions as a wide and down switch when receiving the wide signal wd at a high level (level indicating wide display) and receiving the down signal dn at a low level. The vertical start pulse VST transferred from 1023 is transferred to the shift register arranged in order from the lower side to the upper side of the effective pixel unit 101 in the order from the lower side to the upper side. To the first shift register VSR1 and further to the dummy shift register, and transfer to the output terminal (Vout).

  The down switch group 1023 controls the corresponding shift registers VSR29 to VSR192 or VSR192 while transferring the vertical start pulse VST forwardly or upside down in accordance with the supply level of the down signal dn regardless of the supply level of the wide signal wd. Shift in to VSR29 in order.

The down and wide switch group 1024 on the lower side receives a wide signal wd at a low level (a level indicating a normal display mode) and receives a down signal dn at a high level (a level indicating a normal transfer mode). The vertical start pulse VST is applied to the shift registers arranged in order from the upper side to the lower side of the effective pixel portion 101 in the same manner from the upper side to the lower side. The data is input to the 220th shift register VSR193 to VSR220. As in the case of the upper down and wide switch group 1022, a two-stage dummy shift register is arranged after the lower down and wide switch group 1024. The lower down and wide switch group 1024 is input to the dummy shift register and then transferred to the output terminal (Vout).
The down and wide switch group 1024 functions as a normal down switch when it receives the wide signal wd at a low level and the down signal dn at a low level (a level indicating the upside down transfer mode), and the down switch group 1023 The vertical start pulses VST propagated from the lower pixel side to the upper side of the effective pixel unit 101 in order from the lower side to the upper side, more specifically, from the 220th to the second. The signals are sequentially input to the 193rd shift registers VSR220 to VSR193 and transferred to the down switch group 1023 in the next stage.

On the other hand, the down and wide switch group 1024 on the lower side functions as a wide and down switch when receiving the wide signal wd at a high level (level indicating the wide display mode) and receiving the down signal dn at a high level. When dn is received at a high level, the vertical start pulses VST distributed from the down switch group 1023 are arranged in order from the upper side to the lower side of the effective pixel unit 101, similarly from the upper side to the lower side. The data is input to the shift register VSR, input to the lowermost shift register VSR220, further input to the dummy shift register, and then transferred to the output terminal (Vout).
The lower down and wide switch group 1024 functions as a wide and down switch when receiving the wide signal wd at a high level (level indicating wide display) and receiving the down signal dn at a low level. The vertical start pulse VST distributed from the boundary of the down and wide switch group 1022 with the down switch group 1023 is sequentially applied from the lower side to the upper side of the effective pixel unit 101 and also from the lower side to the upper side. After being input to the arranged shift registers, specifically, to the two-stage dummy register registers, they are input to the 220th to 194th shift registers VSR194 and transferred to the down switch group 1023 of the next stage. To prevent it.

A specific configuration example of the idle transfer circuit 103, the upper-side down and wide switch group 1022, the down-switch group 1023, and the lower-side down and wide switch group 1024 will be described with reference to FIG.
In this example, there are 220 scanning lines, and 28 on the upper side and 28 on the lower side are assigned for the black mask at the time of wide display.
The transferred pulse is the vertical start pulse VST or its inverted signal pulse XVST.
In the figure, VST transfer from the upper side to the lower side is normal transfer, and VST transfer from the lower side to the upper side is upside down transfer. Two dummy shift registers VSRDU1 and VSRDU2 are provided on the upper side. Similarly, two dummy shift registers VSRDB1 and VSRDB2 are provided on the lower side.

  The transfer lines include upper and lower switch groups 1022, down switch group 1023, first and second transfer lines TML1 and TML2 wired over the lower and wide switch group 1024, and empty transfer. A third transfer line TML3 for connecting to the second transfer line TML2 on the upper side of the down and wide switch group 1022 from the output of the circuit 103 branches from the third transfer line TML3 and the upper side The fourth transfer line TML4 for connecting to the first transfer line TML1 at the bottom of the down and wide switch group 1022 (the boundary with the down switch group 1023) branches from the third transfer line TML3 and the lower part Side down and top of wide switch group 1024 (down switch The fifth transfer line TML5 for connecting to the second transfer line TML2 at the boundary between the second transfer line TML2 and the third transfer line TML3, and the lower side down and at the bottom of the wide switch group 1024 The sixth transfer line TML6 for connecting to the first transfer line TML1, the lower side down and the second transfer line TML2 at the top of the wide switch group 1024 (boundary with the down switch group 1023) branches Then, the seventh transfer line TML7 for connecting to the upper side down and the second transfer line TML2 at the top of the wide switch group 1022 branches from the first transfer line TML1 at the top of the down switch group 1023 The lower side down and wide switch group 1024 are connected to the lowermost first transfer line TML1. The first transfer line TML1 at the top of the down and wide switch group 1022 on the upper side and the bottom of the second transfer line TML2 and the output terminal (Vout) It has a ninth transfer line TML9.

  As a transfer switch, a transfer A switch (hereinafter A-SW), a transfer B switch (hereinafter B-SW), a transfer C switch (hereinafter C-SW), a transfer D switch (hereinafter D-SW), Each of a transfer E switch (hereinafter referred to as E-SW), a transfer F switch (hereinafter referred to as F-SW), a transfer G switch (hereinafter referred to as G-SW), and a transfer H switch (hereinafter referred to as H-SW) is started vertically. By appropriately arranging on the transfer line of the pulse VST or its inverted signal XVST, normal transfer and upside down transfer in normal display or wide display are realized.

  Here, specific configuration examples of A-SW to H-SW will be described with reference to FIGS.

  As shown in FIG. 6A, the A-SW is configured by connecting the sources and drains of a p-channel MOS (PMOS) transistor PTA1 and an n-channel MOS (NMOS) transistor NTA1. The gate of the NMOS transistor NTA1 is connected to the supply line of the down signal dn, and the gate of the PMOS transistor PTA1 is connected to the supply line of the inverted signal xdn of the down signal.

  As shown in FIG. 6B, the B-SW is configured by connecting the sources and drains of the PMOS transistor PTB1 and the NMOS transistor NTB1. The gate of the PMOS transistor PTB1 is connected to the supply line of the down signal dn, and the gate of the NMOS transistor NTB1 is connected to the supply line of the inverted signal xdn of the down signal.

  As shown in FIG. 6C, the C-SW is configured by connecting PMOS transistors PTC1 and PTC2 connected in series and NMOS transistors NTC1 and NTC2 connected in series in parallel. The gate of the PMOS transistor PTC1 is connected to the supply line of the inverted signal xdn of the down signal, the gate of the NMOS transistor NTC1 is connected to the supply line of the down signal dn, and the gate of the PMOS transistor PTC2 is connected to the supply line of the wide signal wd. The gate of the NMOS transistor NTC2 is connected to the supply line of the inverted signal xwd of the wide signal.

  As shown in FIG. 6D, the D-SW is configured by connecting in parallel PMOS transistors PTD1 and PTD2 connected in series, and NMOS transistors NTD1 and NTD2 connected in series. The gate of the PMOS transistor PTD1 is connected to the supply line of the down signal dn, the gate of the NMOS transistor NTD1 is connected to the supply line of the inverted signal xdn of the down signal, and the gate of the PMOS transistor PTD2 is connected to the supply line of the wide signal wd. The gate of the NMOS transistor NTD2 is connected to the supply line of the inverted signal xwd of the wide signal.

  As shown in FIG. 6E, the E-SW is configured by connecting PMOS transistors PTE1 and PTE2 connected in series and NMOS transistors NTE1 and NTE2 connected in series in parallel. The gate of the PMOS transistor PTE1 is connected to the supply line of the inverted signal xdn of the down signal, the gate of the NMOS transistor NTE1 is connected to the supply line of the down signal dn, and the gate of the PMOS transistor PTE2 is connected to the inverted signal xwd of the wide signal. Connected to the supply line, the gate of the NMOS transistor NTE2 is connected to the supply line of the wide signal wd.

  As shown in FIG. 6F, the F-SW is configured by connecting PMOS transistors PTF1 and PTF2 connected in series and NMOS transistors NTF1 and NTF2 connected in series in parallel. The gate of the PMOS transistor PTF1 is connected to the supply line of the down signal dn, the gate of the NMOS transistor NTF1 is connected to the supply line of the inverted signal xdn of the down signal, and the gate of the PMOS transistor PTF2 is connected to the inverted signal xwd of the wide signal. Connected to the supply line, the gate of the NMOS transistor NTF2 is connected to the supply line of the wide signal wd.

  As shown in FIG. 6G, the G-SW is configured by connecting the sources and drains of the PMOS transistor PTG1 and the NMOS transistor NTG1. The gate of the PMOS transistor PTG1 is connected to the supply line of the inverted signal xwd of the wide signal, and the gate of the NMOS transistor NTH1 is connected to the supply line of the wide signal wd.

  As shown in FIG. 6H, the H-SW is configured by connecting the sources and drains of the PMOS transistor PTH1 and the NMOS transistor NTH1. The gate of the PMOS transistor PTH1 is connected to the supply line of the wide signal wd, and the gate of the NMOS transistor NTH1 is connected to the supply line of the inverted signal xwd of the wide signal.

  FIG. 7 is a diagram showing the four display modes, the setting levels of the wide signal and the down signal, and the ON (OFF) and OFF (OFF) states of the A-SW to H-SW.

In the normal display mode with the aspect ratio of 4: 3 and the forward transfer mode, the wide signal wd is supplied at the low level, the inverted signal xdn is supplied at the high level, the down signal dn is supplied at the high level, and the inverted signal xdn is supplied at the low level. The
As a result, A-SW is on, B-SW is off, C-SW is on, D-SW is off, E-SW is off, F-SW is off, and G-SW is off The state, H-SW, is kept on.

In normal display mode with aspect ratio 4: 3 and upside down transfer mode, wide signal wd is supplied at low level, inverted signal xdn is supplied at high level, down signal dn is supplied at low level, and inverted signal xdn is supplied at high level. Is done.
As a result, A-SW is off, B-SW is on, C-SW is off, D-SW is on, E-SW is off, F-SW is off, G-SW is off The state, H-SW, is kept on.

In the case of the wide display mode with the aspect ratio of 16: 9 and the forward transfer mode, the wide signal wd is supplied at the high level, the inverted signal xdn is supplied at the low level, the down signal dn is supplied at the high level, and the inverted signal xdn is supplied at the low level. The
As a result, A-SW is on, B-SW is off, C-SW is off, D-SW is off, E-SW is on, F-SW is off, G-SW is on The state, H-SW, is kept off.

In a wide display mode with an aspect ratio of 16: 9 and an upside down transfer mode, the wide signal wd is supplied at a high level, the inverted signal xdn is set at a low level, the down signal dn is supplied at a low level, and the inverted signal xdn is supplied at a high level. Is done.
As a result, A-SW is off, B-SW is on, C-SW is off, D-SW is off, E-SW is off, F-SW is on, G-SW is on The state, H-SW, is kept off.

As shown in FIG. 5, the empty transfer circuit 103 includes empty transfer shift registers W1 to W10, three A-SWs, three B-SWs, one G-SW, and one H-SW. Yes.
The empty transfer shift registers W1 to W10 are connected in series to the supply line of the vertical start pulse VST, and one B-SW is arranged between the output side of the shift register W1 and the input side of the shift register W2. ing. One A-SW is arranged between the supply line of the inverted signal pulse XVST of the vertical start pulse VST and the input side of the shift register W2.
Further, G-SW and HH-SW are connected in parallel to the output terminal of the output transfer line TML3.
One A-SW is arranged between the output side of the shift register W10 and the G-SW, and one B-SW is arranged between the output side of the shift register W9 and the G-SW.
One B-SW is arranged between the H-SW and the supply line of the vertical start pulse VST, and one A- is provided between the H-SW and the supply line of the inverted signal pulse XVST of the vertical start pulse VST. SW is arranged.

  As shown in FIG. 5, the upper down and wide switch group 1022, the down switch group 1023, and the lower down and wide switch group 1024 are basically the first for transferring the vertical start pulse VST or XVST. It has a transfer line TML1 and a second transfer line TML2.

A-SW and B-SW are arranged in order from the transfer start side (upper side in the figure) of the vertical start pulse VST on the first transfer line TML1 in the down and wide switch group 1022 on the upper side. Instead of A-SW, C-SW is arranged at the connection part of the fourth transfer line TML4 (input part of the shift register VSR28), and B-SW is arranged at the boundary with the down switch group 1023 at the next stage. Has been.
A B-SW is arranged at the connection between the first transfer line TML1 and the ninth transfer line TML9, and an E-SW is arranged on the fourth transfer line TML4.
The input / output terminals of the A-SW, B-SW, and C-SW are connected to one input of shift registers VSRDU1, VSRDU2, and VSR1 to VSR28 that are arranged correspondingly.

B-SW and A-SW are arranged in order from the transfer start side (upper side in the figure) of the vertical start pulse VST on the second transfer line TML2 in the down and wide switch group 1022 on the upper side. Yes.
A C-SW is arranged at the connection between the second transfer line TML2 and the third transfer line TML3, and an E-SW is connected at the connection between the second transfer line TML2 and the seventh transfer line TML7. Has been placed.
The input / output terminals of the A-SW, B-SW, and C-SW are connected to the other inputs of the shift registers VSRDU1, VSRDU2, and VSR1 to VSR28 that are arranged correspondingly.

In the first transfer line TML1 in the down switch group 1023, A-SW and B-SW are basically arranged in order from the transfer start side (upper side in the figure) of the vertical start pulse VST, and the second transfer line. In TML2, B-SW and A-SW are basically arranged in order from the transfer end side (upper side in the figure) of the vertical start pulse VST.
The input / output terminals of the A-SW and B-SW of the first transfer line TML1 are connected to one input of shift registers VSR29 to VSR192 arranged correspondingly.
The input / output terminals of the A-SW and B-SW of the second transfer line TML2 are connected to the other inputs of the shift registers VSR192 to VSR29 arranged correspondingly.

  The down switch group 1023 having such a configuration performs the positive transfer or the vertical inversion transfer of the vertical start pulse VST or XVST in accordance with the supply level of the down signal dn regardless of the supply level of the wide signal wd as the first transfer. While the A-SW or B-SW arranged on the line TML1 and the second transfer line TML2 are alternately transferred, the corresponding shift registers VSR29 to VSR192 or VSR192 to VSR29 are sequentially shifted in.

The first transfer line TML1 in the lower down and wide switch group 1024 basically has A-SW and B-SW arranged in order from the boundary side with the down switch group 1023, and the sixth transfer line A D-SW is arranged in place of B-SW at the connection portion of TML4 (input portion of the dummy shift register VSRDBU1). In addition, an F-SW is disposed at a connection portion between the first transfer line TML1 and the eighth transfer line TML8.
The input / output terminals of the A-SW, B-SW, and D-SW are connected to one input of shift registers VSRDB1, VSRDB2, and VSR193 to VSR220 that are arranged correspondingly.

On the second transfer line TML2 in the down and wide switch group 1024 on the lower side, B-SW and A-SW are basically arranged in order from the boundary side with the down switch group 1023. However, a D-SW is arranged instead of the B-SW at the boundary with the down switch group 1023.
And F-SW is arrange | positioned at the connection part of 2nd transfer line TML2 and 5th transfer line TML.
The input / output terminals of the A-SW, B-SW, and D-SW are connected to the other inputs of the shift registers VSRDB1, VSRDB2, and VSR193 to VSR220 that are arranged correspondingly.

The gate buffer group 1025 includes a gate buffer GB to which the scanning lines 105-1 to 105-220 are connected, and the vertical start pulse VST or the first transfer line TML1 or TML2 transferred from the enable signal en or the first transfer line TML1 or TML2. In response to XVST and the output signal of the corresponding shift register VSR, a scan pulse SP is output and applied to scan lines 105-1 to 105-220 connected for a predetermined period.
In this case, when the scanning pulse SP1 is applied from the gate buffer group 1025 of the vertical driving circuit 102 to the first scanning line, the pixels in each column of the first row are selected, and the scanning of the second row is performed. When the scanning pulse SP2 is applied to the line, the pixel in each column of the second row is selected. Similarly, scanning pulses SP3,..., SPm are sequentially applied to the third scanning line,..., The mth scanning line.

The horizontal driving circuit 104 receives an input video signal Vsig based on a horizontal start pulse HST for instructing the start of horizontal scanning and a horizontal clock HCK (or vertical clocks HCK and HCKX having opposite phases to each other) as a reference for horizontal scanning. Sampling is sequentially performed every 1H (H is a horizontal scanning period), and writing processing is performed on each pixel circuit selected in units of rows by the vertical driving circuit 102 via the signal lines 106-1 to 106-n.
Further, the horizontal driving circuit 104 uses a video signal Vsig as a black signal during wide display, and is a pixel circuit arranged in a matrix on the upper and lower sides of the effective pixel unit 101 that is selectively driven by the vertical driving circuit 102. Are written sequentially.

  As shown in FIG. 1, the horizontal drive circuit 104 uses a horizontal shift register group (HS / R) 1041, a precharge switch group (PSW) 1042, a horizontal sampling switch group (HSW) 1043, and a horizontal start pulse HST as effective pixels. A switch group (RGT / SW) 1044 for switching between propagating from the left side or right side of the unit 101 is provided.

  The horizontal shift register group (HS / R) 1041 has a plurality of shift registers corresponding to the pixel columns of the effective pixel unit 101, and when a horizontal start pulse HST is given by a clock generator (not shown), the horizontal clock HCK (or each other) The shift operation is performed in synchronization with the opposite-phase horizontal clocks HCK and XHCK). Thus, sample pulses synchronized with the horizontal clock are sequentially output from each shift register.

The precharge switch group 1042 includes a plurality of switches that operatively connect the supply line of the precharge signal Psig and the signal lines arranged corresponding to the pixel columns of the pixel portion 101.
When the precharge switch group 1042 receives the pulse signal PCG in an active state, the precharge switch group 1042 is turned on at the same time to write the precharge signal Psig into the signal line.

The horizontal sampling switch group (HSW) 1043 includes a plurality of switches that operatively connect the video signal Vsig and signal lines arranged corresponding to the pixel columns of the pixel unit 101.
The horizontal sampling switch group (HSW) 1043 receives the sample pulses sequentially supplied by the horizontal shift register group (HS / R) 1041 and sequentially turns on the switches to sequentially sample the video signal Vsig. The signal lines 106-1 to 106-n are supplied. At the time of wide display, the video signal Vsig during the vertical blanking period is used as a black signal, which is similarly sampled and supplied to the signal lines 106-1 to 106-n.

  Next, operations in the wide display mode and the normal display mode with the above configuration will be described with reference to the drawings.

First, the operation in the wide display mode and in the normal transfer mode will be described with reference to FIG. 8 and FIG.
FIG. 8 shows the operating state of the empty transfer circuit 103, the upper wide and down switch group 1022, the down switch group 1023, and the lower wide and down switch group 1024 in the wide display mode and in the normal transfer mode. FIG.
FIG. 9 is a diagram showing black mask write timing for the first and second mask regions in the wide display mode.

In the wide display mode and the normal transfer mode, the wide signal wd is supplied at the high level, the inverted signal xwd is supplied at the low level, the down signal dn is supplied at the high level, and the inverted signal xdn is supplied at the low level.
As a result, A-SW is on, B-SW is off, C-SW is off, D-SW is off, E-SW is on, F-SW is off, G-SW is on The state, H-SW, is kept off.
As a result, first, in the empty transfer circuit 103, the vertical transfer start pulse VST is sequentially shifted through the empty transfer shift registers W1 to W9 and transferred empty for 9H period, and then the third transfer is performed through B-SW and G-SW. Transferred to line TML3.
The vertical start pulse VST propagating through the third transfer line TML3 is branched to the fourth to sixth transfer lines TML4 to TML6. In the wide display mode and the normal transfer mode, the third to sixth Among the C-SW, D-SW, E-SW, and F-SW arranged on the transfer lines TML4 to TML6, only the E-SW arranged on the fourth transfer line TML4 is in the ON state. The vertical start pulse VST propagates through the third transfer line TML3 and the fourth transfer line TML4 to the upper wide and the first transfer line TML1 at the boundary between the down switch group 1022 and the down switch group 1023. Propagated.
Then, it is input to the shift register VSR28, transferred to the second transfer line TML2, and then propagated to the second transfer line TML2 of the down switch group 1023.

  In the shift registers VSR29 to VSR192 corresponding to the down switch group 1023, a vertical start pulse VST and a vertical clock VCK (or vertical clocks VCK and VCKX having opposite phases to each other) as a reference for vertical scanning are supplied. In synchronization with the vertical clock VCK, VST is shifted by a half clock of the vertical clock VCK and output to the corresponding gate buffer of the gate buffer group 1025.

  In the gate buffer group 1025, the vertical start pulse VST to which the enable signal en and the first or second transfer lines TML1 and TML2 are transferred to each gate buffer GB to which each scan line 105-29 to 105-192 is connected. And the output signal of the corresponding shift register VSR is supplied and input to the AND circuit. Further, the output of the AND circuit is sequentially applied as scan pulses SP to the scan lines 105-29 to 105-192 connected for a predetermined period via the buffer.

At this time, in the horizontal drive circuit 104, when a horizontal start pulse HST is given to the horizontal shift register group 1041, a shift operation is performed in synchronization with the horizontal clock HCK (or horizontal clocks HCK and XHCK having opposite phases to each other). Each shift register sequentially outputs sample pulses synchronized with the horizontal clock.
The horizontal sampling switch group 1043 receives the sample pulses sequentially supplied from the horizontal shift register group 1041 and receives the signal lines 106 arranged in correspondence with the supply line of the video signal Vsig and the pixel column of the pixel unit 101. A plurality of switches that operatively connect -1 to 106-n are sequentially turned on, and the video signal Vsig is sequentially sampled and supplied to the signal lines 106-1 to 106-n.
Then, video signals are sequentially written to n pixel circuits connected to the scanning lines 105-29 to 105-192.

As described above, in the down switch group 1023, the vertical start pulse VST is positively transferred while alternately transferring the A-SWs arranged on the first transfer line TML1 and the second transfer line TML2, and the corresponding shift register. After being shifted in order to VSR29 to VSR192 and inputted to the shift register VSR192 of the 192nd face, the vertical start pulse VST is transferred to the second wide transfer line TML2 of the lower side and down switch group 1024 of the next stage. Is done.
Then, the vertical start pulse VST transferred to the second transfer line TML2 is branched to the seventh transfer line TML7, and the second transfer of the upper side down and wide switch group 1022 via the E-SW. Transferred to line TML2.
Then, it is input to the dummy shift register VSRDU1, transferred to the first transfer line TML1, and then propagated to the first transfer line TML1 of the down and wide switch group 1022 on the upper side.

  As a result, as shown in FIG. 9, the following operations are performed simultaneously in parallel in the down and wide switch group 1022 on the upper side and the down and wide switch group 1024 on the lower side.

In shift registers VST1 to VST27 corresponding to the down and wide switch group 1022 on the upper side, a vertical start pulse VST and a vertical clock VCK (or vertical clocks VCK and VCKX having opposite phases to each other) serving as a reference for vertical scanning are supplied. The vertical start pulse VST is shifted by a half clock of the vertical clock VCK in synchronization with the vertical clock VCK and output to the corresponding gate buffer of the gate buffer group 1025.
In the gate buffer group 1025, the vertical start pulse VST, to which the enable signal en and the first or second transfer lines TML1, TML2 are transferred to the gate buffers GB to which the scan lines 105-1 to 105-27 are connected, And the output signal of the corresponding shift register VSR is supplied and input to the AND circuit. Further, the output of the AND circuit is applied as a scanning pulse SP to the scanning lines 105-1 to 105-27 connected for a predetermined period through the buffer.
It is to be noted that transfer to the first and second transfer lines TML1 and TML2 that is input to the first to 27th shift registers VSR27 and is transferred to the next-stage down switch group 1023 is in an OFF state. It is blocked by C-SW and B-SW as circuits.

In parallel with this, in the shift registers VST193 to VST220 corresponding to the down side and wide switch group 1024 on the lower side, the vertical start pulse VST, the vertical clock VCK as a reference for vertical scanning (or the vertical clocks VCK, VCKX) is supplied, and the vertical start pulse VST is shifted by a half clock of the vertical clock VCK in synchronization with the vertical clock VCK and output to the corresponding gate buffer of the gate buffer group 1025.
In the gate buffer group 1025, the vertical start pulse VST for transferring the enable signal en and the first or second transfer lines TML1 and TML2 to the gate buffers GB to which the scan lines 105-193 to 105-220 are connected. And the output signal of the corresponding shift register VSR is supplied and input to the AND circuit. Further, the output of the AND circuit is applied as a scanning pulse SP to the scanning lines 105-193 to 105-220 connected for a predetermined period via the buffer.

  At this time, the horizontal drive circuit 104 uses the video signal Vsig as a black signal for wide display, and the signal lines 106-1 to 106-n arranged corresponding to the Vsig supply line and the pixel column of the pixel unit 101. A plurality of switches that operatively connect each of them are turned on in turn. As a result, the black signal Vsig is written into the plurality of pixel circuits in the first mask region 1012 on the upper side and the second mask region 1023 on the lower side of the effective pixel unit 101 that is selectively driven by the vertical drive circuit 102. It is.

  Then, video signals are sequentially written to n pixel circuits connected to the scanning lines 105-29 to 105-192, and a video display with an aspect ratio of 16: 9 is displayed at the center of the effective pixel portion 101. Is done.

Next, the operation in the wide display mode and the upside down transfer mode will be described with reference to FIG.
FIG. 10 shows operating states of the empty transfer circuit 103, the upper wide and down switch group 1022, the down switch group 1023, and the lower wide and down switch group 1024 in the wide display mode and the upside down transfer mode. FIG.

In the wide display mode and the upside down transfer mode, the wide signal wd is supplied at the high level, the inverted signal xwd is supplied at the low level, the down signal dn is supplied at the low level, and the inverted signal xdn is supplied at the high level.
As a result, A-SW is off, B-SW is on, C-SW is off, D-SW is off, E-SW is off, F-SW is on, G-SW is on The state, H-SW, is kept off.
As a result, first, in the empty transfer circuit 103, the inverted vertical start pulse XVST is sequentially shifted through the empty transfer shift registers W2 to W10 and transferred empty for the 9H period, and then the third through the A-SW and G-SW. Transferred to the transfer line TML3.
The vertical start pulse VST propagating through the third transfer line TML3 is branched to the fourth to sixth transfer lines TML4 to TML6. In the wide display mode and the upside down transfer mode, the third to third Among the C-SW, D-SW, E-SW, and F-SW arranged on the six transfer lines TML4 to TML6, only the F-SW arranged on the fifth transfer line TML5 is in the ON state. The vertical start pulse VST propagates through the third transfer line TML3 and the fifth transfer line TML5, and the second transfer line TML2 at the boundary between the lower wide and the down switch group 1024 and the down switch group 1023. Is propagated to.
Then, it is input to the shift register VSR 193, transferred to the first transfer line TML 1, and then propagated to the first transfer line TML 1 of the down switch group 1023.

  In the shift registers VSR192 to VSR29 corresponding to the down switch group 1023, the vertical start pulse VST and the vertical clock VCK (or vertical clocks VCK and VCKX having opposite phases to each other) are supplied, and the vertical start pulse is supplied. In synchronization with the vertical clock VCK, VST is shifted by a half clock of the vertical clock VCK and output to the corresponding gate buffer of the gate buffer group 1025.

  In the gate buffer group 1025, the vertical start pulse VST for transferring the enable signal en and the first or second transfer lines TML1 and TML2 to the gate buffers GB to which the scan lines 105-192 to 105-29 are connected. And the output signal of the corresponding shift register VSR is supplied and input to the AND circuit. Further, the output of the AND circuit is sequentially applied as scan pulses SP to the scan lines 105-192 to 105-29 connected for a predetermined period via the buffer.

At this time, in the horizontal drive circuit 104, when a horizontal start pulse HST is given to the horizontal shift register group 1041, a shift operation is performed in synchronization with the horizontal clock HCK (or horizontal clocks HCK and XHCK having opposite phases to each other). Each shift register sequentially outputs sample pulses synchronized with the horizontal clock.
The horizontal sampling switch group 1043 receives the sample pulses sequentially supplied from the horizontal shift register group 1041 and receives the signal lines 106 arranged in correspondence with the supply line of the video signal Vsig and the pixel column of the pixel unit 101. A plurality of switches that operatively connect -1 to 106-n are sequentially turned on, and the video signal Vsig is sequentially sampled and supplied to the signal lines 106-1 to 106-n.
Then, video signals are sequentially written into n pixel circuits connected to the scanning lines 105-192 to 105-29.

As described above, in the down switch group 1023, the vertical start pulse VST is transferred upside down while alternately transferring the B-SWs arranged on the first transfer line TML1 and the second transfer line TML2, and the corresponding shift is performed. After being sequentially shifted into the registers VSR192 to VSR29 and input to the 29th shift register VSR29, the vertical start pulse VST is applied to the first transfer line TML1 of the wide and down switch group 1022 on the upper side of the next stage. Transferred.
The vertical start pulse VST transferred to the first transfer line TML1 is branched to the eighth transfer line TML8, and the second transfer of the lower down and wide switch group 1024 is performed via the F-SW. Transferred to line TML1.
Then, it is input to the dummy shift register VSRDB1, transferred to the second transfer line TML2, and then propagated to the lower transfer and the second transfer line TML2 of the wide switch group 1024.

  As a result, the following operations are performed simultaneously in parallel in the down and wide switch group 1022 on the upper side and the down and wide switch group 1024 on the lower side.

In the shift registers VST28 to VST1 corresponding to the down and wide switch group 1022 on the upper side, a vertical start pulse VST and a vertical clock VCK serving as a reference for vertical scanning (or vertical clocks VCK and VCKX having opposite phases to each other) are supplied. The vertical start pulse VST is shifted by a half clock of the vertical clock VCK in synchronization with the vertical clock VCK and output to the corresponding gate buffer of the gate buffer group 1025.
In the gate buffer group 1025, the vertical start pulse VST, to which the enable signal en and the first or second transfer lines TML1 and TML2 are transferred to the gate buffers GB to which the scanning lines 105-28 to 105-1 are connected, And the output signal of the corresponding shift register VSR is supplied and input to the AND circuit. Further, the output of the AND circuit is applied as a scanning pulse SP to the scanning lines 105-28 to 105-1 connected for a predetermined period through the buffer.

In parallel with this, in the shift registers VST220 to VST194 corresponding to the down side and wide switch group 1024 on the lower side, the vertical start pulse VST, the vertical clock VCK as a reference for vertical scanning (or the vertical clocks VCK, VCKX) is supplied, and the vertical start pulse VST is shifted by a half clock of the vertical clock VCK in synchronization with the vertical clock VCK and output to the corresponding gate buffer of the gate buffer group 1025.
In the gate buffer group 1025, the vertical start pulse VST to which the enable signal en and the first or second transfer lines TML1 and TML2 are transferred to each gate buffer GB to which each scan line 105-220 to 105-194 is connected. And the output signal of the corresponding shift register VSR is supplied and input to the AND circuit. Further, the output of the AND circuit is applied as a scan pulse SP through a buffer to scan lines 105-220 to 105-194 connected for a predetermined period.
It should be noted that the transfer of the first and second transfer lines TML1 and TML2 that are input to the 220th to 194th shift registers VSR194 and transferred to the down switch group 1023 in the next stage is in the off state. It is blocked by D-SW and A-SW as circuits.

  At this time, the horizontal drive circuit 104 uses the video signal Vsig as a black signal for wide display, and the signal lines 106-1 to 106-n arranged corresponding to the Vsig supply line and the pixel column of the pixel unit 101. A plurality of switches that operatively connect each of them are turned on in turn. As a result, the black signal Vsig is written into the plurality of pixel circuits in the first mask region 1012 on the upper side and the second mask region 1023 on the lower side of the effective pixel unit 101 that is selectively driven by the vertical drive circuit 102. It is.

  Then, video signals are sequentially written to n pixel circuits connected to the scanning lines 105-29 to 105-192, and a video display with an aspect ratio of 16: 9 is displayed at the center of the effective pixel portion 101. Is done.

Next, the operation in the normal display mode and the normal transfer mode will be described with reference to FIG.
FIG. 11 shows operating states of the empty transfer circuit 103, the upper wide and down switch group 1022, the down switch group 1023, and the lower wide and down switch group 1024 in the normal display mode and in the normal transfer mode. FIG.

In the normal display mode and the normal transfer mode, the wide signal wd is supplied at the low level, the inverted signal xwd is supplied at the high level, the down signal dn is supplied at the high level, and the inverted signal xdn is supplied at the low level.
As a result, A-SW is on, B-SW is off, C-SW is on, D-SW is off, E-SW is off, F-SW is off, and G-SW is off The state, H-SW, is kept on.
Thereby, first, in the empty transfer circuit 103, the vertical start pulse VST bypasses the empty transfer shift registers W1 to W9, and the empty transfer for 9H period is not performed, and the third through the B-SW and H-SW. Transferred to the transfer line TML3.
The vertical start pulse VST propagating through the third transfer line TML3 is branched to the fourth to sixth transfer lines TML4 to TML6. In the wide display mode and the normal transfer mode, the third to sixth Of the C-SW, D-SW, E-SW, and F-SW arranged on the transfer lines TML4 to TML6, only the C-SW arranged on the third transfer line TML3 is in the on state. The vertical start pulse VST propagates through the third transfer line TML3 and is propagated to the second wide transfer line TML2 of the upper wide and down switch group 1022.
Then, after being input to the dummy shift register VSRDU1, transferred to the first transfer line TML1, and further input to the dummy shift register VSRDU2 and transferred to the second transfer line TML2, the upper side down and wide switch group 1022 is propagated to the second transfer line TML2.
That is, the vertical start pulse VST is input to the upper side wide and down switch group 1022 from the dummy part side (from the first stage part).

  In such a state, when the down and wide switch group 1022 on the upper side receives the wide signal wd at a low level and receives the down signal dn at a high level, it functions as a down switch, and the vertical start pulse VST is an effective pixel. The data are sequentially input to the shift registers VSR1 to VSR28 arranged in order from the upper side to the lower side of the unit 101, similarly from the upper side to the lower side. After being input to the 28th shift register VSR28, the vertical start pulse VST is transferred to the down switch group 1023 of the next stage.

  In the shift registers VST1 to VST28 corresponding to the down and wide switch group 1022 on the upper side, a vertical start pulse VST and a vertical clock VCK (or vertical clocks VCK and VCKX having opposite phases to each other) serving as a reference for vertical scanning are supplied. The vertical start pulse VST is shifted by a half clock of the vertical clock VCK in synchronization with the vertical clock VCK and output to the corresponding gate buffer of the gate buffer group 1025.

  In the gate buffer group 1025, the vertical start pulse VST, to which the enable signal en and the first or second transfer lines TML1, TML2 are transferred to the gate buffers GB to which the scan lines 104-1 to 104-28 are connected, And the output signal of the corresponding shift register VSR is supplied and input to the AND circuit. Further, the output of the AND circuit is applied as a scanning pulse SP to the scanning lines 105-1 to 105-28 connected for a predetermined period through the buffer.

  In the vertical drive circuit 102, in the down switch group 1023 to which the vertical start pulse VST is transferred from the wide and down switch group 1022, the vertical start pulse is determined according to the high level down signal dn regardless of the supply level of the wide signal wd. The VST is forward-transferred while alternately transferring the A-SWs arranged on the first transfer line TML1 and the second transfer line TML2, and is sequentially shifted into the corresponding shift registers VSR29 to VSR192. After being input to the shift register VSR 192, the vertical start pulse VST is transferred to the wide and down switch group 1024 on the lower side of the next stage.

  In the shift registers VST29 to VST192 corresponding to the down switch group 1023, the vertical start pulse VST and the vertical clock VCK (or vertical clocks VCK and VCKX having opposite phases to each other) as a reference for the vertical scanning are supplied to the vertical start pulse VST. In synchronization with the vertical clock VCK, the half clock of the vertical clock VCK is shifted and output to the corresponding gate buffer of the gate buffer group 1025.

  In the gate buffer group 1025, the vertical start pulse VST to which the enable signal en and the first or second transfer lines TML1 and TML2 are transferred to each gate buffer GB to which each scan line 105-29 to 105-192 is connected. And the output signal of the corresponding shift register VSR is supplied and input to the three-input AND circuit. Further, the output of the AND circuit is input to the buffer B, and the output is sequentially applied to the scan lines 105-29 to 105-192 connected for a predetermined period as the scan pulse SP.

  In the wide and down switch group 1024 to which the vertical start pulse VST is transferred from the down switch group 1023, when the wide signal wd is received at a low level and the down signal dn is received at a high level, the vertical start pulse functions as a down switch. VST is sequentially input to the shift registers VSR193 to VSR220 arranged in order from the upper side to the lower side of the effective pixel portion 101 in the same order from the upper side to the lower side.

  In the shift registers VSR193 to VSR220 corresponding to the down and wide switch group 1024 on the lower side, a vertical start pulse VST and a vertical clock VCK (or vertical clocks VCK and VCKX having opposite phases to each other) serving as a reference for vertical scanning are supplied. The vertical start pulse VST is shifted by a half clock of the vertical clock VCK in synchronization with the vertical clock VCK and output to the corresponding gate buffer of the gate buffer group 1025.

  In the gate buffer group 1025, the vertical start pulse VST for transferring the enable signal en and the first or second transfer lines TML1 and TML2 to the gate buffers GB to which the scan lines 105-193 to 105-220 are connected. And the output signal of the corresponding shift register VSR is supplied and input to the AND circuit. Further, the output of the AND circuit is applied as a scanning pulse SP to the scanning lines 105-193 to 105-220 connected for a predetermined period via the buffer.

At this time, in the horizontal drive circuit 104, when a horizontal start pulse HST is given to the horizontal shift register group 1041, a shift operation is performed in synchronization with the horizontal clock HCK (or horizontal clocks HCK and XHCK having opposite phases to each other). Each shift register sequentially outputs sample pulses synchronized with the horizontal clock.
The horizontal sampling switch group 1043 receives the sample pulses sequentially supplied from the horizontal shift register group 1041 and receives the signal lines 106 arranged in correspondence with the supply line of the video signal Vsig and the pixel column of the pixel unit 101. A plurality of switches that operatively connect -1 to 106-n are sequentially turned on, and the video signal Vsig is sequentially sampled and supplied to the signal lines 106-1 to 106-n.
Then, video signals are sequentially written to n pixel circuits connected to the scanning lines 105-1 to 105-220, and a video display with an aspect ratio of 4: 3 is displayed on the entire effective pixel portion 101. Done.

  The above operation is repeated to perform normal display.

Next, the operation in the normal display mode and the upside down transfer mode will be described.
FIG. 12 shows the operating state of the idle transfer circuit 103, the upper wide and down switch group 1022, the down switch group 1023, and the lower wide and down switch group 1024 in the normal display mode and the upside down transfer mode. FIG.

In the normal display mode and the upside down transfer mode, the wide signal wd is supplied at the low level, the inverted signal xwd is supplied at the high level, the down signal dn is supplied at the low level, and the inverted signal xdn is supplied at the high level.
As a result, A-SW is on, B-SW is off, C-SW is off, D-SW is on, E-SW is off, F-SW is off, G-SW is off The state, H-SW, is kept on.
Thereby, first, in the empty transfer circuit 103, the inverted vertical start pulse XVST bypasses the empty transfer shift registers W2 to W10, and the empty transfer for 9H period is not performed, but the third through the A-SW and H-SW. Are transferred to the transfer line TML3.
The vertical start pulse VST propagating through the third transfer line TML3 is branched to the fourth to sixth transfer lines TML4 to TML6. In the wide display mode and the normal transfer mode, the third to sixth Among the C-SW, D-SW, E-SW, and F-SW arranged on the transfer lines TML4 to TML6, only the D-SW arranged on the third transfer line TML3 is in the ON state. The inverted vertical start pulse XVST propagates through the third transfer line TML3 and the sixth transfer line TML6, and is propagated to the second wide transfer line TML2 of the lower side wide and down switch group 1024.
Then, after being input to the dummy shift register VSRDB1, transferred to the first transfer line TML1, and further input to the dummy shift register VSRDB2 and transferred to the second transfer line TML2, the lower side down and wide switch group It is propagated to the 1024 second transfer line TML2.
That is, the inverted vertical start pulse VST is input from the dummy part side (from the first stage part) to the lower side wide and down switch group 1024.

  In such a state, when the down and wide switch group 1024 on the lower side receives the wide signal wd at a low level and receives the down signal dn at a low level, it functions as a down switch, and the vertical start pulse VST is an effective pixel. The data are sequentially input to the shift registers VSR220 to VSR193 arranged in order from the lower side to the upper side of the unit 101, similarly from the lower side to the upper side. After being input to the 193rd shift register VSR 193, the vertical start pulse VST is transferred to the next down switch group 1023.

  In the shift registers VST220 to VST193 corresponding to the down and wide switch group 1024 on the upper side, a vertical start pulse VST and a vertical clock VCK (or vertical clocks VCK and VCKX having opposite phases to each other) serving as a reference for vertical scanning are supplied. The vertical start pulse VST is shifted by a half clock of the vertical clock VCK in synchronization with the vertical clock VCK and output to the corresponding gate buffer of the gate buffer group 1025.

  In the gate buffer group 1025, the vertical start pulse VST, to which the enable signal en and the first or second transfer lines TML1 and TML2 are transferred to each gate buffer GB to which each scan line 105-220 to 105-193 is connected, And the output signal of the corresponding shift register VSR is supplied and input to the AND circuit. Further, the output of the AND circuit is applied as a scanning pulse SP to the scanning lines 105-220 to 105-193 connected for a predetermined period via the buffer.

  In the vertical drive circuit 102, in the down switch group 1023 to which the vertical start pulse VST is transferred from the wide and down switch group 1024, the vertical start pulse depends on the low level down signal dn regardless of the supply level of the wide signal wd. The VST is forward-transferred while alternately transferring the B-SWs arranged on the first transfer line TML1 and the second transfer line TML2, and sequentially shifted into the corresponding shift registers VSR192 to VSR29. After being input to the shift register VSR29, the vertical start pulse VST is transferred to the wide and down switch group 1022 on the upper side of the next stage.

  In the shift registers VSR192 to VSR29 corresponding to the down switch group 1023, the vertical start pulse VST and the vertical clock VCK (or vertical clocks VCK and VCKX having opposite phases to each other) as a reference for the vertical scanning are supplied to the vertical start pulse VST. In synchronization with the vertical clock VCK, the half clock of the vertical clock VCK is shifted and output to the corresponding gate buffer of the gate buffer group 1025.

  In the gate buffer group 1025, the vertical start pulse VST for transferring the enable signal en and the first or second transfer lines TML1 and TML2 to the gate buffers GB to which the scan lines 105-192 to 105-29 are connected. And the output signal of the corresponding shift register VSR is supplied and input to the AND circuit. Further, the output of the AND circuit is sequentially applied as scan pulses SP to the scan lines 105-192 to 105-29 connected for a predetermined period via the buffer.

  In the wide and down switch group 1022 to which the vertical start pulse VST is transferred from the down switch group 1023, when the wide signal wd is received at the low level and the down signal dn is received at the high level, the vertical start pulse functions as a down switch. VST is sequentially input to the shift registers VSR28 to VSR1 arranged in order from the lower side to the upper side of the effective pixel unit 101, similarly from the lower side to the upper side.

  In the shift registers VST28 to VST1 corresponding to the down and wide switch group 1022 on the upper side, a vertical start pulse VST and a vertical clock VCK serving as a reference for vertical scanning (or vertical clocks VCK and VCKX having opposite phases to each other) are supplied. The vertical start pulse VST is shifted by a half clock of the vertical clock VCK in synchronization with the vertical clock VCK and output to the corresponding gate buffer of the gate buffer group 1025.

  In the gate buffer group 1025, the vertical start pulse VST, to which the enable signal en and the first or second transfer lines TML1 and TML2 are transferred to the gate buffers GB to which the scanning lines 105-28 to 105-1 are connected, And the output signal of the corresponding shift register VSR is supplied and input to the AND circuit. Further, the output of the AND circuit is applied as a scanning pulse SP to the scanning lines 105-28 to 105-1 connected for a predetermined period through the buffer.

At this time, in the horizontal drive circuit 104, when a horizontal start pulse HST is given to the horizontal shift register group 1041, a shift operation is performed in synchronization with the horizontal clock HCK (or horizontal clocks HCK and XHCK having opposite phases to each other). Each shift register sequentially outputs sample pulses synchronized with the horizontal clock.
The horizontal sampling switch group 1043 receives the sample pulses sequentially supplied from the horizontal shift register group 1041 and receives the signal lines 106 arranged in correspondence with the supply line of the video signal Vsig and the pixel column of the pixel unit 101. A plurality of switches that operatively connect -1 to 106-n are sequentially turned on, and the video signal Vsig is sequentially sampled and supplied to the signal lines 106-1 to 106-n.
Then, video signals are sequentially written to n pixel circuits connected to the scanning lines 105-220 to 105-1, and a video display with an aspect ratio of 4: 3 is displayed on the entire effective pixel unit 101. Done.

  The above operation is repeated to perform normal display.

As described above, according to this embodiment, the vertical drive circuit 102 scans in the vertical direction (row direction) every field period and is connected to the scanning lines 105-1 to 105-m during normal display. In the wide display, the vertical start pulse VST is idle-transferred by the idle transfer circuit 103 for a predetermined period, and then a plurality of scanning lines wired to the effective pixel unit 101 is selected. And writing a video signal, the vertical start pulse VST is transferred to the transfer lines corresponding to the first mask region 1012 and the second mask region 1013 of the effective pixel portion 101, respectively, and the effective pixel portion 101 The first mask region 1012 and the second mask region 1013 are connected to a plurality (28 each) of scanning lines arranged in the first mask region 1012 and the second mask region 1013. By sequentially shifting in the vertical start pulse VST transferred on the transfer line to the scanning unit and sequentially driving the scanning line, each 28 lines in the first mask region 1012 and the second mask region 1013 are driven. Wide and down switch groups 1022 and 1024 for performing black mask writing for 28 scanning lines simultaneously and in parallel and performing black mask display are provided, and switching between the forward transfer mode and the upside down transfer mode is performed by switching the transfer switch. Therefore, it is possible to simplify the circuit configuration and control without adding a transfer switch, and it is possible to reduce the power consumption without degrading the image quality. There are advantages that can be done.
A smooth wide black mask display can be realized only by using two timings such as displaying the effective area first and then displaying the wide black mask portion.
Further, the writing method of the wide black mask portion and the effective area is the same, and there is no difference in image quality between areas, and smoothness can be realized.
In addition, transfer pulse transfer was realized only by controlling the transfer switch without adding a special circuit.

  Further, in the case of wide display, during normal transfer, transfer of the vertical start pulse VST from the wide and down switch group 1022 to the down switch group 1023 is blocked, and during upside down transfer, from the wide and down switch group 1024 to the down switch Since the switches functioning as transfer blocking circuits for blocking the transfer of the vertical start pulse VST to the group 1023 are arranged on the first and second transfer lines TML1 and TML2, a smooth wide black mask display can be performed without malfunction. This is advantageous in that the screen display of the 16: 9 wide black mask region is smooth and stable, and the product can be improved in quality.

  In the above embodiment, an analog video signal is input to the liquid crystal display device, and after latching the analog video signal, it is applied to a liquid crystal display device equipped with an analog interface driving circuit that writes the analog video signal to each pixel in a dot sequence. As described above, the present invention can be similarly applied to a liquid crystal display device equipped with a drive circuit that inputs a digital video signal and writes the video signal to pixels in a line-sequential manner by a selector method.

In the above embodiment, the case where the present invention is applied to an active matrix liquid crystal display device using a liquid crystal cell as a display element (electro-optical element) of each pixel has been described as an example. It is not limited, but an active matrix display using a dot sequential drive system that employs a clock drive system in a horizontal drive circuit, such as an active matrix EL display device using an electroluminescence (EL) element as a display element of each pixel. Applicable to all devices.
In addition to the well-known 1H inversion driving method and the dot inversion driving method, the dot sequential driving method has the same polarity in the pixel arrangement after the video signal is written, and the left and right pixels adjacent to each other. There is a so-called dot line inversion driving method in which video signals having opposite polarities are simultaneously written in two rows separated by odd numbers between adjacent pixel columns, for example, pixels in two upper and lower rows so that the pixels have opposite polarities.
The active matrix type liquid crystal display device of the dot sequential drive system according to the embodiment described above is a display panel of a direct-view type video display device (liquid crystal monitor, liquid crystal viewfinder) or projection type liquid crystal display device (liquid crystal projector), that is, an LCD ( It can be used as a liquid crystal display panel.

  DESCRIPTION OF SYMBOLS 100 ... Liquid crystal display device 101 ... Effective pixel part, 1011 ... Display area, 1012 ... 1st mask area | region, 1013 ... 2nd mask area | region, 102 ... Vertical drive circuit (VDRV), 1021 ... Vertical shift register group (VS / R), 1022 ... Down and wide switch group on the upper side (DWN + WIDE SW), 1023 ... Down switch group at the center (DWN · SW), 1024 ... Down and wide switch group on the lower side (DWN + WIDE SW), 1025 ... Gate buffer group (GTBUF) 1025, 103 ... Empty transfer circuit (PSDC), 104 ... Horizontal drive circuit (HDRV), 1041 ... Horizontal shift register group (HS / R), 1042 ... Precharge switch group (PSW), 1043 ... Horizontal sampling switch group (HSW), 1044. Switch group (RGT / SW), 105-1 to 105-m ... scanning line, 106-1 to 106-n ... signal line, 107 ... VCOM supply line, PXLC ... pixel circuit, TFT101 ... switching element, LC101 ... liquid crystal Cell, Cs101... Holding capacitor, TML1 to TML9.

Claims (7)

A display device having at least a first display mode and a second display mode having different aspect ratios,
Pixel circuits for writing pixel data through the switching elements are arranged in a matrix,
Two areas are assigned as a first mask area and a second mask area in the first display mode with a display area including a plurality of predetermined lines, and in the first display mode, the first and second mask areas are assigned. Mask pixel data is written in each pixel circuit in the second mask area, and video pixel data is written in each pixel circuit in the display area. In the second display mode, the first and second masks are used. A pixel portion in which video pixel data is written to each pixel circuit in the display area and display area;
A plurality of scan lines arranged to correspond to the row arrangement of the pixel circuits, and for controlling conduction of the switching elements;
A plurality of signal lines arranged to correspond to the column arrangement of the pixel circuits and propagating the pixel data;
A plurality of scanning lines connected to each other, and a vertical driving circuit having a plurality of scanning units for selectively scanning the scanning lines by applying a scanning signal to the connected scanning lines in response to a start pulse;
An empty transfer circuit, and
The vertical drive circuit is
A transfer line for transferring the start pulse in one direction, and a switch circuit;
The switch circuit is
In the first display mode, a plurality of start pulses transferred in the one direction are sequentially propagated to the scanning units connected to the plurality of scanning lines arranged in the display area. The scan lines are sequentially driven, and then the start pulse is transferred to the transfer lines corresponding to the first and second mask regions in the one direction, and arranged in the first and second mask regions. For each scanning unit connected to the plurality of scanning lines, the plurality of scanning lines are sequentially driven by sequentially propagating start pulses transferred in the one direction through the transfer lines, and the second display. In the mode, all the scanning lines are sequentially driven by propagating a start pulse transferred in the one direction to the scanning lines to all scanning units,
The empty transfer circuit is
A display device that performs idle transfer for a predetermined period before transferring the start pulse to the transfer line corresponding to the display area. A display device having at least a first display mode and a second display mode having different aspect ratios,
Pixel circuits for writing pixel data through the switching elements are arranged in a matrix,
Two areas are assigned as a first mask area and a second mask area in the first display mode with a display area including a plurality of predetermined lines, and in the first display mode, the first and second mask areas are assigned. Mask pixel data is written in each pixel circuit in the second mask area, and video pixel data is written in each pixel circuit in the display area. In the second display mode, the first and second masks are used. A pixel portion in which video pixel data is written to each pixel circuit in the display area and display area;
A plurality of scan lines arranged to correspond to the row arrangement of the pixel circuits, and for controlling conduction of the switching elements;
A plurality of signal lines arranged to correspond to the column arrangement of the pixel circuits and propagating the pixel data;
A vertical driving circuit having a plurality of scanning units for sequentially driving the scanning lines in response to a start pulse;
An empty transfer circuit, and
The vertical drive circuit is
Including a transfer line in which the start pulse is transferred in one direction;
The scanning unit is
In the first display mode, the plurality of scanning lines arranged in the display area are sequentially driven in the one direction, and then the plurality of scanning lines arranged in the first and second mask areas are Drive in order in one direction, and in the second display mode, drive all scan lines in order in the one direction,
The empty transfer circuit is
A display device that performs idle transfer for a predetermined period before transferring the start pulse to the transfer line corresponding to the display area. A display device having at least a first display mode and a second display mode having different aspect ratios,
Pixel circuits for writing pixel data through the switching elements are arranged in a matrix,
A pixel portion in which two areas are allocated as a first mask area and a second mask area in the first display mode across a display area including a predetermined plurality of rows;
A plurality of scan lines arranged to correspond to the row arrangement of the pixel circuits and connected to the switching elements;
A vertical driving circuit having a plurality of scanning units for sequentially driving the scanning lines in response to a start pulse;
An empty transfer circuit, and
The vertical drive circuit is
Including a transfer line in which the start pulse is transferred in one direction;
The scanning unit is
In the first display mode, the plurality of scanning lines arranged in the display area are sequentially driven in the one direction, and then the plurality of scanning lines arranged in the first and second mask areas are Drive in order in one direction, and in the second display mode, drive all scan lines in order in the one direction,
The empty transfer circuit is
A display device that performs idle transfer for a predetermined period before transferring the start pulse to the transfer line corresponding to the display area. A display device having at least a first display mode and a second display mode having different aspect ratios,
Pixel circuits for writing pixel data through the switching elements are arranged in a matrix,
Two areas are assigned as a first mask area and a second mask area in the first display mode with a display area including a plurality of predetermined lines, and in the first display mode, the first and second mask areas are assigned. Mask pixel data is written in each pixel circuit in the second mask area, and video pixel data is written in each pixel circuit in the display area. In the second display mode, the first and second masks are used. A pixel portion in which video pixel data is written to each pixel circuit in the display area and display area;
A plurality of scan lines arranged to correspond to the row arrangement of the pixel circuits, and for controlling conduction of the switching elements;
A plurality of signal lines arranged to correspond to the column arrangement of the pixel circuits and propagating the pixel data;
A plurality of scanning lines connected to each other, and a vertical driving circuit having a plurality of scanning units for selectively scanning the scanning lines by applying a scanning signal to the connected scanning lines in response to a start pulse;
A transfer blocking circuit,
The vertical drive circuit is
A transfer line for transferring the start pulse in one direction, and a switch circuit;
The switch circuit is
In the first display mode, a plurality of start pulses transferred in the one direction are sequentially propagated to the scanning units connected to the plurality of scanning lines arranged in the display area. The scan lines are sequentially driven, and then the start pulse is transferred to the transfer lines corresponding to the first and second mask regions in the one direction, and arranged in the first and second mask regions. For each scanning unit connected to the plurality of scanning lines, the plurality of scanning lines are sequentially driven by sequentially propagating the start pulse transferred in the one direction through the transfer line, and the second display. At the time of mode, all the scanning lines are sequentially driven by propagating a start pulse that is transferred in one direction to the scanning lines for all scanning units,
The transfer blocking circuit is in the first display mode.
A display device that prevents a start pulse transferred on a transfer line corresponding to the first mask area from being transferred to the transfer line corresponding to the display area. A display device having at least a first display mode and a second display mode having different aspect ratios,
Pixel circuits for writing pixel data through the switching elements are arranged in a matrix,
Two areas are assigned as a first mask area and a second mask area in the first display mode with a display area including a plurality of predetermined lines, and in the first display mode, the first and second mask areas are assigned. Mask pixel data is written in each pixel circuit in the second mask area, and video pixel data is written in each pixel circuit in the display area. In the second display mode, the first and second masks are used. A pixel portion in which video pixel data is written to each pixel circuit in the display area and display area;
A plurality of scan lines arranged to correspond to the row arrangement of the pixel circuits, and for controlling conduction of the switching elements;
A plurality of signal lines arranged to correspond to the column arrangement of the pixel circuits and propagating the pixel data;
A vertical driving circuit having a plurality of scanning units for sequentially driving the scanning lines in response to a start pulse;
A transfer blocking circuit,
The vertical drive circuit is
Including a transfer line in which the start pulse is transferred in one direction;
The scanning unit is
In the first display mode, the plurality of scanning lines arranged in the display area are sequentially driven in the one direction, and then the plurality of scanning lines arranged in the first and second mask areas are Drive in order in one direction, and in the second display mode, drive all scan lines in order in the one direction,
The transfer blocking circuit is in the first display mode.
A display device that prevents a start pulse transferred on a transfer line corresponding to the first mask area from being transferred to the transfer line corresponding to the display area. A display device having at least a first display mode and a second display mode having different aspect ratios,
Pixel circuits for writing pixel data through the switching elements are arranged in a matrix,
A pixel portion in which two areas are allocated as a first mask area and a second mask area in the first display mode across a display area including a predetermined plurality of rows;
A plurality of scan lines arranged to correspond to the row arrangement of the pixel circuits and connected to the switching elements;
A vertical driving circuit having a plurality of scanning units for sequentially driving the scanning lines in response to a start pulse;
A transfer blocking circuit,
The vertical drive circuit is
Including a transfer line in which the start pulse is transferred in one direction;
The scanning unit is
In the first display mode, the plurality of scanning lines arranged in the display area are sequentially driven in the one direction, and then the plurality of scanning lines arranged in the first and second mask areas are Drive in order in one direction, and in the second display mode, drive all scan lines in order in the one direction,
The transfer blocking circuit is in the first display mode.
A display device that prevents a start pulse transferred on a transfer line corresponding to the first mask area from being transferred to the transfer line corresponding to the display area. The display device according to claim 4, further comprising: an empty transfer circuit that idle-transfers only a predetermined period before the start pulse is transferred to the transfer line corresponding to the display area.

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