JP2005536925A - 演算増幅器 - Google Patents
演算増幅器 Download PDFInfo
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- JP2005536925A JP2005536925A JP2004528764A JP2004528764A JP2005536925A JP 2005536925 A JP2005536925 A JP 2005536925A JP 2004528764 A JP2004528764 A JP 2004528764A JP 2004528764 A JP2004528764 A JP 2004528764A JP 2005536925 A JP2005536925 A JP 2005536925A
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- Prior art keywords
- operational amplifier
- transistors
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- transistor
- current
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- 238000000034 method Methods 0.000 claims abstract description 11
- 238000013459 approach Methods 0.000 description 8
- 238000012937 correction Methods 0.000 description 6
- 238000004458 analytical method Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 5
- 238000004088 simulation Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000001419 dependent effect Effects 0.000 description 2
- 230000009897 systematic effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004513 sizing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
- H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
- H03F3/45766—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using balancing means
- H03F3/45771—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using balancing means using switching means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
- H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
- H03F3/45748—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using a feedback circuit
- H03F3/45753—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using a feedback circuit using switching means, e.g. sample and hold
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
Description
本発明の好ましい実施の態様は従属請求項より明らかとなる。
Io≒Gm・Vofs−gm(Vc+Vofc) (1)
ここでGmはトランジスタMP1およびMP2のトランスコンダクタンスであり、VofcはトランスコンダクタンスTの入力基準電圧オフセットである。
Claims (10)
- 演算増幅器の少なくとも1つの内部ノードにさらなる電流を導入して前記演算増幅器の出力オフセット電圧を低下させる手段を備える演算増幅器。
- 前記さらなる電流を導入する手段は直流電圧源およびトランスコンダクタを含み、前記直流電圧源は前記トランスコンダクタに電圧を印加し、前記トランスコンダクタは前記さらなる電流を供給する、請求項1に記載の演算増幅器。
- 前記直流電圧源によって前記トランスコンダクタに印加される前記電圧を変化させることができる、請求項2に記載の演算増幅器。
- 前記トランスコンダクタは差動段として実現される、請求項2に記載の演算増幅器。
- 前記トランスコンダクタは、第1、第2、第3および第4のトランジスタを有する差動段を有し、前記各第1、第2、第3および第4のトランジスタはソース、ゲートおよびドレインを有し、前記第1および前記第2のトランジスタの前記ゲートにバイアス電圧が印加され、前記直流電圧源は前記第1のトランジスタの前記ゲートにさらなる電圧を印加し、前記第1および前記第2のトランジスタの前記ソースは前記演算増幅器の供給電圧に接続され、前記第3および前記第4のトランジスタの前記ソースはグランドに接続され、前記第1および前記第2のトランジスタの前記ドレインはそれぞれ前記第3および前記第4のトランジスタの前記ドレインに接続され、前記第3のトランジスタの前記ゲートおよび前記ドレインは互いに短絡し、前記第2および前記第4のトランジスタの前記ドレインの間の前記接続は、前記演算増幅器にさらなる電流を導入する前記演算増幅器の内部ノードに接続されている、請求項4に記載の演算増幅器。
- 前記第1のトランジスタの前記ゲートにさらなる電流を印加することは、前記第1のトランジスタおよび前記第2のトランジスタの前記ゲートに差動電圧信号を印加することを含む、請求項5に記載の演算増幅器。
- 前記演算増幅器の出力オフセット電圧を検出し、検出されたオフセットに従って前記さらなる電流を導入する手段を制御するフィードバック手段をさらに備える、請求項1に記載の演算増幅器。
- 前記演算増幅器は、その通常動作のために、互いに接続された差動入力段および第2段を備え、前記さらなる電流を導入する手段は、前記さらなる電流を前記差動入力段のノードに印加する、請求項1に記載の演算増幅器。
- 前記差動入力段は、第1、第2、第3および第4のトランジスタを含み、前記各第1、第2、第3および第4のトランジスタはソース、ゲートおよびドレインを有し、前記第1および前記第2のトランジスタの前記ゲートは前記演算増幅器の異なる入力端末に接続され、前記第1および前記第2のトランジスタの前記ソースは前記演算増幅器の供給電圧に接続され、前記第3および前記第4のトランジスタの前記ソースはグランドに接続され、前記第1および前記第2のトランジスタの前記ドレインはそれぞれ前記第3および前記第4のトランジスタの前記ドレインに接続され、前記第3のトランジスタの前記ゲートおよび前記ドレインは互いに短絡し、前記第2および前記第4のトランジスタの前記ドレインの間の前記接続は前記第2段に接続され、前記さらなる電流を導入する手段は、前記第1および前記第3のトランジスタの前記ドレインの間の前記接続に前記さらなる電流を印加する、請求項8に記載の演算増幅器。
- 演算増幅器の出力オフセット電圧を低下させる方法であって、前記演算増幅器の少なくとも1つの内部ノードにさらなる電流を導入することを備える、方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02018582 | 2002-08-19 | ||
PCT/IB2003/003647 WO2004017514A1 (en) | 2002-08-19 | 2003-08-12 | Operational amplifier |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2005536925A true JP2005536925A (ja) | 2005-12-02 |
Family
ID=31725347
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004528764A Pending JP2005536925A (ja) | 2002-08-19 | 2003-08-12 | 演算増幅器 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7248104B2 (ja) |
EP (1) | EP1537654A1 (ja) |
JP (1) | JP2005536925A (ja) |
CN (1) | CN1675830A (ja) |
AU (1) | AU2003253182A1 (ja) |
WO (1) | WO2004017514A1 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7109697B1 (en) * | 2005-06-29 | 2006-09-19 | Texas Instruments Incorporated | Temperature-independent amplifier offset trim circuit |
US20070127149A1 (en) * | 2005-12-02 | 2007-06-07 | Texas Instruments Incorporated | Offset cancellation scheme for perpendicular reader |
TWI342119B (en) * | 2007-11-07 | 2011-05-11 | Realtek Semiconductor Corp | Output stage circuit and operational amplifier thereof |
WO2011071836A1 (en) * | 2009-12-10 | 2011-06-16 | Marvell World Trade Ltd | Circuits and methods for calibrating offset in an amplifier |
US8698560B2 (en) * | 2012-05-09 | 2014-04-15 | Mstar Semiconductor, Inc. | Variable-gain low noise amplifier |
TWI577153B (zh) * | 2015-10-08 | 2017-04-01 | 九暘電子股份有限公司 | 乙太網路供電設備的增益電路 |
US9787263B2 (en) | 2015-11-23 | 2017-10-10 | Texas Instruments Incorporated | Mismatch correction in differential amplifiers using analog floating gate transistors |
US10164591B1 (en) * | 2017-08-23 | 2018-12-25 | Qualcomm Incorporated | Differential amplifier with common-mode biasing technique |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2951024A1 (de) | 1979-12-19 | 1981-06-25 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Verstaerkerschaltung |
JPS59196613A (ja) * | 1983-04-21 | 1984-11-08 | Toshiba Corp | 演算増幅回路 |
US4622521A (en) * | 1985-12-23 | 1986-11-11 | Linear Technology Corporation | Precision operational amplifier using data sampling |
US4760349A (en) * | 1986-08-19 | 1988-07-26 | Regents Of The University Of Minnesota | CMOS analog standard cell arrays using linear transconductance elements |
US4884039A (en) | 1988-09-09 | 1989-11-28 | Texas Instruments Incorporated | Differential amplifier with low noise offset compensation |
GB9204434D0 (en) | 1992-02-27 | 1992-04-15 | Sec Dep For The Defence | Differential amplifier |
FR2714548B1 (fr) * | 1993-12-23 | 1996-03-15 | Sgs Thomson Microelectronics | Amplificateur à correction de tension de décalage. |
AU9014298A (en) | 1997-08-01 | 1999-02-22 | Lsi Logic Corporation | Offset adjustment of cmos matched pairs with body voltage |
JP2000049546A (ja) | 1998-07-28 | 2000-02-18 | Mitsubishi Electric Corp | オフセット調整装置 |
US6583660B2 (en) * | 2001-05-25 | 2003-06-24 | Infineon Technologies Ag | Active auto zero circuit for time continuous open loop amplifiers |
JP4629279B2 (ja) * | 2001-08-17 | 2011-02-09 | 富士通セミコンダクター株式会社 | オフセットキャンセル機能を有するオペアンプ |
US6683441B2 (en) * | 2001-11-26 | 2004-01-27 | Analog Devices, Inc. | Multi-phase switching regulator |
US6621333B1 (en) * | 2001-12-11 | 2003-09-16 | National Semiconductor Corporation | Circuit and method to counter offset voltage induced by load changes |
US20050110550A1 (en) * | 2003-11-24 | 2005-05-26 | Qian Shi | DC offset cancellation in a direct-conversion receiver |
-
2003
- 2003-08-12 JP JP2004528764A patent/JP2005536925A/ja active Pending
- 2003-08-12 EP EP03787968A patent/EP1537654A1/en not_active Withdrawn
- 2003-08-12 AU AU2003253182A patent/AU2003253182A1/en not_active Abandoned
- 2003-08-12 CN CN03819649.2A patent/CN1675830A/zh active Pending
- 2003-08-12 WO PCT/IB2003/003647 patent/WO2004017514A1/en not_active Application Discontinuation
- 2003-08-12 US US10/524,570 patent/US7248104B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP1537654A1 (en) | 2005-06-08 |
AU2003253182A1 (en) | 2004-03-03 |
WO2004017514A1 (en) | 2004-02-26 |
CN1675830A (zh) | 2005-09-28 |
US20050231275A1 (en) | 2005-10-20 |
US7248104B2 (en) | 2007-07-24 |
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