JP2005519260A5 - - Google Patents

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Publication number
JP2005519260A5
JP2005519260A5 JP2003537118A JP2003537118A JP2005519260A5 JP 2005519260 A5 JP2005519260 A5 JP 2005519260A5 JP 2003537118 A JP2003537118 A JP 2003537118A JP 2003537118 A JP2003537118 A JP 2003537118A JP 2005519260 A5 JP2005519260 A5 JP 2005519260A5
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JP
Japan
Prior art keywords
defect
sub
test
potential
test structure
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JP2003537118A
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English (en)
Japanese (ja)
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JP4505225B2 (ja
JP2005519260A (ja
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Priority claimed from US10/265,051 external-priority patent/US6995393B2/en
Priority claimed from US10/264,625 external-priority patent/US7067335B2/en
Application filed filed Critical
Priority claimed from PCT/US2002/033154 external-priority patent/WO2003034492A2/en
Publication of JP2005519260A publication Critical patent/JP2005519260A/ja
Publication of JP2005519260A5 publication Critical patent/JP2005519260A5/ja
Application granted granted Critical
Publication of JP4505225B2 publication Critical patent/JP4505225B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2003537118A 2001-10-17 2002-10-16 半導体ｉｃ欠陥検出の装置および方法 Expired - Fee Related JP4505225B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US32980401P 2001-10-17 2001-10-17
US10/265,051 US6995393B2 (en) 2000-08-25 2002-10-02 Apparatus and methods for semiconductor IC failure detection
US10/264,625 US7067335B2 (en) 2000-08-25 2002-10-02 Apparatus and methods for semiconductor IC failure detection
PCT/US2002/033154 WO2003034492A2 (en) 2001-10-17 2002-10-16 Apparatus and methods for semiconductor ic failure detection

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2009219052A Division JP5238659B2 (ja) 2001-10-17 2009-09-24 半導体ｉｃ欠陥検出の装置および方法

Publications (3)

Publication Number Publication Date
JP2005519260A JP2005519260A (ja) 2005-06-30
JP2005519260A5 true JP2005519260A5 (https=) 2006-01-05
JP4505225B2 JP4505225B2 (ja) 2010-07-21

Family

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Family Applications (1)

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JP2003537118A Expired - Fee Related JP4505225B2 (ja) 2001-10-17 2002-10-16 半導体ｉｃ欠陥検出の装置および方法

Country Status (2)

Country Link
JP (1) JP4505225B2 (https=)
WO (1) WO2003034492A2 (https=)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4687729B2 (ja) 2008-03-04 2011-05-25 日本電気株式会社 キャッシュメモリ及びベクトル処理装置並びにベクトルデータ整列方法
US10199283B1 (en) 2015-02-03 2019-02-05 Pdf Solutions, Inc. Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage
US9805994B1 (en) 2015-02-03 2017-10-31 Pdf Solutions, Inc. Mesh-style NCEM pads, and process for making semiconductor dies, chips, and wafers using in-line measurements from such pads
US9799575B2 (en) 2015-12-16 2017-10-24 Pdf Solutions, Inc. Integrated circuit containing DOEs of NCEM-enabled fill cells
US10593604B1 (en) 2015-12-16 2020-03-17 Pdf Solutions, Inc. Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells
US10978438B1 (en) 2015-12-16 2021-04-13 Pdf Solutions, Inc. IC with test structures and E-beam pads embedded within a contiguous standard cell area
US9929063B1 (en) 2016-04-04 2018-03-27 Pdf Solutions, Inc. Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
US9646961B1 (en) 2016-04-04 2017-05-09 Pdf Solutions, Inc. Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and metal-short-configured, NCEM-enabled fill cells
US9905553B1 (en) 2016-04-04 2018-02-27 Pdf Solutions, Inc. Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells
US9748153B1 (en) 2017-03-29 2017-08-29 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configure
US9773774B1 (en) 2017-03-30 2017-09-26 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells
US9768083B1 (en) 2017-06-27 2017-09-19 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells
US9786649B1 (en) 2017-06-27 2017-10-10 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including stitch open configured fill cells
US9865583B1 (en) 2017-06-28 2018-01-09 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including stitch open configured fill cells
US10096530B1 (en) 2017-06-28 2018-10-09 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05144901A (ja) * 1991-11-21 1993-06-11 Oki Electric Ind Co Ltd 微細パターンを有するデバイスの不良箇所検出方法
JP3356056B2 (ja) * 1998-05-15 2002-12-09 日本電気株式会社 配線不良検出回路、配線不良検出用半導体ウェハ及びこれらを用いた配線不良検出方法
US6452412B1 (en) * 1999-03-04 2002-09-17 Advanced Micro Devices, Inc. Drop-in test structure and methodology for characterizing an integrated circuit process flow and topography
US6268717B1 (en) * 1999-03-04 2001-07-31 Advanced Micro Devices, Inc. Semiconductor test structure with intentional partial defects and method of use
JP3708763B2 (ja) * 1999-08-31 2005-10-19 株式会社東芝 欠陥検出方法

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