JP2005519260A5 - - Google Patents
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- JP2005519260A5 JP2005519260A5 JP2003537118A JP2003537118A JP2005519260A5 JP 2005519260 A5 JP2005519260 A5 JP 2005519260A5 JP 2003537118 A JP2003537118 A JP 2003537118A JP 2003537118 A JP2003537118 A JP 2003537118A JP 2005519260 A5 JP2005519260 A5 JP 2005519260A5
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- 239000004065 semiconductor Substances 0.000 claims 21
- 238000007689 inspection Methods 0.000 claims 20
- 238000004519 manufacturing process Methods 0.000 claims 11
- 230000001429 stepping Effects 0.000 claims 9
- 239000002245 particle Substances 0.000 claims 8
- 238000000034 method Methods 0.000 claims 6
- 238000010894 electron beam technology Methods 0.000 claims 5
- 230000002950 deficient Effects 0.000 claims 4
- 239000000758 substrate Substances 0.000 claims 2
Claims (42)
電圧コントラスト検査中に第1電位に帯電するよう設計された複数のフローティング導電構造を有する第1サブ構造領域、および
前記電圧コントラスト検査中に前記第1電位とは異なる第2電位に帯電するように選択されたサイズを有する導電構造に結合された第2サブ構造領域
を備えるテスト用半導体装置。 A test semiconductor device having a test structure designed for voltage contrast inspection,
The first sub-structure region having a plurality of floating conductive structure designed to charge the first potential in the voltage contrast test, and
Before Symbol Voltage testing a semiconductor device including a second sub-structure region coupled to a conductive structure having a size selected so that to a static-different second potential to the first potential during contrast test.
電子ビームによる走査によって第1電位に帯電するよう設計された複数のフローティング導電構造を有する第1サブ構造領域を形成すること、および
前記電子ビームによる走査によって前記第1電位とは異なる第2電位に帯電させるように選択されたサイズを有する導電構造に結合される第2サブ構造領域を形成すること
を含み、
前記第1および第2サブ構造領域は共に単一のフォトリソグラフィステップで形成される製造方法。 A method of manufacturing a test semiconductor device designed for voltage contrast inspection,
Forming a first sub-structure region having a plurality of floating conductive structure designed to charge the first potential by the scanning by the electron beam, and a different second potential to the first potential by scanning by the electron beam comprises forming the second sub-structure region which is coupled to a conductive structure having a selected size so as to charge the,
Wherein the first and second sub-structure region manufacturing method together formed in a single photolithographic step.
最初に前記テスト構造の2つ以上の初期部分を帯電された粒子ビームで走査することによって、前記初期走査の結果として前記テスト構造内に予期しないパターンの電位が存在するかに基づいて、前記テスト構造内に欠陥が存在するか否かを決定すること、および
欠陥が存在するとき、前記テスト構造の1つ以上の潜在的欠陥部分に順次にステップ移動し、前記テスト構造の前記1つ以上の潜在的欠陥部分を、帯電された粒子ビームで走査し、それにより前記欠陥を位置特定すること
を含む方法。 A method for inspecting a test structure provided in a semiconductor ,
Based on whether there is an unexpected pattern of potential in the test structure as a result of the initial scan by first scanning two or more initial portions of the test structure with a charged particle beam. Determining whether a defect is present in the structure; and, when there is a defect, sequentially stepping to one or more potential defect portions of the test structure, the one or more of the test structure Scanning a potential defect with a charged particle beam, thereby locating the defect.
前記テスト構造の第1端を走査することによって前記第1端の第1電位を得ること、
前記テスト構造の第2端を走査することによって前記第2端の第2電位を得ること、および
前記第1端の電位が前記第2端の電位と異なるとき、前記テスト構造は開放欠陥を有すると決定すること
を含む方法。 23. A method according to claim 21 or 22, wherein first determining two or more initial portions of the test structure with a charged particle beam to determine whether a defect is present. ,
Obtaining a first potential at the first end by scanning a first end of the test structure;
Obtaining a second potential at the second end by scanning the second end of the test structure; and when the potential at the first end is different from the potential at the second end, the test structure has an open defect. A method that includes determining then.
(a)前記テスト構造の第1現在位置にステップ移動し、前記テスト構造の前記第1現在位置を欠陥を探して走査すること、
(b)前記欠陥が見つからず、かつ輝度の遷移が前記前の走査および現在の走査の間で起こるとき、前記前の走査および前記現在の走査の間にある前記テスト構造の次の部分へステップ移動すること、および
(c)前記欠陥が見つからず、かつ輝度の遷移が前記前の走査および現在の走査の間で起こらないとき、前記前の走査および前記現在の走査の間ではない前記テスト構造の次の部分へステップ移動すること
を含む方法。 24. A method as claimed in claim 21 to claim 23, sequentially stepping to one or more potential defect portions of the test structure and charging the one or more potential defect portions of the test structure. Scanning with a focused particle beam, thereby locating the defect,
(A) stepping to a first current position of the test structure and scanning the first current position of the test structure looking for a defect;
(B) when the defect is not found and a luminance transition occurs between the previous scan and the current scan, step to the next part of the test structure between the previous scan and the current scan And (c) the test structure not between the previous scan and the current scan when the defect is not found and a luminance transition does not occur between the previous scan and the current scan. Including stepping to the next part of the.
前記欠陥が見つからず、かつ輝度の遷移が前記前の走査および現在の走査の間で起こるとき、前記次の部分は、前記前の走査および前記現在の走査の間の中間にあるとし、
前記欠陥が見つからず、かつ輝度の遷移が前記前の走査および現在の走査の間で起こらないとき、前記次の部分は、前記現在の走査と、前記前の走査および前記現在の走査の間ではない前記テスト構造の一端との間の中間にあるとする
方法。 25. The method of claim 24, comprising:
The defect is not found, and when the transition of brightness occurring between the previous scan and the current scan, the next portion, intermediate near suppose between said previous scan and said current scan,
When the defect is not found and no luminance transition occurs between the previous scan and the current scan, the next portion is between the current scan and the previous scan and the current scan. and in the middle between the free end of the test structure
Method.
前記現在の走査が、欠陥ではない前記現在の走査についての輝度の遷移点を含むかを決定することをさらに含み、
前記次の部分へステップ移動する操作は、前記現在の走査が欠陥ではない前記輝度の遷移点を含むとき、新しい向きにおいて実行される
方法。 26. The method of claim 25, comprising:
Further determining whether the current scan includes a luminance transition point for the current scan that is not defective;
The method of stepping to the next part is performed in a new orientation when the current scan includes the luminance transition point that is not defective.
前記欠陥は開放欠陥でありえ、前記欠陥は、輝度の遷移が前記テスト構造自身の中に起きているとき、前記開放欠陥であるとする方法。 A method according to any of claims 21 to 28, wherein
The defect is an open defect example, the defect when the transition of brightness is happening in the test structure itself, a method of the said is an open defect.
前記欠陥は短絡欠陥でありえ、前記欠陥は、物理的短絡が前記テスト構造内で見つかったときに前記短絡欠陥であるとする方法。 A method according to any of claims 21 to 28, wherein
How to the defect is short defect example, the defect is the short defect when physical short circuit is bought One found within the test structure.
電子ビームを発生するビーム発生器、
電子を検出する検出器、および
最初に前記テスト構造の2つ以上の初期部分を帯電された粒子ビームで走査することによって、前記初期走査の結果として前記テスト構造内に予期しないパターンの電位が存在するかに基づいて、前記テスト構造内に欠陥が存在するかを決定し、
欠陥が存在するとき、前記テスト構造の1つ以上の潜在的欠陥部分に順次にステップ移動し、前記テスト構造の前記1つ以上の潜在的欠陥部分を帯電された粒子ビームで走査し、それにより前記欠陥を位置特定するように構成されたコントローラ
を備える検査システム。 An inspection system for detecting contact Keru defects in the test structure provided on a semiconductor,
A beam generator for generating an electron beam,
A detector that detects electrons, and by initially scanning two or more initial portions of the test structure with a charged particle beam, there is an unexpected pattern of potential in the test structure as a result of the initial scan. Based on whether or not there are defects in the test structure;
When a defect is present, it sequentially steps to one or more potential defect portions of the test structure and scans the one or more potential defect portions of the test structure with a charged particle beam, thereby An inspection system comprising a controller configured to locate the defect.
最初に前記テスト構造の2つ以上の初期部分を帯電された粒子ビームで走査することによって、前記テスト構造内に欠陥が存在するかを決定することは、
前記テスト構造の第1端を走査することによって前記第1端の第1電位を得ること、
前記テスト構造の第2端を走査することによって前記第2端の第2電位を得ること、および
前記第1端の電位が前記第2端の電位と異なるとき、前記テスト構造は開放欠陥を有すると決定すること
によって達成される検査システム。 The inspection system according to claim 32 or 33,
Determining whether a defect is present in the test structure by first scanning two or more initial portions of the test structure with a charged particle beam;
Obtaining a first potential at the first end by scanning a first end of the test structure;
Obtaining a second potential at the second end by scanning the second end of the test structure; and when the potential at the first end is different from the potential at the second end, the test structure has an open defect. An inspection system achieved by deciding upon.
前記テスト構造の1つ以上の潜在的欠陥部分に順次にステップ移動し、前記テスト構造の前記1つ以上の潜在的欠陥部分を帯電された粒子ビームで走査し、それにより前記欠陥を位置特定することは、
(a)前記テスト構造の第1現在位置にステップ移動し、前記テスト構造の前記第1現在位置を欠陥を探して走査すること、
(b)前記欠陥が見つからず、かつ輝度の遷移が前記前の走査および現在の走査の間で起こるとき、前記前の走査および前記現在の走査の間にある前記テスト構造の次の部分へステップ移動すること、および
(c)前記欠陥が見つからず、かつ輝度の遷移が前記前の走査および現在の走査の間で起こらないとき、前記前の走査および前記現在の走査の間ではない前記テスト構造の次の部分へステップ移動すること
を含む検査システム。 An inspection system according to any of claims 32 to 34,
Stepping sequentially to one or more potential defect portions of the test structure, scanning the one or more potential defect portions of the test structure with a charged particle beam, thereby locating the defect That is
(A) stepping to a first current position of the test structure and scanning the first current position of the test structure looking for a defect;
(B) when the defect is not found and a luminance transition occurs between the previous scan and the current scan, step to the next part of the test structure between the previous scan and the current scan And (c) the test structure not between the previous scan and the current scan when the defect is not found and a luminance transition does not occur between the previous scan and the current scan. Inspection system including stepping to the next part of
前記欠陥が見つからず、かつ輝度の遷移が前記前の走査および現在の走査の間で起こるとき、前記次の部分は、前記前の走査および前記現在の走査の間の中間にあるとし、
前記欠陥が見つからず、かつ輝度の遷移が前記前の走査および現在の走査の間で起こらないとき、前記次の部分は、前記現在の走査と、前記前の走査および前記現在の走査の間ではない前記テスト構造の一端との間の中間にあるとする
検査システム。 The inspection system according to claim 35, wherein
The defect is not found, and when the transition of brightness occurring between the previous scan and the current scan, the next portion, intermediate near suppose between said previous scan and said current scan,
When the defect is not found and no luminance transition occurs between the previous scan and the current scan, the next portion is between the current scan and the previous scan and the current scan. and in the middle between the free end of the test structure
Inspection system.
前記コントローラは、前記現在の走査が、欠陥ではない前記現在の走査についての輝度の遷移点を含むかを決定するようにさらに構成され、
前記次の部分へステップ移動する操作は、前記現在の走査が欠陥ではない前記輝度の遷移点を含むとき、新しい向きにおいて実行される
検査システム。 The inspection system according to claim 36, wherein
The controller is further configured to determine whether the current scan includes a luminance transition point for the current scan that is not defective;
The stepping operation to the next part is performed in a new orientation when the current scan includes a non-defective luminance transition point.
前記欠陥は開放欠陥でありえ、前記欠陥は、輝度の遷移が前記テスト構造自身の中に起きているときには、前記開放欠陥であるとする検査システム。 40. The inspection system according to any one of claims 32 to 39, wherein:
Inspection system wherein defect example an open defect, the defect is to be when the transition of brightness is happening in the test structure itself is the open defect.
前記欠陥は短絡欠陥であり、前記欠陥は、物理的短絡が前記テスト構造内に見つかったときに前記短絡欠陥であるとする検査システム。 40. The inspection system according to any one of claims 32 to 39, wherein:
The defect is a short defect, the defect inspection system that said a short defect when physical short circuit was not find in the test structure.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US32980401P | 2001-10-17 | 2001-10-17 | |
US10/265,051 US6995393B2 (en) | 2000-08-25 | 2002-10-02 | Apparatus and methods for semiconductor IC failure detection |
US10/264,625 US7067335B2 (en) | 2000-08-25 | 2002-10-02 | Apparatus and methods for semiconductor IC failure detection |
PCT/US2002/033154 WO2003034492A2 (en) | 2001-10-17 | 2002-10-16 | Apparatus and methods for semiconductor ic failure detection |
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JP2009219052A Division JP5238659B2 (en) | 2001-10-17 | 2009-09-24 | Apparatus and method for semiconductor IC defect detection |
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JP2005519260A JP2005519260A (en) | 2005-06-30 |
JP2005519260A5 true JP2005519260A5 (en) | 2006-01-05 |
JP4505225B2 JP4505225B2 (en) | 2010-07-21 |
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JP2003537118A Expired - Fee Related JP4505225B2 (en) | 2001-10-17 | 2002-10-16 | Apparatus and method for semiconductor IC defect detection |
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JP (1) | JP4505225B2 (en) |
WO (1) | WO2003034492A2 (en) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
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US9799575B2 (en) | 2015-12-16 | 2017-10-24 | Pdf Solutions, Inc. | Integrated circuit containing DOEs of NCEM-enabled fill cells |
US9805994B1 (en) | 2015-02-03 | 2017-10-31 | Pdf Solutions, Inc. | Mesh-style NCEM pads, and process for making semiconductor dies, chips, and wafers using in-line measurements from such pads |
US10199283B1 (en) | 2015-02-03 | 2019-02-05 | Pdf Solutions, Inc. | Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage |
US10593604B1 (en) | 2015-12-16 | 2020-03-17 | Pdf Solutions, Inc. | Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells |
US10978438B1 (en) | 2015-12-16 | 2021-04-13 | Pdf Solutions, Inc. | IC with test structures and E-beam pads embedded within a contiguous standard cell area |
US9646961B1 (en) | 2016-04-04 | 2017-05-09 | Pdf Solutions, Inc. | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and metal-short-configured, NCEM-enabled fill cells |
US9929063B1 (en) | 2016-04-04 | 2018-03-27 | Pdf Solutions, Inc. | Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates |
US9905553B1 (en) | 2016-04-04 | 2018-02-27 | Pdf Solutions, Inc. | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells |
US9748153B1 (en) | 2017-03-29 | 2017-08-29 | Pdf Solutions, Inc. | Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configure |
US9773774B1 (en) | 2017-03-30 | 2017-09-26 | Pdf Solutions, Inc. | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells |
US9768083B1 (en) | 2017-06-27 | 2017-09-19 | Pdf Solutions, Inc. | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells |
US9786649B1 (en) | 2017-06-27 | 2017-10-10 | Pdf Solutions, Inc. | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including stitch open configured fill cells |
US10096530B1 (en) | 2017-06-28 | 2018-10-09 | Pdf Solutions, Inc. | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells |
US9865583B1 (en) | 2017-06-28 | 2018-01-09 | Pdf Solutions, Inc. | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including stitch open configured fill cells |
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JPH05144901A (en) * | 1991-11-21 | 1993-06-11 | Oki Electric Ind Co Ltd | Detection of defective point of device having fine pattern |
JP3356056B2 (en) * | 1998-05-15 | 2002-12-09 | 日本電気株式会社 | Wiring fault detecting circuit, wiring fault detecting semiconductor wafer, and wiring fault detecting method using the same |
US6268717B1 (en) * | 1999-03-04 | 2001-07-31 | Advanced Micro Devices, Inc. | Semiconductor test structure with intentional partial defects and method of use |
US6452412B1 (en) * | 1999-03-04 | 2002-09-17 | Advanced Micro Devices, Inc. | Drop-in test structure and methodology for characterizing an integrated circuit process flow and topography |
JP3708763B2 (en) * | 1999-08-31 | 2005-10-19 | 株式会社東芝 | Defect detection method |
-
2002
- 2002-10-16 JP JP2003537118A patent/JP4505225B2/en not_active Expired - Fee Related
- 2002-10-16 WO PCT/US2002/033154 patent/WO2003034492A2/en active Application Filing
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