JP2005512237A5 - - Google Patents

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Publication number
JP2005512237A5
JP2005512237A5 JP2003551711A JP2003551711A JP2005512237A5 JP 2005512237 A5 JP2005512237 A5 JP 2005512237A5 JP 2003551711 A JP2003551711 A JP 2003551711A JP 2003551711 A JP2003551711 A JP 2003551711A JP 2005512237 A5 JP2005512237 A5 JP 2005512237A5
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JP
Japan
Prior art keywords
assertion
pin
arc
timing model
port
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Pending
Application number
JP2003551711A
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English (en)
Japanese (ja)
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JP2005512237A (ja
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Publication date
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Priority claimed from PCT/US2002/038941 external-priority patent/WO2003050725A2/en
Publication of JP2005512237A publication Critical patent/JP2005512237A/ja
Publication of JP2005512237A5 publication Critical patent/JP2005512237A5/ja
Pending legal-status Critical Current

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JP2003551711A 2001-12-07 2002-12-06 タイミングモデル抽出のためのアサーションハンドリング Pending JP2005512237A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US33923501P 2001-12-07 2001-12-07
PCT/US2002/038941 WO2003050725A2 (en) 2001-12-07 2002-12-06 Assertion handling for timing model extraction

Publications (2)

Publication Number Publication Date
JP2005512237A JP2005512237A (ja) 2005-04-28
JP2005512237A5 true JP2005512237A5 (enExample) 2005-12-22

Family

ID=23328095

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2003551710A Pending JP2005512236A (ja) 2001-12-07 2002-12-06 タイミンググラフ縮小によるタイミングモデル抽出
JP2003551711A Pending JP2005512237A (ja) 2001-12-07 2002-12-06 タイミングモデル抽出のためのアサーションハンドリング

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP2003551710A Pending JP2005512236A (ja) 2001-12-07 2002-12-06 タイミンググラフ縮小によるタイミングモデル抽出

Country Status (5)

Country Link
US (2) US7356451B2 (enExample)
EP (2) EP1451730A2 (enExample)
JP (2) JP2005512236A (enExample)
AU (2) AU2002359605A1 (enExample)
WO (2) WO2003050724A2 (enExample)

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US6836874B2 (en) * 2002-06-26 2004-12-28 Agilent Technologies, Inc. Systems and methods for time-budgeting a complex hierarchical integrated circuit
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US20050091555A1 (en) * 2003-10-27 2005-04-28 Tong Xiao Abstraction generation for hierarchical timing analysis using implicity connectivity graph derived from domain propagation
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US8977995B1 (en) * 2007-01-10 2015-03-10 Cadence Design Systems, Inc. Timing budgeting of nested partitions for hierarchical integrated circuit designs
US8640066B1 (en) * 2007-01-10 2014-01-28 Cadence Design Systems, Inc. Multi-phase models for timing closure of integrated circuit designs
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US7962872B2 (en) * 2007-12-04 2011-06-14 Texas Instruments Incorporated Timing analysis when integrating multiple circuit blocks while balancing resource requirements and accuracy
US8499230B2 (en) * 2008-05-07 2013-07-30 Lsi Corporation Critical path monitor for an integrated circuit and method of operation thereof
US8122404B2 (en) * 2009-02-19 2012-02-21 International Business Machines Corporation Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits
US8239805B2 (en) 2009-07-27 2012-08-07 Lsi Corporation Method for designing integrated circuits employing a partitioned hierarchical design flow and an apparatus employing the method
US8341573B2 (en) * 2010-10-15 2012-12-25 Lsi Corporation Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flow
US8458637B2 (en) * 2010-10-22 2013-06-04 International Business Machines Corporation Implementing enhanced RLM connectivity on a hierarchical design with top level pipeline registers
US8589846B2 (en) * 2011-12-02 2013-11-19 Synopsys, Inc. Modeling transition effects for circuit optimization
US8522179B1 (en) * 2012-02-06 2013-08-27 Lsi Corporation System and method for managing timing margin in a hierarchical integrated circuit design process
US8990445B2 (en) * 2012-03-05 2015-03-24 Mediatek Inc. Control chip for communicating with wired connection interface by using one configurable pin selectively serving as input pin or output pin
US8578304B1 (en) * 2012-07-26 2013-11-05 International Business Machines Corporation Implementing mulitple mask lithography timing variation mitigation
US20140156233A1 (en) * 2012-12-03 2014-06-05 Can Wang Method and apparatus for electronic circuit simulation
US8977998B1 (en) * 2013-02-21 2015-03-10 Altera Corporation Timing analysis with end-of-life pessimism removal
US8713502B1 (en) 2013-02-26 2014-04-29 International Business Machines Corporation Methods and systems to reduce a number of simulations in a timing analysis
TW201523312A (zh) * 2013-09-06 2015-06-16 Blue Pearl Software Inc 使用者灰色單元
US9940431B2 (en) 2016-01-07 2018-04-10 International Business Machines Corporation Accurate statistical timing for boundary gates of hierarchical timing models
JP2017167732A (ja) * 2016-03-15 2017-09-21 株式会社東芝 回路設計検証装置およびプログラム
US10223493B1 (en) 2016-06-28 2019-03-05 Altera Corporation Dynamic tag allocation for clock reconvergence pessimism removal
US9977850B2 (en) * 2016-07-12 2018-05-22 International Business Machines Corporation Callback based constraint processing for clock domain independence
US10394987B2 (en) * 2017-03-21 2019-08-27 International Business Machines Corporation Adaptive bug-search depth for simple and deep counterexamples
US11176293B1 (en) * 2018-03-07 2021-11-16 Synopsys, Inc. Method and system for emulation clock tree reduction
US10747925B1 (en) * 2019-01-25 2020-08-18 International Business Machines Corporation Variable accuracy incremental timing analysis
US11188696B1 (en) * 2019-04-15 2021-11-30 Cadence Design Systems, Inc. Method, system, and product for deferred merge based method for graph based analysis pessimism reduction
US10831954B1 (en) 2019-10-29 2020-11-10 International Business Machines Corporation Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs
US10891412B1 (en) 2020-02-13 2021-01-12 International Business Machines Corporation Offline analysis of hierarchical electronic design automation derived data

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