AU2002359605A1 - Timing model extraction by timing graph reduction - Google Patents

Timing model extraction by timing graph reduction

Info

Publication number
AU2002359605A1
AU2002359605A1 AU2002359605A AU2002359605A AU2002359605A1 AU 2002359605 A1 AU2002359605 A1 AU 2002359605A1 AU 2002359605 A AU2002359605 A AU 2002359605A AU 2002359605 A AU2002359605 A AU 2002359605A AU 2002359605 A1 AU2002359605 A1 AU 2002359605A1
Authority
AU
Australia
Prior art keywords
timing
model extraction
graph reduction
reduction
timing model
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002359605A
Other languages
English (en)
Inventor
Krishna Prasad Belkhale
Harish Kriplani
Cho Woo Moon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cadence Design Systems Inc
Original Assignee
Cadence Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cadence Design Systems Inc filed Critical Cadence Design Systems Inc
Publication of AU2002359605A1 publication Critical patent/AU2002359605A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/08—Intellectual property [IP] blocks or IP cores

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Stored Programmes (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
AU2002359605A 2001-12-07 2002-12-06 Timing model extraction by timing graph reduction Abandoned AU2002359605A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US33923501P 2001-12-07 2001-12-07
US60/339,235 2001-12-07
PCT/US2002/038799 WO2003050724A2 (en) 2001-12-07 2002-12-06 Timing model extraction by timing graph reduction

Publications (1)

Publication Number Publication Date
AU2002359605A1 true AU2002359605A1 (en) 2003-06-23

Family

ID=23328095

Family Applications (2)

Application Number Title Priority Date Filing Date
AU2002359605A Abandoned AU2002359605A1 (en) 2001-12-07 2002-12-06 Timing model extraction by timing graph reduction
AU2002351253A Abandoned AU2002351253A1 (en) 2001-12-07 2002-12-06 Assertion handling for timing model extraction

Family Applications After (1)

Application Number Title Priority Date Filing Date
AU2002351253A Abandoned AU2002351253A1 (en) 2001-12-07 2002-12-06 Assertion handling for timing model extraction

Country Status (5)

Country Link
US (2) US7356451B2 (enExample)
EP (2) EP1451730A2 (enExample)
JP (2) JP2005512236A (enExample)
AU (2) AU2002359605A1 (enExample)
WO (2) WO2003050724A2 (enExample)

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US6836874B2 (en) * 2002-06-26 2004-12-28 Agilent Technologies, Inc. Systems and methods for time-budgeting a complex hierarchical integrated circuit
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US7983891B1 (en) * 2003-08-19 2011-07-19 Cadence Design Systems, Inc. Receiver dependent selection of a worst-case timing event for static timing analysis
US20050091555A1 (en) * 2003-10-27 2005-04-28 Tong Xiao Abstraction generation for hierarchical timing analysis using implicity connectivity graph derived from domain propagation
US7243313B1 (en) * 2003-11-24 2007-07-10 Cadence Design Systems, Inc. System and method for reducing the size of RC circuits
US7076753B2 (en) * 2003-12-18 2006-07-11 Synopsys, Inc. Method and apparatus for solving sequential constraints
US7606692B2 (en) * 2004-04-26 2009-10-20 Lsi Corporation Gate-level netlist reduction for simulating target modules of a design
US7089143B2 (en) * 2004-04-29 2006-08-08 International Business Machines Corporation Method and system for evaluating timing in an integrated circuit
JP2006039621A (ja) * 2004-07-22 2006-02-09 Nec Electronics Corp タイミング制約ライブラリの作成方法及び作成システム
US20060190235A1 (en) * 2005-02-22 2006-08-24 Faraday Technology Corp. Verilog HDL simulation model for retain time
US20080115099A1 (en) * 2006-11-15 2008-05-15 Priyadarsan Patra Spatial curvature for multiple objective routing
JP4872635B2 (ja) * 2006-12-06 2012-02-08 日本電気株式会社 電子回路用プリント基板の設計方法とシステム
US7926011B1 (en) * 2007-01-10 2011-04-12 Cadence Design Systems, Inc. System and method of generating hierarchical block-level timing constraints from chip-level timing constraints
US8365113B1 (en) * 2007-01-10 2013-01-29 Cadence Design Systems, Inc. Flow methodology for single pass parallel hierarchical timing closure of integrated circuit designs
US8977995B1 (en) * 2007-01-10 2015-03-10 Cadence Design Systems, Inc. Timing budgeting of nested partitions for hierarchical integrated circuit designs
US8640066B1 (en) * 2007-01-10 2014-01-28 Cadence Design Systems, Inc. Multi-phase models for timing closure of integrated circuit designs
JP2009037278A (ja) * 2007-07-31 2009-02-19 Nec Corp 動作タイミング検証装置、方法、及び、プログラム
US8239798B1 (en) * 2007-08-03 2012-08-07 Cadence Design Systems, Inc. Methods, systems, and apparatus for variation aware extracted timing models
US7962872B2 (en) * 2007-12-04 2011-06-14 Texas Instruments Incorporated Timing analysis when integrating multiple circuit blocks while balancing resource requirements and accuracy
US8499230B2 (en) * 2008-05-07 2013-07-30 Lsi Corporation Critical path monitor for an integrated circuit and method of operation thereof
US8122404B2 (en) * 2009-02-19 2012-02-21 International Business Machines Corporation Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits
US8239805B2 (en) 2009-07-27 2012-08-07 Lsi Corporation Method for designing integrated circuits employing a partitioned hierarchical design flow and an apparatus employing the method
US8341573B2 (en) * 2010-10-15 2012-12-25 Lsi Corporation Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flow
US8458637B2 (en) * 2010-10-22 2013-06-04 International Business Machines Corporation Implementing enhanced RLM connectivity on a hierarchical design with top level pipeline registers
US8589846B2 (en) * 2011-12-02 2013-11-19 Synopsys, Inc. Modeling transition effects for circuit optimization
US8522179B1 (en) * 2012-02-06 2013-08-27 Lsi Corporation System and method for managing timing margin in a hierarchical integrated circuit design process
US8990445B2 (en) * 2012-03-05 2015-03-24 Mediatek Inc. Control chip for communicating with wired connection interface by using one configurable pin selectively serving as input pin or output pin
US8578304B1 (en) * 2012-07-26 2013-11-05 International Business Machines Corporation Implementing mulitple mask lithography timing variation mitigation
US20140156233A1 (en) * 2012-12-03 2014-06-05 Can Wang Method and apparatus for electronic circuit simulation
US8977998B1 (en) * 2013-02-21 2015-03-10 Altera Corporation Timing analysis with end-of-life pessimism removal
US8713502B1 (en) 2013-02-26 2014-04-29 International Business Machines Corporation Methods and systems to reduce a number of simulations in a timing analysis
TW201523312A (zh) * 2013-09-06 2015-06-16 Blue Pearl Software Inc 使用者灰色單元
US9940431B2 (en) 2016-01-07 2018-04-10 International Business Machines Corporation Accurate statistical timing for boundary gates of hierarchical timing models
JP2017167732A (ja) * 2016-03-15 2017-09-21 株式会社東芝 回路設計検証装置およびプログラム
US10223493B1 (en) 2016-06-28 2019-03-05 Altera Corporation Dynamic tag allocation for clock reconvergence pessimism removal
US9977850B2 (en) * 2016-07-12 2018-05-22 International Business Machines Corporation Callback based constraint processing for clock domain independence
US10394987B2 (en) * 2017-03-21 2019-08-27 International Business Machines Corporation Adaptive bug-search depth for simple and deep counterexamples
US11176293B1 (en) * 2018-03-07 2021-11-16 Synopsys, Inc. Method and system for emulation clock tree reduction
US10747925B1 (en) * 2019-01-25 2020-08-18 International Business Machines Corporation Variable accuracy incremental timing analysis
US11188696B1 (en) * 2019-04-15 2021-11-30 Cadence Design Systems, Inc. Method, system, and product for deferred merge based method for graph based analysis pessimism reduction
US10831954B1 (en) 2019-10-29 2020-11-10 International Business Machines Corporation Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs
US10891412B1 (en) 2020-02-13 2021-01-12 International Business Machines Corporation Offline analysis of hierarchical electronic design automation derived data

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Also Published As

Publication number Publication date
US6928630B2 (en) 2005-08-09
WO2003050724A2 (en) 2003-06-19
JP2005512236A (ja) 2005-04-28
WO2003050725A3 (en) 2004-04-08
US20030120474A1 (en) 2003-06-26
WO2003050724A3 (en) 2004-06-10
EP1451731A2 (en) 2004-09-01
AU2002351253A1 (en) 2003-06-23
US7356451B2 (en) 2008-04-08
EP1451730A2 (en) 2004-09-01
WO2003050725A2 (en) 2003-06-19
US20030121013A1 (en) 2003-06-26
JP2005512237A (ja) 2005-04-28

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase