JP2005512236A - タイミンググラフ縮小によるタイミングモデル抽出 - Google Patents

タイミンググラフ縮小によるタイミングモデル抽出 Download PDF

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JP2005512236A
JP2005512236A JP2003551710A JP2003551710A JP2005512236A JP 2005512236 A JP2005512236 A JP 2005512236A JP 2003551710 A JP2003551710 A JP 2003551710A JP 2003551710 A JP2003551710 A JP 2003551710A JP 2005512236 A JP2005512236 A JP 2005512236A
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timing
model
graph
pin
arc
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JP2005512236A5 (enExample
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チョ ウー ムーン，
ハリシュ クリプラニ，
クリシュナ プラサド ベルクヘール，
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カデンス デザイン システムズ， インコーポレイテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/08—Intellectual property [IP] blocks or IP cores

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Stored Programmes (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP2003551710A 2001-12-07 2002-12-06 タイミンググラフ縮小によるタイミングモデル抽出 Pending JP2005512236A (ja)

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Application Number Priority Date Filing Date Title
US33923501P 2001-12-07 2001-12-07
PCT/US2002/038799 WO2003050724A2 (en) 2001-12-07 2002-12-06 Timing model extraction by timing graph reduction

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JP2005512236A5 JP2005512236A5 (enExample) 2005-12-22

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JP2003551710A Pending JP2005512236A (ja) 2001-12-07 2002-12-06 タイミンググラフ縮小によるタイミングモデル抽出
JP2003551711A Pending JP2005512237A (ja) 2001-12-07 2002-12-06 タイミングモデル抽出のためのアサーションハンドリング

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US (2) US7356451B2 (enExample)
EP (2) EP1451730A2 (enExample)
JP (2) JP2005512236A (enExample)
AU (2) AU2002359605A1 (enExample)
WO (2) WO2003050724A2 (enExample)

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US20050091555A1 (en) * 2003-10-27 2005-04-28 Tong Xiao Abstraction generation for hierarchical timing analysis using implicity connectivity graph derived from domain propagation
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US20080115099A1 (en) * 2006-11-15 2008-05-15 Priyadarsan Patra Spatial curvature for multiple objective routing
US7926011B1 (en) * 2007-01-10 2011-04-12 Cadence Design Systems, Inc. System and method of generating hierarchical block-level timing constraints from chip-level timing constraints
US8365113B1 (en) * 2007-01-10 2013-01-29 Cadence Design Systems, Inc. Flow methodology for single pass parallel hierarchical timing closure of integrated circuit designs
US8977995B1 (en) * 2007-01-10 2015-03-10 Cadence Design Systems, Inc. Timing budgeting of nested partitions for hierarchical integrated circuit designs
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US8239798B1 (en) * 2007-08-03 2012-08-07 Cadence Design Systems, Inc. Methods, systems, and apparatus for variation aware extracted timing models
US7962872B2 (en) * 2007-12-04 2011-06-14 Texas Instruments Incorporated Timing analysis when integrating multiple circuit blocks while balancing resource requirements and accuracy
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US8341573B2 (en) * 2010-10-15 2012-12-25 Lsi Corporation Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flow
US8458637B2 (en) * 2010-10-22 2013-06-04 International Business Machines Corporation Implementing enhanced RLM connectivity on a hierarchical design with top level pipeline registers
US8589846B2 (en) * 2011-12-02 2013-11-19 Synopsys, Inc. Modeling transition effects for circuit optimization
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US8990445B2 (en) * 2012-03-05 2015-03-24 Mediatek Inc. Control chip for communicating with wired connection interface by using one configurable pin selectively serving as input pin or output pin
US8578304B1 (en) * 2012-07-26 2013-11-05 International Business Machines Corporation Implementing mulitple mask lithography timing variation mitigation
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US8977998B1 (en) * 2013-02-21 2015-03-10 Altera Corporation Timing analysis with end-of-life pessimism removal
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JP2017167732A (ja) * 2016-03-15 2017-09-21 株式会社東芝 回路設計検証装置およびプログラム
US10223493B1 (en) 2016-06-28 2019-03-05 Altera Corporation Dynamic tag allocation for clock reconvergence pessimism removal
US9977850B2 (en) * 2016-07-12 2018-05-22 International Business Machines Corporation Callback based constraint processing for clock domain independence
US10394987B2 (en) * 2017-03-21 2019-08-27 International Business Machines Corporation Adaptive bug-search depth for simple and deep counterexamples
US11176293B1 (en) * 2018-03-07 2021-11-16 Synopsys, Inc. Method and system for emulation clock tree reduction
US10747925B1 (en) * 2019-01-25 2020-08-18 International Business Machines Corporation Variable accuracy incremental timing analysis
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008146142A (ja) * 2006-12-06 2008-06-26 Nec Corp 電子回路用プリント基板の設計方法とシステム

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US6928630B2 (en) 2005-08-09
WO2003050724A2 (en) 2003-06-19
WO2003050725A3 (en) 2004-04-08
US20030120474A1 (en) 2003-06-26
WO2003050724A3 (en) 2004-06-10
EP1451731A2 (en) 2004-09-01
AU2002359605A1 (en) 2003-06-23
AU2002351253A1 (en) 2003-06-23
US7356451B2 (en) 2008-04-08
EP1451730A2 (en) 2004-09-01
WO2003050725A2 (en) 2003-06-19
US20030121013A1 (en) 2003-06-26
JP2005512237A (ja) 2005-04-28

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