JP2005505856A5 - - Google Patents

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Publication number
JP2005505856A5
JP2005505856A5 JP2003536900A JP2003536900A JP2005505856A5 JP 2005505856 A5 JP2005505856 A5 JP 2005505856A5 JP 2003536900 A JP2003536900 A JP 2003536900A JP 2003536900 A JP2003536900 A JP 2003536900A JP 2005505856 A5 JP2005505856 A5 JP 2005505856A5
Authority
JP
Japan
Prior art keywords
packet
buffer circuit
command
bus
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2003536900A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005505856A (ja
JP4391820B2 (ja
Filing date
Publication date
Priority claimed from US10/093,146 external-priority patent/US6725297B1/en
Application filed filed Critical
Priority claimed from PCT/US2002/026884 external-priority patent/WO2003034240A1/en
Publication of JP2005505856A publication Critical patent/JP2005505856A/ja
Publication of JP2005505856A5 publication Critical patent/JP2005505856A5/ja
Application granted granted Critical
Publication of JP4391820B2 publication Critical patent/JP4391820B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2003536900A 2001-10-15 2002-08-22 コンピュータシステムのｉ／ｏノードのための周辺インターフェイス回路 Expired - Fee Related JP4391820B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US97853401A 2001-10-15 2001-10-15
US10/093,146 US6725297B1 (en) 2001-10-15 2002-03-07 Peripheral interface circuit for an I/O node of a computer system
PCT/US2002/026884 WO2003034240A1 (en) 2001-10-15 2002-08-22 A peripheral interface circuit for an i/o node of a computer system

Publications (3)

Publication Number Publication Date
JP2005505856A JP2005505856A (ja) 2005-02-24
JP2005505856A5 true JP2005505856A5 (enExample) 2006-03-09
JP4391820B2 JP4391820B2 (ja) 2009-12-24

Family

ID=26787193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003536900A Expired - Fee Related JP4391820B2 (ja) 2001-10-15 2002-08-22 コンピュータシステムのｉ／ｏノードのための周辺インターフェイス回路

Country Status (6)

Country Link
EP (1) EP1436709B1 (enExample)
JP (1) JP4391820B2 (enExample)
CN (1) CN100524264C (enExample)
DE (1) DE60211006T2 (enExample)
TW (1) TWI225989B (enExample)
WO (1) WO2003034240A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6839784B1 (en) * 2001-10-15 2005-01-04 Advanced Micro Devices, Inc. Control unit of an I/O node for a computer system including a plurality of scheduler units each including a plurality of buffers each corresponding to a respective virtual channel
WO2004081805A1 (en) * 2003-03-10 2004-09-23 Uhs Systems Pty Ltd A dedicated communications system and interface
US7881303B2 (en) * 2006-12-13 2011-02-01 GlobalFoundries, Inc. Command packet packing to mitigate CRC overhead
JP5125885B2 (ja) * 2008-08-26 2013-01-23 セイコーエプソン株式会社 データ入出力装置
US11360920B2 (en) * 2020-08-31 2022-06-14 Micron Technology, Inc. Mapping high-speed, point-to-point interface channels to packet virtual channels

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5187780A (en) * 1989-04-07 1993-02-16 Digital Equipment Corporation Dual-path computer interconnect system with zone manager for packet memory
CA2075835C (en) * 1991-03-04 2001-05-08 Jayesh M. Patel Data bus interface apparatus
US5983291A (en) * 1996-09-24 1999-11-09 Cirrus Logic, Inc. System for storing each of streams of data bits corresponding from a separator thereby allowing an input port accommodating plurality of data frame sub-functions concurrently

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