JP4391820B2 - コンピュータシステムのｉ／ｏノードのための周辺インターフェイス回路 - Google Patents

コンピュータシステムのｉ／ｏノードのための周辺インターフェイス回路 Download PDF

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Publication number
JP4391820B2
JP4391820B2 JP2003536900A JP2003536900A JP4391820B2 JP 4391820 B2 JP4391820 B2 JP 4391820B2 JP 2003536900 A JP2003536900 A JP 2003536900A JP 2003536900 A JP2003536900 A JP 2003536900A JP 4391820 B2 JP4391820 B2 JP 4391820B2
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Japan
Prior art keywords
packet
bus
command
posted
peripheral
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Expired - Fee Related
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JP2003536900A
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English (en)
Japanese (ja)
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JP2005505856A (ja
JP2005505856A5 (enExample
Inventor
アスカー ターシン
ディー． ヒューイット ラリー
ジー． チャンバーズ エリック
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication date
Priority claimed from US10/093,146 external-priority patent/US6725297B1/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2005505856A publication Critical patent/JP2005505856A/ja
Publication of JP2005505856A5 publication Critical patent/JP2005505856A5/ja
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Publication of JP4391820B2 publication Critical patent/JP4391820B2/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/128—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
JP2003536900A 2001-10-15 2002-08-22 コンピュータシステムのｉ／ｏノードのための周辺インターフェイス回路 Expired - Fee Related JP4391820B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US97853401A 2001-10-15 2001-10-15
US10/093,146 US6725297B1 (en) 2001-10-15 2002-03-07 Peripheral interface circuit for an I/O node of a computer system
PCT/US2002/026884 WO2003034240A1 (en) 2001-10-15 2002-08-22 A peripheral interface circuit for an i/o node of a computer system

Publications (3)

Publication Number Publication Date
JP2005505856A JP2005505856A (ja) 2005-02-24
JP2005505856A5 JP2005505856A5 (enExample) 2006-03-09
JP4391820B2 true JP4391820B2 (ja) 2009-12-24

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ID=26787193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003536900A Expired - Fee Related JP4391820B2 (ja) 2001-10-15 2002-08-22 コンピュータシステムのｉ／ｏノードのための周辺インターフェイス回路

Country Status (6)

Country Link
EP (1) EP1436709B1 (enExample)
JP (1) JP4391820B2 (enExample)
CN (1) CN100524264C (enExample)
DE (1) DE60211006T2 (enExample)
TW (1) TWI225989B (enExample)
WO (1) WO2003034240A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6839784B1 (en) * 2001-10-15 2005-01-04 Advanced Micro Devices, Inc. Control unit of an I/O node for a computer system including a plurality of scheduler units each including a plurality of buffers each corresponding to a respective virtual channel
WO2004081805A1 (en) * 2003-03-10 2004-09-23 Uhs Systems Pty Ltd A dedicated communications system and interface
US7881303B2 (en) * 2006-12-13 2011-02-01 GlobalFoundries, Inc. Command packet packing to mitigate CRC overhead
JP5125885B2 (ja) * 2008-08-26 2013-01-23 セイコーエプソン株式会社 データ入出力装置
US11360920B2 (en) * 2020-08-31 2022-06-14 Micron Technology, Inc. Mapping high-speed, point-to-point interface channels to packet virtual channels

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5187780A (en) * 1989-04-07 1993-02-16 Digital Equipment Corporation Dual-path computer interconnect system with zone manager for packet memory
CA2075835C (en) * 1991-03-04 2001-05-08 Jayesh M. Patel Data bus interface apparatus
US5983291A (en) * 1996-09-24 1999-11-09 Cirrus Logic, Inc. System for storing each of streams of data bits corresponding from a separator thereby allowing an input port accommodating plurality of data frame sub-functions concurrently

Also Published As

Publication number Publication date
CN100524264C (zh) 2009-08-05
JP2005505856A (ja) 2005-02-24
EP1436709B1 (en) 2006-04-26
WO2003034240A1 (en) 2003-04-24
TWI225989B (en) 2005-01-01
DE60211006T2 (de) 2006-11-30
EP1436709A1 (en) 2004-07-14
DE60211006D1 (de) 2006-06-01
CN1639698A (zh) 2005-07-13

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