JP2005347496A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

Info

Publication number
JP2005347496A
JP2005347496A JP2004165177A JP2004165177A JP2005347496A JP 2005347496 A JP2005347496 A JP 2005347496A JP 2004165177 A JP2004165177 A JP 2004165177A JP 2004165177 A JP2004165177 A JP 2004165177A JP 2005347496 A JP2005347496 A JP 2005347496A
Authority
JP
Japan
Prior art keywords
semiconductor device
circuit board
manufacturing
substrate
sheet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004165177A
Other languages
Japanese (ja)
Inventor
Yasutake Yaguchi
安武 矢口
Takashi Yui
油井　　隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2004165177A priority Critical patent/JP2005347496A/en
Publication of JP2005347496A publication Critical patent/JP2005347496A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which can improve yield of the semiconductor device by reducing the occurrence of a crack in a sheet substrate as much as possible. <P>SOLUTION: The method of manufacturing the semiconductor device includes the steps of arranging a semiconductor element at a non-mounting surface side and performing a sealing resin at the semiconductor element side of a circuit board having an external terminal electrode formed on the other surface. The method further includes the step of forming a plurality of crack preventing vias 18 at a predetermined interval at the outside edge 11a (14a) of the circuit board 2 in the sheet substrate 11, when a plurality of insulating sheet layers 14 are superposed and wiring patterns are connected to each other via a conduction via 16 in the sheet substrate 11 in which the wiring patterns 19 are arranged between the insulating sheet layers to form the circuit board 2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、回路基板を用いて構成される半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device configured using a circuit board.

近年、半導体装置の高密度化・薄型化への要求が強くなっている。そのため、回路基板が用いられるＢＧＡ（ＢＡＬＬ ＧＬＩＤ ＡＬＬＡＹ）タイプの半導体装置においては、回路基板の強度が低くなり基板割れが発生しやすくなるが、回路基板自体を薄くすることで、半導体装置全体の薄型化を図っている。   In recent years, there has been a strong demand for higher density and thinner semiconductor devices. For this reason, in a BGA (BALL GLID ALLY) type semiconductor device in which a circuit board is used, the strength of the circuit board is reduced and the substrate is likely to be cracked. We are trying to make it.

なお、このＢＧＡタイプの半導体装置は、回路基板の一方の表面に半導体素子が配置されるとともに他方の表面（実装面側）にボール状の外部端子電極が碁盤目のように（格子の交差点位置に）配置されたものである。   In this BGA type semiconductor device, a semiconductor element is arranged on one surface of a circuit board, and ball-like external terminal electrodes are arranged on the other surface (mounting surface side) like a grid (at the intersection of lattices). ).

以下、この回路基板が用いられた半導体装置の製造方法について説明する。
この半導体装置の製造工程については、大きく分けて、複数個の回路基板をシート基板に纏めて形成する工程と、このシート基板に形成された各回路基板に半導体素子を配置する工程と、この半導体素子が配置された表面に封止樹脂を施す封止工程と、この封止樹脂が施された回路基板の他方の表面に外部端子電極を形成してシート基板に複数個の半導体装置を形成する工程と、このシート基板に形成された複数個の半導体装置を１個ずつ切断する切断工程とから構成されている（例えば、特許文献１参照）。 A method for manufacturing a semiconductor device using this circuit board will be described below.
The manufacturing process of this semiconductor device is roughly divided into a step of forming a plurality of circuit boards together on a sheet substrate, a step of arranging a semiconductor element on each circuit substrate formed on the sheet substrate, and this semiconductor A sealing step of applying a sealing resin to the surface on which the element is arranged, and forming a plurality of semiconductor devices on the sheet substrate by forming external terminal electrodes on the other surface of the circuit board on which the sealing resin is applied It comprises a process and a cutting process for cutting a plurality of semiconductor devices formed on the sheet substrate one by one (see, for example, Patent Document 1).

そして、上記シート基板は、絶縁シート層と配線層とが交互に重ねられて形成されたもので、各配線層同士は絶縁シート層に設けられるビアと呼ばれる金属で電気的導通が行われている。すなわち、各回路基板の所定位置には、複数個のビアホールが形成されるとともに、これら各ビアホールに導電性金属が充填されてビアが形成される。
特開平１１−２１９９５９号公報 The sheet substrate is formed by alternately stacking insulating sheet layers and wiring layers, and each wiring layer is electrically connected with a metal called a via provided in the insulating sheet layer. . That is, a plurality of via holes are formed at predetermined positions on each circuit board, and vias are formed by filling each via hole with a conductive metal.
Japanese Patent Laid-Open No. 11-219959

ところで、上述した半導体装置の製造方法によると、回路基板を製造する工程から最終的に半導体素子が載置された回路基板ごとに、すなわち半導体装置ごとに切断するまでの各工程においておよび各工程間を搬送させる間に、シート基板に割れが発生する可能性がある。工程間の搬送では、シート基板の外側縁部は工程間の搬送の際に掴みしろになることから負荷がかかるため、ある工程よりも前の搬送の際に発生した基板割れが、ある工程よりも後で進展する場合もある。外側縁部で発生した割れが回路基板に達すると、歩留まりが低下してしまう。   By the way, according to the manufacturing method of the semiconductor device described above, in each process from the process of manufacturing the circuit board to each circuit board on which the semiconductor element is finally mounted, that is, for each semiconductor device, and between the processes. There is a possibility that the sheet substrate is cracked while the sheet is being conveyed. In conveyance between processes, since the outer edge of the sheet substrate becomes gripped during conveyance between processes, a load is applied, so that a substrate crack that occurred during conveyance before a certain process is more than in a certain process May evolve later. When the crack generated at the outer edge reaches the circuit board, the yield decreases.

特に、樹脂の封止工程においては、シート基板の外側縁部での割れが多く発生する。なぜなら、トランスファー工法により封止樹脂を施す際は、上下の金型で基板の外側縁部を挟むため、当該外側縁部で基板割れが発生しやすく、また封止工程よりも前の工程で発生した基板の割れが進展しやすくなるからである。   In particular, in the resin sealing process, many cracks occur at the outer edge of the sheet substrate. This is because when the sealing resin is applied by the transfer method, the outer edge of the substrate is sandwiched between the upper and lower molds, so that the substrate is likely to crack at the outer edge, and it occurs in the process prior to the sealing process. It is because the crack of the board | substrate which carried out becomes easy to progress.

そこで、上記課題を解決するため、本発明は、シート基板での割れ発生をできるだけ少なくして、半導体装置の歩留まりを向上させ得る半導体装置の製造方法を提供することを目的とする。   Accordingly, in order to solve the above-described problems, an object of the present invention is to provide a method for manufacturing a semiconductor device that can improve the yield of the semiconductor device by reducing the occurrence of cracks in the sheet substrate as much as possible.

上記課題を解決するため、本発明の請求項１に係る半導体装置の製造方法は、一方の表面に半導体素子が配置されるとともに他方の表面に外部端子電極が形成された回路基板の上記半導体素子側に封止樹脂が施されてなる半導体装置の製造方法であって、
絶縁シート層が複数枚重ねられるとともにこれら絶縁シート層間に配線層が配置されてなるシート基板に、上記配線層同士を導通用ビアを介して接続することにより回路基板を形成する際に、
上記シート基板における回路基板の外側縁部に、所定間隔おきに割れ防止用穴を複数個形成する方法である。 In order to solve the above-described problem, a method of manufacturing a semiconductor device according to claim 1 of the present invention provides a semiconductor device on a circuit board in which a semiconductor element is disposed on one surface and an external terminal electrode is formed on the other surface. A method for manufacturing a semiconductor device in which a sealing resin is applied to the side,
When forming a circuit board by connecting a plurality of insulating sheet layers and connecting the wiring layers via conductive vias to a sheet substrate in which wiring layers are arranged between the insulating sheet layers,
In this method, a plurality of crack prevention holes are formed at predetermined intervals on the outer edge of the circuit board in the sheet substrate.

また、請求項２に係る半導体装置の製造方法は、請求項１に記載の製造方法において、
割れ防止用穴を一列にまたは千鳥状に配置する方法である。
さらに、請求項３に係る半導体装置の製造方法は、一方の表面に半導体素子が配置されるとともに他方の表面に外部端子電極が形成された回路基板の上記半導体素子側に封止樹脂が施されてなる半導体装置の製造方法であって、
絶縁シート層が複数枚重ねられるとともにこれら絶縁シート層間に配線層が配置されてなるシート基板に、上記配線層同士を導通用ビアを介して接続することにより回路基板を形成する際に、
上記シート基板における回路基板の外側縁部に、所定間隔おきに割れ防止用ビアを複数個形成する方法である。 A method for manufacturing a semiconductor device according to claim 2 is the method according to claim 1,
This is a method of arranging crack prevention holes in a row or in a staggered manner.
Further, in the method of manufacturing a semiconductor device according to claim 3, a sealing resin is applied to the semiconductor element side of the circuit board in which the semiconductor element is disposed on one surface and the external terminal electrode is formed on the other surface. A method for manufacturing a semiconductor device comprising:
When forming a circuit board by connecting a plurality of insulating sheet layers and connecting the wiring layers via conductive vias to a sheet substrate in which wiring layers are arranged between the insulating sheet layers,
In this method, a plurality of crack prevention vias are formed at predetermined intervals on the outer edge of the circuit board in the sheet substrate.

また、請求項４に係る半導体装置の製造方法は、請求項３に記載の製造方法において、
割れ防止用ビアを一列にまたは千鳥状に配置する方法である。 A method for manufacturing a semiconductor device according to claim 4 is the method for manufacturing a semiconductor device according to claim 3,
This is a method of arranging crack prevention vias in a row or in a staggered manner.

上記の各構成によると、シート基板における回路基板の外側縁部に、割れ防止用穴または割れ防止用ビアを形成したので、半導体装置の製造途中においてシート基板の外側縁部を把持する際に、その把持力により、たとえ基板に割れが発生したとしても、割れ防止用穴または割れ防止用ビアの部分で、その割れの進展を止めることができ、したがって基板の外側縁部に発生した割れが回路基板に到達するのが防止されるので、半導体装置の歩留まりを向上させることができる。   According to each of the above configurations, since the crack prevention hole or the crack prevention via is formed in the outer edge portion of the circuit board in the sheet substrate, when gripping the outer edge portion of the sheet substrate during the manufacturing of the semiconductor device, Even if a crack occurs in the board due to the gripping force, the progress of the crack can be stopped at the part of the crack prevention hole or the crack prevention via. Since reaching to the substrate is prevented, the yield of the semiconductor device can be improved.

［実施の形態］
以下、本発明の実施の形態に係る半導体装置の製造方法を、図１〜図１８に基づき説明する。 [Embodiment]
A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to FIGS.

なお、本実施の形態における半導体装置としては、ＢＧＡタイプのものについて説明する。
図１および図２に示すように、このＢＧＡタイプの半導体装置１は、回路基板２の上面に半導体素子３が配置されるとともに、この半導体素子３と回路基板２とが金属細線４で接続され、そして半導体素子３が配置された非実装面（一方の表面）側に封止樹脂５にて封止されたもので、また回路基板２の実装面（他方の表面）側には、碁盤目のように（格子の交差点位置に）外部端子電極６が多数配置されたものである。 Note that a semiconductor device of the present embodiment will be described as a BGA type.
As shown in FIGS. 1 and 2, the BGA type semiconductor device 1 includes a semiconductor element 3 disposed on an upper surface of a circuit board 2, and the semiconductor element 3 and the circuit board 2 are connected by a thin metal wire 4. And the non-mounting surface (one surface) side where the semiconductor element 3 is arranged is sealed with the sealing resin 5, and the mounting surface (the other surface) side of the circuit board 2 is In this way, a large number of external terminal electrodes 6 are arranged (at the intersections of the lattices).

次に、上記半導体装置１の製造方法について説明する。
この半導体装置１の製造方法は、まず回路基板２を準備する工程から始まる。
この回路基板２は、図３に示すように、１枚のシート基板１１に纏めて複数個、例えば９個（３列×３列）形成される。なお、このシート基板１１を用いた半導体装置１の製造方法は、回路基板２のサイズが変わってもシート基板１１の大きさを変える必要がなく、したがって設備、治具などの変更を要しないため、製造コストおよび作業時間の低減化を図り得るものとして、近年、用いられている。 Next, a method for manufacturing the semiconductor device 1 will be described.
The manufacturing method of the semiconductor device 1 starts from a step of preparing the circuit board 2 first.
As shown in FIG. 3, a plurality of, for example, nine (3 rows × 3 rows) circuit boards 2 are formed on one sheet substrate 11. Note that the manufacturing method of the semiconductor device 1 using the sheet substrate 11 does not need to change the size of the sheet substrate 11 even if the size of the circuit board 2 changes, and therefore does not require changes in equipment, jigs, and the like. In recent years, it has been used as a means for reducing manufacturing cost and working time.

次に、シート基板１１を準備した後、図４に示すように、当該シート基板１１の非実装面側に、接着テープ１２を用いて、半導体素子３を熱および荷重を付加して接着する。
次に、図５に示すように、半導体素子３と回路基板２との電気的導通をとるために、半導体素子３側に形成されている電極パッドと回路基板２側に形成されている電極パッドとに亘って金属細線４を設ける（張る）。 Next, after preparing the sheet substrate 11, as shown in FIG. 4, the semiconductor element 3 is bonded to the non-mounting surface side of the sheet substrate 11 by applying heat and a load using the adhesive tape 12.
Next, as shown in FIG. 5, in order to establish electrical continuity between the semiconductor element 3 and the circuit board 2, an electrode pad formed on the semiconductor element 3 side and an electrode pad formed on the circuit board 2 side. A thin metal wire 4 is provided (stretched).

次に、図６の（ａ）および（ｂ）に示すように、半導体素子３および金属細線４の全体を覆うように封止樹脂５を施す。なお、この樹脂の封止工程は、上下の金型２１，２２でシート基板１１を挟み、そしてシート基板１１と上金型２１との隙間に封止用の樹脂５をプランジャ２３により圧力をかけて注入し、熱により硬化させるというトランスファー工法が用いられる。図７に、シート基板１１上に封止樹脂５が施された状態の断面図を示す。   Next, as shown in FIGS. 6A and 6B, a sealing resin 5 is applied so as to cover the entire semiconductor element 3 and the fine metal wires 4. In this resin sealing step, the sheet substrate 11 is sandwiched between the upper and lower molds 21, 22, and the sealing resin 5 is applied to the gap between the sheet substrate 11 and the upper mold 21 by the plunger 23. The transfer method of injecting and curing by heat is used. FIG. 7 is a cross-sectional view showing a state where the sealing resin 5 is applied on the sheet substrate 11.

次に、図８に示すように、各半導体素子３に対応する封止樹脂５の上面に、マーキングツール２４を用いて、所定のマーキングを行なう。なお、図８では、例としてインクマーキング工法を示しており、その他、レーザーマーキング工法などを用いることができる。   Next, as shown in FIG. 8, predetermined marking is performed on the upper surface of the sealing resin 5 corresponding to each semiconductor element 3 using a marking tool 24. In addition, in FIG. 8, the ink marking construction method is shown as an example, and laser marking construction method etc. can be used in addition.

次に、図９に示すように、シート基板１１に形成された回路基板２の実装面側に、碁盤目（格子の各交差点位置）のように外部端子電極６を複数個形成し、最後に、図１０に示すように、高速回転するダイシングブレード２５で、シート基板を半導体素子３、すなわち回路基板２ごとに切断することにより、図１に示すような半導体装置１が得られる。   Next, as shown in FIG. 9, a plurality of external terminal electrodes 6 are formed on the mounting surface side of the circuit board 2 formed on the sheet substrate 11 like a grid (at each intersection position of the lattice), and finally As shown in FIG. 10, the semiconductor device 1 as shown in FIG. 1 is obtained by cutting the sheet substrate for each semiconductor element 3, that is, the circuit substrate 2, with a dicing blade 25 that rotates at high speed.

次に、回路基板２を構成するシート基板１１の製造方法、すなわち製造工程について、詳しく説明する。
回路基板２を構成するシート基板１１は、絶縁シート層（後述するグリーンシートである）と配線層（後述する配線パターンで、配線部ともいう）とが交互に重ねられて形成されており、各配線層は絶縁シート層に設けられたビアと呼ばれる導電性物質（金属）で電気的導通が行われている。このビアは、半導体素子３と外部端子電極６との電気的導通をとるためのものである。 Next, a manufacturing method of the sheet substrate 11 constituting the circuit board 2, that is, a manufacturing process will be described in detail.
The sheet substrate 11 constituting the circuit board 2 is formed by alternately stacking insulating sheet layers (which are green sheets to be described later) and wiring layers (wiring patterns to be described later, also referred to as wiring portions). The wiring layer is electrically connected with a conductive material (metal) called a via provided in the insulating sheet layer. This via is for establishing electrical continuity between the semiconductor element 3 and the external terminal electrode 6.

ここでは、シート基板１１として、セラミック基板を用いた場合の製造工程について説明する。
まず、図１１に示すように、ペースト状になった絶縁性材料１３をドクターブレード法により、ローラ３１により駆動されるベルト３２上に所定厚さでもって引き出して、絶縁シート層となるグリーンシート１４を形成し、そして所定の大きさに切断して必要枚数分だけを準備する。 Here, a manufacturing process when a ceramic substrate is used as the sheet substrate 11 will be described.
First, as shown in FIG. 11, the paste-like insulating material 13 is drawn out with a predetermined thickness on a belt 32 driven by a roller 31 by a doctor blade method, and the green sheet 14 serving as an insulating sheet layer is obtained. And cut to a predetermined size to prepare only the required number of sheets.

次に、図１２および図１３に示すように、所定の大きさに切断されたグリーンシート１４上に且つ各回路基板２における電気的導通位置に対応してパンチングによりビアホール（ビア用穴）１５をそれぞれ複数箇所に形成し、そしてこれらビアホール１５にモリブデンなどの導電性物質を充填して、各絶縁シート層１４間での電気的導通をとるための導通用ビア１６を形成する。   Next, as shown in FIGS. 12 and 13, via holes (via holes) 15 are punched on the green sheet 14 cut to a predetermined size and corresponding to the electrical conduction positions in each circuit board 2. Each via hole 15 is filled with a conductive material such as molybdenum to form conductive vias 16 for electrical conduction between the insulating sheet layers 14.

そして、このとき、グリーンシート１４の回路基板２の外周縁部（端材部ともいう）１４ａに、例えば上記ビアホール１５と同様のビアホール１７を、全周に亘って且つ所定間隔おきに複数個形成するとともに、例えばモリブデンなどの導電性物質を充填して割れ防止用ビア１８を形成する。   At this time, for example, a plurality of via holes 17 similar to the via holes 15 are formed on the outer peripheral edge portion (also referred to as end material portion) 14a of the circuit board 2 of the green sheet 14 over the entire circumference and at predetermined intervals. At the same time, a crack prevention via 18 is formed by filling a conductive material such as molybdenum.

次に、図１４および図１５に示すように、各グリーンシート１４上に配線層としての配線パターン１９を印刷する。
次に、図１６に示すように、配線パターン１９が印刷された複数のグリーンシート１４を積層し、そして焼成を行うことにより、複数の回路基板２が形成されたシート基板１１が完成する。図１６においては、互いに上下に隣接するグリーンシート１４の外側縁部１４ａに形成されるビアホール１７（割れ防止用ビア１８）の位置が、水平方向で、例えば外周方向で少しずらされている。 Next, as shown in FIGS. 14 and 15, a wiring pattern 19 as a wiring layer is printed on each green sheet 14.
Next, as shown in FIG. 16, a plurality of green sheets 14 printed with a wiring pattern 19 are stacked and fired to complete a sheet substrate 11 on which a plurality of circuit boards 2 are formed. In FIG. 16, the positions of the via holes 17 (breaking prevention vias 18) formed in the outer edge portion 14 a of the green sheet 14 that are adjacent to each other vertically are slightly shifted in the horizontal direction, for example, in the outer circumferential direction.

なお、上記ビア１６，１８および配線パターン１９の製造工程においては、各層ごとに所定パターンが形成された印刷マスクを用意してあり、各層ごとに一括して配線パターン１９を形成することができる。   In the manufacturing process of the vias 16 and 18 and the wiring pattern 19, a printing mask having a predetermined pattern formed for each layer is prepared, and the wiring pattern 19 can be formed for each layer in a lump.

ここで、具体的な寸法例について説明しておく。
シート基板１１の大きさについては、縦および横をそれぞれ５０．８ｍｍに、回路基板２については、縦および横をそれぞれ１３ｍｍにするとともに、１個のシート基板１１に９個の回路基板２を形成した。 Here, a specific example of dimensions will be described.
The size of the sheet substrate 11 is 50.8 mm in length and width, and the circuit board 2 is 13 mm in length and width, and nine circuit boards 2 are formed on one sheet substrate 11. did.

また、シート基板１１の外側縁部１１ａ（１４ａ）に、９個の回路基板２の全周囲を囲むようにビアホール１７（割れ防止用ビア１８）を配置した。
なお、ビアホール１７の間隔はおよそ５ｍｍにするとともにその穴径（直径）を約８０μｍとした。 In addition, via holes 17 (breaking prevention vias 18) are arranged on the outer edge 11 a (14 a) of the sheet substrate 11 so as to surround the entire periphery of the nine circuit boards 2.
The interval between the via holes 17 was about 5 mm, and the hole diameter (diameter) was about 80 μm.

そして、ビアホール１７すなわち割れ防止用ビア１８がその外側縁部１１ａに配置されたシート基板１１を１００枚用いて半導体装置１を製造した。
なお、半導体装置１の製造を行なう前に、基板割れがないことを確認した。 Then, the semiconductor device 1 was manufactured using 100 sheet substrates 11 in which the via holes 17, that is, the crack prevention vias 18 were arranged on the outer edge portion 11 a.
In addition, before manufacturing the semiconductor device 1, it confirmed that there was no board | substrate crack.

そして、半導体装置１の製造工程ごとに、外側縁部１１ａに基板割れが発生した基板の個数を調査した結果、樹脂の封止工程までの搬送時においては、２枚であったが、全て割れ防止用ビア１８でその進展が止まっていた。   And as a result of investigating the number of substrates in which the substrate crack occurred in the outer edge portion 11a for each manufacturing process of the semiconductor device 1, it was found that the number of substrates was two at the time of transporting to the resin sealing step. The progress was stopped by the prevention via 18.

また、封止工程においては、上金型２１と下金型２２とでシート基板１１の外側縁部１１ａが挟まれるために基板割れが２８枚発生したが、そのうち１８枚については、割れ防止用ビア１８で割れの進展を止めることができた。なお、封止工程以降においては、外側縁部１１ａでの基板割れは発生しなかった。   In the sealing process, 28 substrate cracks occurred because the outer edge portion 11a of the sheet substrate 11 was sandwiched between the upper mold 21 and the lower mold 22, and 18 of them were for crack prevention. Via 18 was able to stop the cracking. In addition, the board | substrate crack in the outer edge part 11a did not generate | occur | produce after the sealing process.

このように、割れ防止用ビア１８を設けることにより、半導体装置１の製造工程で、シート基板１１の外側縁部１１ａに発生した割れが割れ防止用ビア１８で止まり（より、詳しく説明すれば、ビアホール１７の切欠きにより応力集中が起こり、すなわち割れがビアホールに集り、ここで割れが止まる）、回路基板２に到達するのを効果的に防止することができる。   As described above, by providing the crack prevention via 18, the crack generated in the outer edge portion 11 a of the sheet substrate 11 in the manufacturing process of the semiconductor device 1 stops at the crack prevention via 18 (more specifically, Stress concentration occurs due to the cutout of the via hole 17, that is, cracks gather in the via hole, and the crack stops here), and can effectively prevent the circuit board 2 from being reached.

また、割れ防止用ビア１８を設けることは、基板の製造工程において、殆ど、コストの増加を招くことはなかった。
また、今回、割れ防止用ビア１８の配置は、回路基板２を囲むように四角形状に沿って、すなわち各辺において一列に配置したが、図１７に示すように、千鳥状に配置してもよい。 Further, providing the crack prevention via 18 hardly caused an increase in cost in the manufacturing process of the substrate.
In addition, this time, the crack prevention vias 18 are arranged along a square shape so as to surround the circuit board 2, that is, arranged in a line on each side. However, as shown in FIG. Good.

また、上述した説明においては、シート基板１１の断面において、割れ防止用ビア１８の配置を、各層ごとにずらしたが、図１８に示すように、各層における割れ防止用ビア１８を同じ位置に配置してもよい。   In the above description, in the cross section of the sheet substrate 11, the arrangement of the crack prevention vias 18 is shifted for each layer. However, as shown in FIG. 18, the crack prevention vias 18 in each layer are arranged at the same position. May be.

さらに、基板の割れを防止するものとして割れ防止用ビア１８を形成したが、パンチングによりビアホール１７すなわち穴を開けた状態だけでも、上述したように、穴に応力が集中することから、基板の割れをこの穴で止めることができる。この意味で、この穴１７を割れ防止用ビアホール（割れ防止用穴）と呼ぶことができる。なお、この割れ防止用ビアホール内に充填する物質としては、金属以外のものであってもよい。   Furthermore, the crack prevention via 18 is formed to prevent the cracking of the substrate. However, as described above, the stress is concentrated in the hole even when the via hole 17 is formed by punching. Can be stopped at this hole. In this sense, the hole 17 can be referred to as a crack preventing via hole (a crack preventing hole). The material filled in the crack prevention via hole may be other than metal.

本発明に係る半導体装置の製造方法は、基板を用いたＢＧＡタイプの半導体装置の製造方法に有用であり、特に、近年の高密度実装を目的に基板の薄型化を進めている半導体素子積層型タイプのものに有効である。   The method of manufacturing a semiconductor device according to the present invention is useful for a method of manufacturing a BGA type semiconductor device using a substrate, and in particular, a semiconductor element stacked type in which the substrate is being made thinner for the purpose of recent high-density mounting. Valid for type.

本発明の実施の形態に係る製造方法にて得られる半導体装置の断面図である。It is sectional drawing of the semiconductor device obtained with the manufacturing method which concerns on embodiment of this invention. 同半導体装置を実装面側から見た斜視図である。It is the perspective view which looked at the same semiconductor device from the mounting surface side. 同半導体装置の製造工程を示すシート基板の平面図である。It is a top view of the sheet | seat board | substrate which shows the manufacturing process of the same semiconductor device. 同半導体装置の製造工程を示すシート基板の側面図である。It is a side view of the sheet substrate which shows the manufacturing process of the semiconductor device. 同半導体装置の製造工程を示すシート基板の側面図である。It is a side view of the sheet | seat board | substrate which shows the manufacturing process of the same semiconductor device. 同半導体装置の封止工程を示す断面図である。It is sectional drawing which shows the sealing process of the same semiconductor device. 同半導体装置の封止工程後の断面図である。It is sectional drawing after the sealing process of the same semiconductor device. 同半導体装置のマーキング工程を示す断面図である。It is sectional drawing which shows the marking process of the same semiconductor device. 同半導体装置の製造工程を示す断面図である。FIG. 26 is a cross-sectional view showing a manufacturing process of the same semiconductor device. 同半導体装置の分離工程を示す断面図である。It is sectional drawing which shows the isolation | separation process of the same semiconductor device. 同半導体装置におけるシート基板の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the sheet | seat board | substrate in the semiconductor device. 同半導体装置におけるシート基板の製造工程を示す平面図である。It is a top view which shows the manufacturing process of the sheet | seat board | substrate in the same semiconductor device. 図１２のＡ−Ａ断面図である。It is AA sectional drawing of FIG. 同半導体装置におけるシート基板の製造工程を示す平面図である。It is a top view which shows the manufacturing process of the sheet | seat board | substrate in the same semiconductor device. 図１４のＢ−Ｂ断面図である。It is BB sectional drawing of FIG. 同半導体装置におけるシート基板の製造工程を示す要部断面図である。It is principal part sectional drawing which shows the manufacturing process of the sheet | seat board | substrate in the semiconductor device. 同半導体装置におけるシート基板の製造工程を示す平面図である。It is a top view which shows the manufacturing process of the sheet | seat board | substrate in the same semiconductor device. 同半導体装置におけるシート基板の製造工程を示す要部断面図である。It is principal part sectional drawing which shows the manufacturing process of the sheet | seat board | substrate in the semiconductor device.

符号の説明Explanation of symbols

１ 半導体装置
２ 回路基板
３ 半導体素子
４ 金属細線
５ 封止樹脂
６ 外部端子電極
１１ シート基板
１１ａ 外側縁部
１４ グリーンシート
１４ａ 外側縁部
１５ ビアホール
１６ 導通用ビア
１７ ビアホール
１８ 割れ防止用ビア DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Circuit board 3 Semiconductor element 4 Metal fine wire 5 Sealing resin 6 External terminal electrode 11 Sheet substrate 11a Outer edge part 14 Green sheet 14a Outer edge part 15 Via hole 16 Conductive via 17 Via hole 18 Crack prevention via

Claims (4)

一方の表面に半導体素子が配置されるとともに他方の表面に外部端子電極が形成された回路基板の上記半導体素子側に封止樹脂が施されてなる半導体装置の製造方法であって、
絶縁シート層が複数枚重ねられるとともにこれら絶縁シート層間に配線層が配置されてなるシート基板に、上記配線層同士を導通用ビアを介して接続することにより回路基板を形成する際に、
上記シート基板における回路基板の外側縁部に、所定間隔おきに割れ防止用穴を複数個形成したことを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device in which a sealing resin is applied to the semiconductor element side of a circuit board in which a semiconductor element is disposed on one surface and an external terminal electrode is formed on the other surface,
When forming a circuit board by connecting a plurality of insulating sheet layers and connecting the wiring layers via conductive vias to a sheet substrate in which wiring layers are arranged between the insulating sheet layers,
A method of manufacturing a semiconductor device, wherein a plurality of crack prevention holes are formed at predetermined intervals on an outer edge of the circuit board in the sheet substrate. 割れ防止用穴を一列にまたは千鳥状に配置したことを特徴とする請求項１に記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the crack prevention holes are arranged in a row or in a staggered pattern. 一方の表面に半導体素子が配置されるとともに他方の表面に外部端子電極が形成された回路基板の上記半導体素子側に封止樹脂が施されてなる半導体装置の製造方法であって、
絶縁シート層が複数枚重ねられるとともにこれら絶縁シート層間に配線層が配置されてなるシート基板に、上記配線層同士を導通用ビアを介して接続することにより回路基板を形成する際に、
上記シート基板における回路基板の外側縁部に、所定間隔おきに割れ防止用ビアを複数個形成したことを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device in which a sealing resin is applied to the semiconductor element side of a circuit board in which a semiconductor element is disposed on one surface and an external terminal electrode is formed on the other surface,
When forming a circuit board by connecting a plurality of insulating sheet layers and connecting the wiring layers via conductive vias to a sheet substrate in which wiring layers are arranged between the insulating sheet layers,
A manufacturing method of a semiconductor device, wherein a plurality of crack prevention vias are formed at predetermined intervals on an outer edge portion of a circuit board in the sheet substrate. 割れ防止用ビアを一列にまたは千鳥状に配置したことを特徴とする請求項３に記載の半導体装置の製造方法。
4. The method of manufacturing a semiconductor device according to claim 3, wherein the crack prevention vias are arranged in a line or in a staggered pattern.
JP2004165177A 2004-06-03 2004-06-03 Method of manufacturing semiconductor device Pending JP2005347496A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004165177A JP2005347496A (en) 2004-06-03 2004-06-03 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004165177A JP2005347496A (en) 2004-06-03 2004-06-03 Method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JP2005347496A true JP2005347496A (en) 2005-12-15

Family

ID=35499590

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004165177A Pending JP2005347496A (en) 2004-06-03 2004-06-03 Method of manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2005347496A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100097739A1 (en) * 2008-10-17 2010-04-22 Prymak John D Capacitor Comprising Flex Crack Mitigation Voids

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100097739A1 (en) * 2008-10-17 2010-04-22 Prymak John D Capacitor Comprising Flex Crack Mitigation Voids
US8576537B2 (en) * 2008-10-17 2013-11-05 Kemet Electronics Corporation Capacitor comprising flex crack mitigation voids
US8713770B2 (en) 2008-10-17 2014-05-06 Kemet Electronics Corporation Capacitor comprising flex crack mitigation voids

Similar Documents

Publication Publication Date Title
JP2007095927A (en) Wiring board and its production method
JP4502130B2 (en) Manufacturing method of laminated electronic component
JP2005347496A (en) Method of manufacturing semiconductor device
WO2015182229A1 (en) Mother ceramic substrate, ceramic substrate, mother module component, module component, and manufacturing method for mother ceramic substrate
JP5738109B2 (en) Multiple wiring board
JP2005322659A (en) Wiring board, its manufacturing method and semiconductor device
WO2011152085A1 (en) Method for producing integrated substrate
JP4458974B2 (en) Multiple wiring board
JP2007243088A (en) Multilayer ceramic substrate and its manufacturing method
TWI576020B (en) Printed wiring board and manufacturing method thereof
JP4721926B2 (en) Multiple wiring board
TWI576021B (en) Printed wiring board and manufacturing method thereof
JP4057960B2 (en) Multiple wiring board
JP2006128363A (en) Multiple patterning wiring board and electronic device
JP2016143726A (en) Printed wiring board and method of manufacturing the same
JP3801843B2 (en) Wiring board manufacturing method
JP4549156B2 (en) Multiple wiring board
JP6119843B2 (en) Method for manufacturing multilayer inductor element, multilayer inductor element, and multilayer body
JP2005050935A (en) Multi-piece wiring board
JP4760253B2 (en) Manufacturing method of ceramic electronic component and fired ceramic mother substrate
JP2005136172A (en) Wiring substrate capable of being divided into a multitude of pieces
JP2006041310A (en) Multi-pattern wiring board
JP2005050936A (en) Multi-piece wiring board
JP2005277078A (en) Multi-patterned wiring board
WO2014155810A1 (en) Laminated-inductor-element manufacturing method, laminated inductor element, and laminate