JP2005316145A - Display signal processing circuit and liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display signal processing circuit for simply displaying a plurality of pictures without scaling a video signal in displaying the plurality of pictures on one display screen. <P>SOLUTION: The display signal display processing circuit 10 has a timing controller 30 and a changeover switch 13. The timing controller 30 outputs a switching signal SSWW and a clock signal GRCLK on the basis of a horizontal synchronizing signal HD obtained from the video signal having one horizontal scanning period possessing a video period including a video signal and a non-video period including the horizontal synchronizing signal. The switching signal SSWW indicates the timing at which the non-video period and the video period change over. The clock signal GRCLK indicates the generation timing of the image signal. The changeover switch 13 receives the image signal generated according to the clock signal GRCLK and the video signal, selects the image signal in the non-video period according to the switching signal SSWW and selects the video signal included in the video signal in the video period. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display signal processing circuit used for displaying a plurality of screens on one display unit, and is used, for example, in a liquid crystal display device.

  In recent years, when a video signal (for example, a TV signal) and an image signal (for example, a navigation signal or a menu screen signal) are displayed on a liquid crystal display panel, there is a demand for simultaneously displaying two screens.

  The video signal is an analog signal arranged in time series on the premise of horizontal scanning / vertical scanning, and can be sequentially displayed on the display screen in the case of a single screen display. For this, temporal operation (compression) is required. For this reason, in the two-screen display, the video signal is usually digitized, and the digitized video signal is stored in a memory device and scaled and output according to the display size. As shown in FIG. 7, this scaled video signal is output. Is combined with a separately generated image signal and displayed. The image signal is an analog signal obtained by graphic processing of a digital source.

  However, in order to perform two-screen display with such a configuration, it is necessary to convert a video signal into a digital signal once, hold it in a memory device, and scale it with a scaler. Therefore, a memory device and a scaler must be prepared. Therefore, there is a problem that the circuit becomes complicated and the price cannot be lowered.

  The following configuration has been proposed as an example of a device that takes measures against this. One display area is divided into two display areas, two drive circuits are used corresponding to each display area, and the two drive circuits are driven in association with each other to perform one-screen display. Are independently driven to perform two-screen display (see, for example, Patent Document 1).

However, even in a device having such a configuration, two drive circuits must be provided in order to drive the two display areas independently, and there is a problem that the circuit is complicated and versatility is difficult to obtain.
JP 2003-108967 A

  The present invention has been made in view of the above-described circumstances. When a plurality of screens are displayed on a single display screen using video signals and image signals, a plurality of screens can be displayed without scaling the video signals. It is an object of the present invention to provide a display signal processing circuit that generates a display signal for simple display and a liquid crystal display device including the display signal processing circuit.

  According to an embodiment of the present invention, the video is based on the horizontal synchronization signal obtained from a video signal having one horizontal scanning period having a video period including a video signal and a non-video period including a horizontal synchronization signal. A switching signal indicating a timing at which a non-video period and a video period in one horizontal scanning period of the signal are switched; a timing controller that generates a timing signal indicating a generation timing of an image signal; and the image generated according to the timing signal The video signal is received, the image signal is selected in the non-video period in the one horizontal scanning period, and the video signal is included in the video period in the one horizontal scanning period in accordance with the switching signal. A display signal processing circuit comprising a switch circuit for selecting a signal is provided.

  According to another embodiment of the present invention, in a liquid crystal display device having a liquid crystal display unit having a display screen and a driving circuit for driving and displaying the liquid crystal display unit, a video period including a video signal and a synchronization signal are included. A video signal processing circuit that outputs a video signal having one horizontal scanning period having a non-video period, an image signal generation circuit that outputs an image signal, a non-video period and a video period in one horizontal scanning period of the video signal, A timing controller that outputs a switching signal indicating the timing at which the video signal is switched; and the video signal output from the image signal generation circuit during a non-video period in one horizontal scanning period of the video signal in response to the switching signal output from the timing controller. An image signal is selected and output to the drive circuit, and the video signal is included in the video period in the one horizontal scanning period. The liquid crystal display device comprising a switch circuit for outputting to said driving circuit selects the video signal is provided.

  According to the present invention, when a plurality of screens are displayed using a video signal and an image signal on one display screen, a display signal for easily displaying the plurality of screens is generated without scaling the video signal. And a liquid crystal display device including the display signal processing circuit.

  Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

[First Embodiment]
First, a display signal processing circuit according to a first embodiment of the present invention will be described. Here, a case where a liquid crystal display unit is driven by a display signal processing circuit to perform two-screen display is taken as an example.

  FIG. 1 is a block diagram illustrating a configuration of a liquid crystal display device including a display signal processing circuit, a liquid crystal display unit, and a driver thereof according to the first embodiment. The liquid crystal display device includes a display signal processing circuit 10, a liquid crystal display unit 20, a source driver 21, and a gate driver 22. The display signal processing circuit 10 includes a video signal processing circuit 11, an image signal generator 12, a changeover switch 13, a gamma and inverter circuit 14, a synchronization separation circuit 15, a phase comparator (AFC) 16, a voltage controlled oscillator (VCO) 17, It consists of a horizontal timing logic circuit 18 and a vertical timing logic circuit 19. The phase comparator 16, the voltage controlled oscillator 17, and the horizontal timing logic circuit 18 constitute a PLL (phase-locked loop) and a timing controller 30 that generates various clock signals and control signals. .

  The video signal processing circuit 11 processes a video signal (composite video signal) input from the outside and outputs a video signal RGB-1 which is an RGB signal. The output video signal RGB-1 is input to the changeover switch 13.

  Note that a video signal (composite video signal) input from the outside is a signal that is transmitted in a time series in which image information is divided in the horizontal and vertical directions. The video signal RGB-1 has a plurality of horizontal scanning periods (1H periods), and one horizontal scanning period includes a video period including a video signal and a non-video period including a synchronization signal without including a video signal (return blanking period). ). The video signal input from the outside usually corresponds to a signal in a format conforming to a broadcast signal such as PAL / NTSC / SECAM, or a signal in a format often used in digital equipment such as YCbCr or YPbPr, and its output. Examples of the source include TV broadcast, VCR, and DVD.

  The sync separation circuit 15 receives the video signal, extracts a composite sync signal included in the video signal, and outputs a horizontal sync signal HD and a vertical sync signal VD. The phase comparator (AFC) 16 compares the phases of the horizontal synchronizing signal HD and the clock signal PCLK obtained by dividing the oscillation signal output from the voltage controlled oscillator 17 by the horizontal timing logic circuit 18, and an error signal corresponding to the phase difference. ERR is output. A voltage controlled oscillator (VCO) 17 receives the error signal ERR and generates a clock signal DOTCLK synchronized with a horizontal synchronization signal HD which is a reference for pixel drawing in the horizontal direction in the liquid crystal display unit 20. The oscillation frequency of the clock signal DOTCLK is controlled according to the error signal ERR.

  The horizontal timing logic circuit 18 receives the clock signal DOTCLK from the voltage controlled oscillator 17, and based on this clock signal DOTCLK, a horizontal pixel drawing clock signal (operation clock of the shift register in the source driver 21) SCLK, pixel drawing. A start signal SST for determining the start position of the image signal, a switch signal SSW for the changeover switch 13, a clock signal GRCLK for determining the drawing (output) timing of the image signal generator 12, and a phase difference from the horizontal synchronizing signal HD by the phase comparator (AFC) 16 Are generated, and a clock signal VCLK for operation in the vertical timing logic circuit 19 is generated.

  Here, the clock signal SCLK and the start signal SST are generated as follows. First, the horizontal synchronization signal HD included in the video signal and the clock signal PCLK obtained by frequency division of the clock signal DOTCLK output from the voltage controlled oscillator 17 by the horizontal timing logic circuit 18 are compared by the phase comparator 16, and the phase difference is output. Is done. The voltage controlled oscillator 17 outputs an oscillation signal at a frequency corresponding to the phase difference. Then, the oscillation of the voltage controlled oscillator 17 according to the phase difference and the comparison by the phase comparator 16 are repeated, and the oscillation of the voltage controlled oscillator 17 is controlled so that the phase difference is eliminated. By such a PLL (phase-locked loop), the horizontal synchronization signal HD and the clock signal PCLK divided by the horizontal timing logic circuit 18 are synchronized. The clock signal SCLK and the start signal SST of the source driver 21 are generated based on the clock signal DOTCLK output from the voltage controlled oscillator 17 at this time.

  The image signal generator 12 outputs an image signal RGB-2, which is an RGB signal, in response to the clock signal GRCLK from the horizontal timing logic circuit 18. The image signal RGB-2 is an analog signal obtained by graphic processing of a digital source, and corresponds to, for example, a signal for displaying a car navigation image or a signal for displaying a menu screen. The changeover switch 13 receives the video signal RGB-1 output from the video signal processing circuit 11 and the image signal RGB-2 output from the image signal generator 12, and responds to the changeover signal SSW from the horizontal timing logic circuit 18. Select one of the signals and output it.

  In the gamma and inverter circuit 14, the gamma circuit corrects the signal in accordance with the color development performance of the liquid crystal in the liquid crystal display unit 20, and the inverter circuit detects the video signal RGB-1 and the image signal RGB- in order to prevent deterioration of the liquid crystal element. Reverse the polarity of 2 alternately.

  The vertical timing logic circuit 19 receives the vertical synchronization signal VD output from the synchronization separation circuit 15, operates with the clock signal VCLK from the horizontal timing logic circuit 18, and sets the vertical pixel drawing start timing in the liquid crystal display unit 20. A prescribed start signal GST and a clock signal GCLK for scanning the drawing position are output.

  The source driver 21 and the gate driver 22 drive pixels (including TFTs) constituting the liquid crystal display unit 20. These drivers 21 and 22 are usually composed of an integrated circuit (IC), receive clock signals SCLK and GCLK from the horizontal timing logic circuit 18 or the vertical timing logic circuit 19, and operate in synchronization with these clock signals. . The source driver 15 drives the pixels in the horizontal direction in the liquid crystal display unit 17. Thus, the video signal RGB-1 and the image signal RGB-2 or any one of these signals is stored and supplied (storage for one line). The gate driver 16 drives the pixels in the vertical direction in the liquid crystal display unit 17. As a result, a line to be drawn is selected. The liquid crystal display unit 17 is formed of pixels arranged in the horizontal direction and the vertical direction, and displays the video signal RGB-1 and the image signal RGB-2 or any one of these signals.

  Hereinafter, the connection relationship in the display signal processing circuit 10 will be described.

  A video signal is input to the input portion of the video signal processing circuit 11 from the outside. The video signal is a signal transmitted by dividing image information in the horizontal and vertical directions and arranging them in time series.

The output part of the video signal processing circuit 11 is connected to the first input part of the changeover switch 13, and the output part of the image signal generator 12 is connected to the second input part of the changeover switch 13. The output part of the changeover switch 13 is connected to the input part of the source driver 21 via the gamma and inverter circuit 14.

  The video signal input from the outside is also input to the sync separation circuit 15. A first output portion of the sync separation circuit 15 is connected to a first input portion of a phase comparator (AFC) 16. The output of the phase comparator 16 is connected to the input of the horizontal timing logic circuit 18 via a voltage controlled oscillator (VCO) 17.

  A plurality of outputs of the horizontal timing logic circuit 18 are connected to the second input of the phase comparator (AFC) 16, the image signal generator 12, the changeover switch 13, the vertical timing logic circuit 19, and the source driver 21. ing. Further, the second output of the sync separator 15 is connected to the first input of the vertical timing logic 19, and the output of the horizontal timing logic 18 is connected to the second input of the vertical timing logic 19. . The first and second output sections of the vertical timing logic circuit 19 are connected to the input section of the gate driver 22, respectively. The outputs of the source driver 21 and the gate driver 22 are supplied to the liquid crystal display unit 20.

  Next, the operation of the liquid crystal display device including the display signal processing circuit of the first embodiment will be described.

  FIG. 2 is a time chart showing the operation of the liquid crystal display device including the display signal processing circuit. The video signal (composite video signal) input to the video signal processing circuit 11 is processed by the video signal processing circuit 11 and output to the changeover switch 13 as a video signal RGB-1 which is an RGB signal. The video signal (composite video signal) is also input to the sync separation circuit 15, the composite sync signal included in the video signal is extracted by the sync separation circuit 15, and the horizontal sync signal HD and the vertical sync signal VD are output.

  The horizontal synchronization signal HD is input to the phase comparator (AFC) 16. The phase comparator (AFC) 16 compares the phase of the input horizontal synchronization signal HD with the clock signal PCLK obtained by frequency dividing the clock signal DOTCLK output from the voltage controlled oscillator 17 by the horizontal timing logic circuit 18, and the phase difference An error signal ERR corresponding to is output. The error signal ERR is input to a voltage controlled oscillator (VCO) 17. The voltage controlled oscillator 17 outputs a clock signal DOTCLK serving as a reference for pixel drawing in the horizontal direction in the liquid crystal display unit 20 in accordance with the error signal ERR. The clock signal DOTCLK is again divided by the horizontal timing logic circuit 18 to generate the clock signal SCLK. The phase of the clock signal SCLK is compared with the horizontal synchronization signal HD by the phase comparator 16, and an error signal ERR corresponding to the phase difference is output. As described above, the phase comparison between the horizontal synchronizing signal HD and the clock signal SCLK by the phase comparator 16 and the oscillation of the clock signal DOTCLK in the voltage controlled oscillator 17 according to the phase difference are repeated, so that the phase difference is eliminated. In other words, the frequency of the clock signal DOTCLK in the voltage controlled oscillator 17 is controlled so that the phases of the horizontal synchronization signal HD and the clock signal SCLK match.

  The clock signal DOTCLK is input to the horizontal timing logic circuit 18. Based on the clock signal DOTCLK, the horizontal timing logic circuit 18 is a horizontal pixel drawing clock signal (shift register operating clock in the source driver 21) SCLK, a pixel drawing start signal SST that determines the pixel drawing start position, and a changeover switch 13. Switching signal SSW, a clock signal GRCLK that determines the drawing (output) timing of the image signal generator 12, a clock signal PCLK that is compared with the horizontal synchronization signal HD by the phase comparator (AFC) 16, and a vertical timing A clock signal VCLK for operation in the logic circuit 19 is generated.

  When the clock signal GRCLK that determines the drawing (output) timing is input to the image signal generator 12, the image signal RGB-2 is output to the changeover switch 13 at the timing determined by the clock signal GRCLK.

  Further, when the changeover signal SSW is input to the changeover switch 13, the changeover switch 13 selects and outputs either the video signal RGB-1 or the image signal RGB-2 according to the changeover signal SSW. The switching signal SSW indicates a timing at which the non-video period and the video period are switched in the 1H period (non-video period + video period) of the video signal RGB-1.

  Further, when the vertical synchronization signal VD and the clock signal VCLK are input to the vertical timing logic circuit 19, the vertical timing logic circuit 19 detects the vertical pixels of the liquid crystal display unit 20 based on the vertical synchronization signal VD and the clock signal VCLK. A start signal GST for defining the drawing start timing and a clock signal GCLK for scanning the drawing position are output.

Here, a method of generating the clock signal SCLK in the timing controller 30 constituted by the phase comparator 16, the voltage controlled oscillator 17, and the horizontal timing logic circuit 18 will be described. Conventionally, the frequency of the clock signal SCLK generated by the timing controller 30 is usually set so that the video period in the non-video period (about 16 μs) and the video period (about 48 μs) of the video signal is in the horizontal direction of the liquid crystal display unit 20. It is set to match the number of pixels (number of dots). For example, when the number of pixels is 480 (the number of dots is 1440 = 480 × 3),
(1/64 μs) × (480 × (64 μs / 48 μs)) = 9.6 MHz, and the oscillation frequency of the voltage controlled oscillator is 29 MHz (= 9.6 × 3 MHz), which is three times the frequency.

  In this embodiment, image display by the image signal RGB-2 output from the image signal generator 12 is performed during the non-video period in the 1H period of the video signal RGB-1, and video signal processing is performed during the video period in the 1H period. The video display by the video signal RGB-1 output from the circuit 11 is performed. Therefore, the clock frequency of the clock signal SCLK generated by the timing controller 30 is set so that the 1H period (non-video period + video period) of the video signal RGB-1 matches the number of pixels in the horizontal direction of the liquid crystal display unit 20. Set.

  For example, when the number of pixels is 480 (the number of dots is 1440 = 480 × 3), the frequency of the clock signal SCLK is 7.6 MHz (the oscillation frequency of the voltage controlled oscillator is set to (1/64 μs) × 480 = 7.6 MHz). Set to 23 MHz (= 7.6 × 3). Thereby, the clock number (image clock) of the clock signal SCLK that samples the image signal RGB-2 in the non-video period becomes 120, and the clock number (video clock) of the clock signal SCLK that samples the video signal RGB-1 in the video period. Is 360.

  The image signal generator 12 switches the image signal RGB-2 at the start of the non-video period according to the clock signal GRCLK output from the horizontal timing logic circuit 18 in order to display a desired image during the non-video period. 13 to output. At this time, the changeover switch 13 selects the image signal RGB-2 from the start time to the end time of the non-video period according to the changeover signal SSW output from the horizontal timing logic circuit 18 and outputs it to the source driver 21.

  Subsequently, the changeover switch 13 selects the video signal RGB-1 output from the video signal processing circuit 11 from the start of the video period (at the end of the non-video period) to the end in accordance with the switching signal SSW. Output to the source driver 21.

  As a result, the source driver 21 that receives a signal to be displayed on the liquid crystal display unit 20 is supplied with a signal obtained by synthesizing the image signal RGB-2 and the video signal RGB-1 in a time division manner. A signal in which an image signal and a video signal are combined in a time-division manner is sampled and held by the source driver 21 in accordance with the sampling frequency of the clock signal SCLK, and assigned to each pixel (each dot) in the horizontal direction. Thus, the entire display screen of the liquid crystal display unit 20 is divided into the first display screen 20A corresponding to the non-video period and the second display screen 20B corresponding to the video period. The first display screen 20A has the image signal RGB−. 2 is output, and a video display based on the video signal RGB-1 is output to the second display screen 20B.

  According to the display signal processing circuit having the above configuration, in the non-video period and the video period included in one horizontal scanning period of the video signal, the image signal RGB-2 is selected by the changeover switch 13 during the non-video period, The video signal RGB-1 is selected by the changeover switch 13. Thereby, two screens can be displayed on the one display screen of the liquid crystal display unit 20 by the image signal and the video signal. In this embodiment, since it is not necessary to digitize the video signal, store it in the image memory, and perform scaling, it is not necessary to perform processing by the image memory and the scaler, and two-screen display can be easily performed. Further, since there is no need to provide an image memory and a scaler, the versatility of the display signal processing circuit and the liquid crystal display device can be improved, and the cost can be reduced.

  Next, a display signal processing circuit according to a modification of the first embodiment will be described. FIG. 3 is a block diagram illustrating a configuration of a display signal processing circuit according to a modification of the first embodiment, a liquid crystal display device including a liquid crystal display unit and a driver thereof, and FIG. 4 illustrates a display signal processing circuit according to the modification. It is a time chart which shows operation | movement of the liquid crystal display device containing.

  As described above, the signal in which the image signal RGB-2 and the video signal RGB-1 are synthesized in a time-division manner is sampled and held by the source driver 21 in accordance with the clock signal SCLK, and the horizontal direction in the liquid crystal display unit 20 is displayed. Assigned to each pixel. By changing the frequency of the clock signal SCLK at this time between the non-video period and the video period, as shown in FIG. 3, the first display screen (image display) 20A and the second display screen (video) in the liquid crystal display unit 20 are displayed. Display) The display screen size ratio with 20B can be changed.

  For example, when the number of pixels is 480 (the number of dots is 1440 = 480 × 3) by doubling the frequency of the clock signal SCLK in the non-video period and the frequency in the video period by 2/3, FIG. As shown in FIG. 4, the number of clocks of the clock signal SCLK in the non-video period and the video period can be 240 respectively. Thereby, the display screen size ratio in the liquid crystal display unit 20 is “first display screen (image display): second display screen (video display) = 1: 1”.

  By setting the number of clocks in the non-video period to 160 and the number of clocks in the video period to 320, the display screen size ratio of the liquid crystal display unit 17 is changed to “first display screen (image display): second display screen ( (Video display) = 1: 2 ”.

Such control of the frequency of the clock signal SCLK within the 1H period is usually realized by changing the frequency division ratio of the clock signal DOTCLK by the horizontal timing logic circuit 18. As an example, a frequency when “first display screen (image display): second display screen (video display) = 1: 3” is used, and “first display screen: second display screen = 1: 1”. The case will be described.

  In the above embodiment, the frequency of the clock signal DOTCLK output from the voltage controlled oscillator is 23 MHz. This 23 MHz is an oscillation frequency that is three times the sampling clock of each of the R, G, and B axes. Therefore, the clock signal SCLK as shown in FIG. 4 can be realized by changing the frequency division number. As shown in FIG. 5, the clock signal SCLK at the time of displaying “first display screen (image display): second display screen (video display) = 1: 3” is an image display period (non-video period). The number is changed from 120 to 240 (doubled), and the video display period (video period) is changed from 360 to 240 (2/3). Thereby, it is possible to display with “first display screen: second display screen = 1: 1”.

  In this embodiment, the case of performing the two-screen display has been described. However, if two or more image signals are displayed in the non-video period, it is possible to display three or more screens. Moreover, although the example which displays a color image was demonstrated, it is applicable also when displaying a monochrome image.

[Second Embodiment]
Next explained is a display signal processing circuit according to the second embodiment of the invention. The same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. Only different components will be described below. Here, the case where the liquid crystal display unit is driven by the display signal processing circuit to perform two-screen display is taken as an example.

  FIG. 6 is a block diagram illustrating a configuration of a liquid crystal display device including a display signal processing circuit, a liquid crystal display unit, and a driver thereof according to the second embodiment. The time chart showing the operation of the liquid crystal display device of the second embodiment is the same as that shown in FIG.

  In the first embodiment, the control of the clock signal for horizontal synchronization and pixel drawing is configured by one PLL, but in the second embodiment, the clock signal for horizontal synchronization is controlled by phase comparison. 16A, a voltage controlled oscillator 17A and a horizontal timing logic circuit 18A are used to control a pixel drawing clock signal in the liquid crystal display unit 20 to control the phase comparator 16B, the voltage controlled oscillator 17B, and the horizontal. This is performed by a PLL composed of the timing logic circuit 18B.

  Hereinafter, a connection relationship different from that of the first embodiment in the display signal processing circuit 40 is described. A first output portion of the synchronization separation circuit 15 is connected to a first input portion of a phase comparator (AFC) 16A. The output section of the phase comparator 16A is connected to the input section of the horizontal timing logic circuit 18A through a voltage control oscillator (VCO) 17A for horizontal synchronization.

  The plurality of outputs of the horizontal timing logic circuit 18A are connected to the second input of the phase comparator (AFC) 16A, the input of the vertical timing logic 19 and the first input of the phase comparator (PD) 16B, respectively. Has been. The output section of the phase comparator 16B is connected to the input section of the horizontal timing logic circuit 18B via a voltage drawing oscillator (VCO) 17B for pixel drawing in the liquid crystal display section.

  A plurality of outputs of the horizontal timing logic circuit 18B are connected to respective inputs of the second input of the phase comparator (PD) 16B, the image signal generator 12, the changeover switch 13, and the source driver 21.

  Next, the operation of each part constituting the display signal processing circuit 40 will be described.

  The phase comparator (AFC) 16A compares the phases of the horizontal synchronization signal HD and the clock signal PCLK1 obtained by dividing the clock signal HCLK output from the voltage controlled oscillator 17A by the horizontal timing logic circuit 18A, and according to the phase difference. An error signal ERR1 is output. The voltage controlled oscillator (VCO) 17A receives the error signal ERR1, controls the oscillation frequency of the clock signal HCLK in accordance with the error signal ERR1, and performs a double oscillation of the frequency for horizontal synchronization.

  The horizontal timing logic circuit 18A receives the clock signal HCLK from the voltage controlled oscillator 17A, and compares the phase with the horizontal synchronization signal HD-2 by the horizontal synchronization signal HD-2 and the phase comparator (AC) 16A based on this clock signal HCLK. The clock signal PCLK1 and the clock signal VCLK for operation in the vertical timing logic circuit 19 are generated.

  The phase comparator (PD) 16B compares the phase of the horizontal synchronization signal HD-2 with the clock signal PCLK2 obtained by frequency-dividing the clock signal DOTCLK output from the voltage controlled oscillator 17B by the horizontal timing logic circuit 18B. A corresponding error signal ERR2 is output. The voltage controlled oscillator (VCO) 17B receives the error signal ERR2, and generates a clock signal DOTCLK that is a reference for pixel drawing in the horizontal direction in the liquid crystal display unit 20. The clock signal DOTCLK has its oscillation frequency controlled according to the error signal ERR2.

  The horizontal timing logic circuit 18B receives the clock signal DOTCLK from the voltage controlled oscillator 17B, and determines the pixel drawing clock signal (the operation clock of the shift register in the source driver 21) SCLK and the pixel drawing start position according to the clock signal DOTCLK. The phase of the start signal SST to be determined, the switching signal SSW of the changeover switch 13, the clock signal GRCLK to determine the drawing (output) timing of the image signal generator 12, and the phase of the horizontal synchronizing signal HD-2 in the phase comparator (PD) 16B. A clock signal PCLK2 to be compared is generated. Other configurations are the same as those in the first embodiment.

  In the display signal processing circuit having the above-described configuration, it is possible to divide the voltage-controlled oscillator 17A for synchronous reproduction of the video signal and the voltage-controlled oscillator 17B for driving the liquid crystal panel to have different oscillation frequencies. Even when the oscillation frequency of the voltage controlled oscillator 17B for driving the liquid crystal panel is changed according to the number of pixels of various liquid crystal panels, it is not necessary to change the oscillation frequency of the voltage controlled oscillator 17A for video signal synchronous reproduction. Thereby, the versatility of the display signal processing circuit can be improved. Other effects are the same as those of the first embodiment.

  In the embodiment, the vertical length of the image on each display screen divided into two or plural is fixed. To compress the image in the vertical direction (for example, cut the top and bottom) and bring the aspect ratio of the display screen close to normal, perform vertical interpolation (for example, skipping / writing twice) and thinning out, Change the screen size.

  In addition, each of the above-described embodiments can be implemented not only independently but also in an appropriate combination. Furthermore, the above-described embodiments include inventions at various stages, and the inventions at various stages can be extracted by appropriately combining a plurality of constituent elements disclosed in the embodiments.

It is a block diagram which shows the structure of the liquid crystal display device containing the display signal processing circuit of 1st Embodiment of this invention. 6 is a time chart illustrating an operation of a liquid crystal display device including the display signal processing circuit of the first embodiment. It is a block diagram which shows the structure of the liquid crystal display device containing the display signal processing circuit of the modification of the said 1st Embodiment. 7 is a time chart illustrating an operation of a liquid crystal display device including a display signal processing circuit according to a modification of the first embodiment. It is a figure which shows a mode that the clock signal SCLK is changed by the change of the frequency division ratio in the modification of the said 1st Embodiment. It is a block diagram which shows the structure of the liquid crystal display device containing the display signal processing circuit of the 2nd Embodiment of this invention. It is a time chart which shows operation | movement of the conventional liquid crystal display device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Display signal processing circuit, 11 ... Video signal processing circuit, 12 ... Image signal generator, 13 ... Changeover switch, 14 ... Gamma and inverter circuit, 15 ... Synchronization separation circuit, 16 ... Phase comparator (AFC), 17 ... Voltage control oscillator (VCO), 18 ... horizontal timing logic circuit, 19 ... vertical timing logic circuit, 20 ... liquid crystal display unit, 21 ... source driver, 22 ... gate driver, 30 ... timing controller.

Claims (5)

A non-video period in one horizontal scanning period of the video signal based on the horizontal synchronizing signal obtained from a video signal having one horizontal scanning period having a video period including a video signal and a non-video period including a horizontal synchronizing signal And a timing controller that generates a timing signal that indicates a generation timing of the image signal, a switching signal that indicates a timing at which the video period is switched,
The image signal generated in response to the timing signal and the video signal are received, the image signal is selected in a non-video period in the one horizontal scanning period in response to the switching signal, and the one horizontal scanning period A switch circuit for selecting the video signal included in the video signal in a video period in
A display signal processing circuit comprising:   The timing controller includes a phase comparator, an oscillator, and a horizontal timing logic circuit constituting a PLL (phase-locked loop), and the phase comparator compares the phases of the horizontal synchronization signal and the oscillation signal of the oscillator. The oscillator outputs a phase difference, and the oscillator outputs an oscillation signal whose frequency is controlled in accordance with the phase difference, so that an oscillation signal whose phase matches that of the horizontal synchronization signal is input to the horizontal timing logic circuit. The display signal processing device according to claim 1.   The horizontal timing logic circuit, when dividing the oscillation signal, changes a division ratio of the oscillation signal between the non-video period and the video period in one horizontal scanning period of the video signal. The display signal processing apparatus according to claim 2. A video signal processing circuit for outputting a video signal having one horizontal scanning period having a video period including a video signal and a non-video period including a horizontal synchronization signal;
A sync separator for extracting a horizontal sync signal from the video signal;
The display signal processing circuit according to claim 1, further comprising: In a liquid crystal display device having a liquid crystal display unit having a display screen, and a driving circuit for driving and displaying the liquid crystal display unit,
A video signal processing circuit for outputting a video signal having one horizontal scanning period having a video period including a video signal and a non-video period including a synchronization signal;
An image signal generation circuit for outputting an image signal;
A timing controller that outputs a switching signal indicating a timing of switching between a non-video period and a video period in one horizontal scanning period of the video signal;
In response to the switching signal output from the timing controller, the video signal selected from the image signal generation circuit in a non-video period in one horizontal scanning period of the video signal is selected and output to the drive circuit, A switch circuit that selects and outputs the video signal included in the video signal to the drive circuit in a video period in one horizontal scanning period;
A liquid crystal display device comprising:

Images