JP2005310983A - Wiring board with built-in capacitor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To further increase the electrostatic capacity of a capacitor in a wiring board (the wiring board with the built-in capacitor) having the capacitor as a built-in device and a manufacturing method for the wiring board. <P>SOLUTION: The wiring board with the built-in capacitor has at least three layers of electrode plates, dielectric resin layers which are mounted among the electrode plates respectively and in which each functions as plate base materials as the wiring boards, and interlayer connectors penetrating the dielectric resin layers and connecting the electrode in interlayer so as to form electrically other nodes in a staggered manner. In the manufacturing method, patterns are formed for using conductive layers formed on dielectric resin sheets, and at least one of second dielectric resin sheets is laminated for integration with unpatterned conductive layers on the resin sheet with patterned conductive layers. The interlayer connectors are formed by penetrating the integrated dielectric resin sheets and the second dielectric resin sheets, so as to form the patterned conductive layers alternately in electrically different nodes alternately in the staggered manner. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a wiring board having a capacitor as a built-in device (capacitor built-in wiring board) and a method for manufacturing the same, and more particularly to a capacitor built-in wiring board suitable for increasing the capacitance of a capacitor and a method for manufacturing the same.

As a conventional capacitor built-in wiring board, for example, there is one described in Non-Patent Document 1 below. The wiring board has a structure in which a resin layer having a high relative dielectric constant is used as a capacitor dielectric, and the upper and lower sides of the high relative dielectric constant resin layer are sandwiched between wiring layers. The upper and lower wiring layers become both electrodes as a capacitor by predetermined patterning. In this structure, it is possible to increase the capacitance by using a material having a higher relative dielectric constant as the resin layer serving as the dielectric of the capacitor.
Shimada et al., “Development of capacitor built-in wiring board for RF module”, Journal of Japan Institute of Electronics Packaging, 2002, Vol. 5, No. 7, p. 636-640

  However, when trying to increase the capacitance further by using a material having a high dielectric constant that can be used in the process of an organic material printed wiring board, the area as a capacitor, that is, the area of both electrodes is usually reduced. It is necessary to increase the area, and the area where another wiring pattern is formed is pressed. Therefore, in applications that require miniaturization as a wiring board, the actual area that can be used as a capacitor is usually limited. For this reason, contribution to the reduction in size and weight of electronic devices in recent years is limited as a capacitor built-in wiring board.

  The present invention has been made in consideration of such circumstances, and in a wiring board having a capacitor as a built-in device (capacitor-embedded wiring board) and a method for manufacturing the same, the capacitance of the capacitor can be further increased. An object of the present invention is to provide a capacitor built-in wiring board and a manufacturing method thereof.

  In order to solve the above-described problems, a capacitor built-in wiring board according to the present invention includes at least three electrode plates and a dielectric resin layer provided between each of the electrode plates, each of which is a plate substrate as a wiring board. And an interlayer connection member that connects the layers so as to penetrate the dielectric resin layer and make the electrode plates electrically different nodes alternately in the layer direction.

  That is, a dielectric resin layer is present as a plate base material between each electrode plate as a capacitor. Then, the interlayer connection body passes through the dielectric resin layer and connects the electrode plates so that these electrode plates are electrically separated from each other in the layer direction. Therefore, both electrodes of the electrode plate as a capacitor have a structure in which the facing area can be increased according to the number of stacked electrode plates. Therefore, it is possible to further increase the capacitance of the capacitor without increasing the area.

  Further, the method for manufacturing a capacitor built-in wiring board according to the present invention includes a step of patterning the conductive layer provided on the dielectric resin sheet so as to be a part of the electrode plate, and a pattern forming at the outermost layer direction. At least one second dielectric resin sheet provided with an unpatterned conductive layer is laminated on the dielectric resin sheet provided with the patterned conductive layer so that no conductive layer is disposed. A step of integrating and passing through the integrated dielectric resin sheet and the second dielectric resin sheet so that the patterned conductive layers are alternately electrically separated in the layer direction. A step of forming an interlayer connection, the outermost conductive layer in the layer direction as another part of the electrode plate, and the outermost conductive layer in the layer direction and the patterned conductive layer are layered Direction each other Wherein the electrically by comprising the step of patterning the layer direction outermost conductive layer in order to another node are.

  This manufacturing method can manufacture the capacitor built-in wiring board. Therefore, it is possible to provide a method for manufacturing a capacitor built-in wiring board capable of further increasing the capacitance of the capacitor.

  According to the present invention, in a wiring board having a capacitor as a built-in device and a manufacturing method thereof, the facing area of the capacitor electrode plate is substantially increased without increasing the area as the device, and the capacitance is further increased. It is possible to increase.

  As an embodiment of the present invention, a wiring layer including the outermost layer in the layer direction among the electrode plates and an insulating layer laminated on a side of the wiring layer opposite to the side on which the dielectric resin layer is provided A layer, a second wiring layer laminated on the side of the insulating layer opposite to the side where the wiring layer is located, and the wiring layer and the second wiring layer passing through the insulating layer You may make it further comprise the 2nd interlayer connection body to connect. This is a multi-layer wiring structure.

  Here, the second interlayer connector may be an interlayer connection between the wiring layer that is not removed as a pattern and the second wiring layer that is not removed as a pattern. That is, the second interlayer connection body is made of a conductive composition and has a shape that has an axis that coincides with the layer direction and whether or not the diameter changes in the direction of the axis. Such is the case. In another case, the second interlayer connection body is made of metal and has a columnar or frustum shape having an axis coinciding with the layer direction.

  In the former, for example, a conductive bump made of a conductive composition is formed on a metal foil that is a previous stage of the second wiring layer, and the formed conductive bump is passed through the insulating layer. This is a case where the second interlayer connector is used. Alternatively, a via hole is formed in the insulating layer with a laser, the formed via hole is filled with a conductive plastic material, and a metal foil is laminated and integrated thereon. In the latter case, for example, a conductive bump is formed by etching a metal plate, which is a previous stage of the second wiring layer, or plating on a metal foil, and penetrating the formed conductive bump into the insulating layer. This is a case where the second interlayer connector is obtained.

  In addition, the second interlayer connection body may be formed of a conductive composition and has a cylindrical shape whose axial direction matches the layer direction. This is, for example, a configuration in which a via hole is formed in the insulating layer with a laser and the formed via hole is filled with a conductive composition. Further, the second interlayer connection body may be made of a metal, has a truncated cone shape in which the axial direction coincides with the layer direction, and the inside of the truncated cone is empty. This is the case, for example, when a frustoconical via hole is formed in the insulating layer by a laser, and a conductive layer is formed on the inner wall surface of the formed via hole by plating.

  Further, in the second interlayer connection body, a portion that is the electrode plate in the wiring layer may be used as a connection portion in the interlayer connection to the second wiring layer. According to this, the electrode plate also functions as a land for interlayer connection, which can contribute to the improvement of the wiring pattern placement efficiency.

  In addition, as an embodiment as a manufacturing method, a step of laminating and forming a layer having an insulating layer and a conductive layer on the pattern-formed outermost conductive layer may be further provided. This is for forming a multilayer wiring layer.

  Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a process diagram schematically showing a manufacturing process of a capacitor built-in wiring board according to an embodiment of the present invention. FIG. 2 and FIG. 3 are each a continuation diagram of the previous figure, and are process diagrams schematically showing a manufacturing process of the capacitor built-in wiring board according to the embodiment of the present invention. In each figure, the process proceeds in order from (a). In these drawings, the same reference numerals are given to the same components.

  First, as shown in FIG. 1A, three double-sided copper-clad high relative dielectric constant resin sheets 1, 2, and 3 are prepared. The high relative dielectric constant resin layers 11, 21, and 31, which are those base materials, each have a thickness of, for example, 20 μm, a copper layer (conductive layer) 12 laminated on both surfaces of the high relative dielectric constant resin layers 11, 21, and 31, Each of 13, 22, 23, 32, and 33 has a thickness of, for example, 5 μm (for example, can be formed by electrolytic plating). The high dielectric constant resin layers 11, 21, and 31 have a relative dielectric constant of several tens (for example, 50) are currently available. Such a high relative dielectric constant can be obtained, for example, by a structure in which fine particles of barium titanate, which is a high relative dielectric constant material, are dispersed as a filler in a resin.

  Next, as shown in FIG.1 (b), about the high dielectric constant resin sheet 1, the lower copper layer 13 is made into a predetermined patterned copper layer 13a in the figure. Such patterning can be performed by etching using, for example, a well-known photolithography method. Similar patterning of the copper layer is performed on the copper layers 22 and 23 on both sides for the high relative dielectric constant resin sheet 2 to form the patterned copper layers 22a and 23a, respectively, and for the high relative dielectric constant resin sheet 3 Is performed on the upper copper layer 32 in the figure to form a patterned copper layer 32a.

  Next, as shown in FIG.1 (c), the high dielectric constant resin sheets 4 and 5 are arrange | positioned between each of the high dielectric constant resin sheets which have the copper layer patterned. Each of the high dielectric constant resin sheets 4 and 5 has a thickness of, for example, 30 μm and a relative dielectric constant of several tens (for example, 50). And as shown in FIG.1 (c), after aligning each sheet | seat, it heat-presses in the lamination direction, and is integrated. Thereby, a double-sided copper-clad laminate having copper layers 13a, 22a, 23a, and 32a patterned as inner layers as shown in FIG. 1 (d) can be obtained. This thickness (total thickness) is, for example, 130 μm.

  When laminated and integrated as shown in FIG. 1 (d), the patterned copper layers 13a, 22a, 23a, and 32a are convex on the high dielectric constant resin sheets 4 and 5, respectively. Therefore, unlike the high relative dielectric constant resin layers 11, 21, and 31 of the high relative dielectric constant resin sheets 1, 2, and 3, the high relative dielectric constant resin sheets 4 and 5 exhibit plasticity by this heating press. It is more preferable to use what to do. According to this, it is easy to control the space | interval between each copper layer 13a, 22a, 23a, 32a which will function as an electrode plate of a capacitor to predetermined. Such interval control is important for making the capacitance value as a capacitor without variation. The capacitance value depends on the electrode spacing.

  The laminated plate shown in FIG. 1 (d) has an electrode plate as a capacitor and a dielectric, but is also a plate substrate as a wiring board. In that sense, the patterning in each of the copper layers 13a, 22a, 23a, and 32a may naturally include the formation of an arbitrary wiring pattern in addition to the patterning for forming the capacitor electrode plate.

  Next, as shown to Fig.2 (a), the through-holes 6a, 6b, and 7 are formed in the predetermined position of the obtained laminated board. For this formation, a well-known method such as a drill method or a laser method can be used. Here, the positions of the through holes 6a and 6b are positions in which the copper layers 13a, 22a, 23a, and 32a that are patterned and formed as inner layers are alternately penetrated / non-penetrated in the layer direction. The through hole 7 is a simple through hole for interlayer connection between the outermost copper layers 12 and 33 provided at a position unrelated to the formation of the capacitor.

  Next, as shown in FIG. 2B, conductive plating layers 8a, 8b, and 8c are formed on the inner walls of the through holes 6a, 6b, and 7 with a thickness of 5 μm, for example. For this formation, for example, a well-known two-step plating layer forming method of non-electrolytic plating and electrolytic plating can be used. As a result, in the through holes 6a and 6b, the copper layers 13a, 22a, 23a, and 32a that are patterned and are the inner layers are alternately different nodes in the layer direction.

  Next, as shown in FIG. 2C, the outermost copper layers 12 and 33 are etched using a well-known photolithographic method, for example, to form patterned copper layers 12a and 33a. In this pattern formation, the portions of the copper layers 12a and 33a that are electrically connected to the plating layers 8a and 8b become another part of the electrode plate as a capacitor. That is, in all of the patterned copper layers 12a, 13a, 22a, 23a, 32a, 33a, the copper layers are alternately separated in the layer direction by the plating layers 8a, 8b as the interlayer connection bodies. It becomes. Of course, the patterned copper layers 12a and 33a may be used as an arbitrary wiring pattern except for a region used as an electrode plate of a capacitor.

  The configuration shown in FIG. 2C can exhibit a temporary function as a capacitor built-in wiring board. In other words, the outermost patterned copper layers 12a and 33a are each wiring layer as a so-called double-sided board, and a predetermined node in the wiring layer pattern on both sides functions as a capacitor. In addition, the electrode plate as a capacitor is composed of patterned copper layers 12a, 13a, 22a, 23a, 32a, 33a. With such a laminated structure, the facing area of the capacitor electrode plate can be increased, and the capacitance can be increased more than that obtained in a planar area.

  Here, the electrode plate as a capacitor has a structure composed of a total of 6 layers of 3 layers + 3 layers. However, as can be understood from the above description, a total of 3 layers of 2 layers + 1 layers is the minimum based on the same idea. It is possible to manufacture from a layer to a layer with more than 6 layers. In the case of a total of three layers, a sheet similar to the double-sided copper-clad high relative dielectric constant resin sheet 1 and a single-sided copper-clad high relative dielectric constant resin sheet 1 are prepared. Only one side is patterned. Then, the two sheets are laminated and integrated so that the patterned surface is the inner layer. This state is the same as the stage of FIG. 1D although the structure is simplified. Hereinafter, each process shown in FIG. 2 may be performed.

  The form shown in FIG. 2 (c) is an embodiment as a capacitor built-in wiring board, but a process example in which the capacitor built-in wiring board is subsequently used as a core board to be multilayered as a wiring board will be described with reference to FIG. To do. First, as shown in FIG. 3A, substantially conical bumps 73 and 74 made of a conductive composition are printed at predetermined positions on copper foils 71 and 72 having a thickness of 18 μm, for example, by screen printing, for example. ·Form. In screen printing, for example, a metal screen mask in which cylindrical through holes are formed is used, and the conductive composition prepared in a paste form is transferred onto the copper foils 71 and 72 from the through holes. Then, the bumps 73 and 74 are dried after the transfer. As the conductive composition, for example, a conductive filler such as silver particles dispersed in a resin can be used.

  Next, a prepreg made of glass epoxy resin with a thickness of, for example, 60 μm is disposed on the bumped copper foil, and the glass epoxy resin is softened and pressurized while heating to a temperature at which the curing reaction does not proceed rapidly, The conductive bumps 73 and 74 are laminated and integrated while penetrating the prepreg. Thereby, the thing as shown in FIG.3 (b) which penetrates the insulating layers 75 and 76 by a prepreg and the head of the conductive bumps 73 and 74 is exposed can be obtained. In FIG. 3B, the broken line portions of the head portions of the conductive bumps 73 and 74 indicate that there are both cases where the head portion is crushed and plastically deformed at this stage, and when it is not.

  Next, as shown in FIG. 3C, bumps 73 and 74 and copper foils 71 and 72 with insulating layers 75 and 76 are laminated on both surfaces of the capacitor built-in wiring board shown in FIG. Integrated with a heating press. By this integration, the insulating layers 75 and 76 are completely cured, and the conductive bumps 73 and 74 as a whole have a truncated cone shape (generally, the diameter changes in the axial direction due to plastic deformation). Shape) and pressed and electrically connected to the oppositely formed patterned copper layers 12a and 33a. The direction of the axis of the truncated cone coincides with the stacking direction. Further, the inside of the through holes 6a, 6b, 7 having plating layers 8a, 8b, 8c on the inner wall surface is filled with the prepreg fluidized in the heating press.

  The conductive bumps 73 and 74 serve as vias (interlayer connection bodies) for interlayer connection between the copper layers 12a and 33a in portions not removed as a pattern and the copper foils 71 and 72 in portions not removed as a pattern. In particular, as shown in FIG. 3C, it may be arranged at a position directly connected to a portion of an electrode plate as a capacitor. Such direct connection eliminates the need to separately provide capacitor connection lands on the patterned copper layers 12a and 33a. This is preferable in terms of pattern layout.

  Next, as shown in FIG. 4, the copper foils 71 and 72, which are the outermost layers after lamination, are etched using a well-known photolithographic method, for example, to form wiring patterns (second wiring layers) 71a and 72a. Form. Thereby, a multilayered capacitor built-in wiring board can be obtained. 3 can be further multilayered as a wiring board by further continuing the process shown in FIG. 3 to the wiring board shown in FIG. Such multi-layering can be continued in the same manner.

  One of the advantages of this embodiment is that there are few restrictions on the layout of the multilayer wiring board. That is, the wiring patterns 71a and 72a can be used in the same manner regardless of whether or not the conductive bumps 73 and 74 are arranged on the inner side. For example, it is also easy to arrange conductive bumps on the conductive bumps. Although there is no such advantage, instead of the interlayer connection by the conductive bumps 73 and 74, a through hole is formed in the entire wiring board shown in FIG. Of course, a connection body is also possible.

  The capacitance of the capacitor was measured in the capacitor built-in wiring board having the configuration shown in FIG. 4 obtained by the above process. As a result, a value of 110 pF per 1 mm square could be obtained. This is about five times the value of the conventional one having a high relative dielectric constant resin layer. As shown in FIG. 4, the high relative dielectric constant resin layer has five layers (11, 4,. 21, 5, 31), which is almost the same as the theoretical value.

  In the above embodiment, instead of forming the conductive bumps 73 and 74 by screen printing as shown in FIG. 3A, the following method for forming the conductive bumps may be employed. One of them is a method of forming a columnar, frustum-shaped or conical conductive bump (so-called etching bump) by preparing a metal (for example, copper) plate and etching the plate. In the region where the conductive bump is not formed, the thickness is reduced by etching in the thickness direction of the plate, and the conductive bump is formed so as not to be etched.

  Alternatively, a metal foil (for example, a copper foil) having a thickness similar to that of the copper foils 71 and 72 is prepared, and a conductive bump (so-called plating bump) having a columnar shape, a frustum shape, or a conical shape as a whole by plating on the metal foil. ). In any of the etching and plating methods, the formed metal conductive bumps can be used for the subsequent steps by handling them instead of the conductive bumps 73 and 74 by screen printing. That is, as a result, the configuration and form as shown in FIG. 4 are obtained, and the conductive bump as the interlayer connection body has the axis direction coincident with the stacking direction.

  Next, a capacitor built-in wiring board according to another embodiment of the present invention will be described with reference to FIG. FIG. 5 is a cross-sectional view showing a schematic configuration of a capacitor built-in wiring board according to another embodiment of the present invention, in which parts corresponding to those already described are denoted by the same reference numerals. The description of that part is omitted. As shown in the figure, this capacitor built-in wiring board has columnar interlayer connectors 83 and 84 whose axial directions coincide with the stacking direction as interlayer connectors instead of the conductive bumps 73 and 74 of FIG. is there.

  Such a structure can be manufactured by the following processes, for example. The steps shown in FIGS. 1A to 2C are the same. Subsequently, the insulating layers 75 and 76 and the insulating layers 75 and 76 in which the copper foils, which are the previous stages of the wiring patterns 71a and 72a, are laminated separately or in advance, respectively, are shown in FIG. 2 (c). Laminated on both sides of the capacitor built-in wiring board and integrated by pressing and heating press.

  Next, the copper foil which is the outermost layer after lamination is etched using a well-known photolithography method, for example, to form wiring patterns (second wiring layers) 71a and 72a. At this time, the copper foil is also removed by etching at portions where the interlayer connectors 83 and 84 are to be formed. After this etching, for example, predetermined positions of the insulating layers 75 and 76 are laser processed using the formed wiring patterns 71a and 72a as masks to form via holes reaching the patterned copper layers 12a and 33a. Furthermore, a conductive composition can be filled in the formed via hole to obtain a structure as shown in FIG. In this embodiment, it is somewhat difficult to use the part directly above the interlayer connectors 83 and 84 as a component mounting land or an arrangement position of an interlayer connector in the case of further stacking, but the manufacturing process is simple.

  Next, a capacitor built-in wiring board according to still another embodiment of the present invention will be described with reference to FIG. FIG. 6 is a cross-sectional view showing a schematic configuration of a capacitor built-in wiring board according to still another embodiment of the present invention, and the same reference numerals are given to the same parts as those already described. The description of that part is omitted. As shown in the figure, this capacitor built-in wiring board is a columnar shape whose axial direction coincides with the laminating direction as shown in FIG. 5 as an interlayer connection body replacing the conductive bumps 73 and 74 of FIG. That is, it has interlayer connection bodies 93 and 94 having a shape whose diameter does not change in the axial direction. However, unlike the case shown in FIG. 5, these interlayer connectors 93 and 94 are connected to the portions where the outer wiring patterns 71 and 72a are not removed.

  Such a structure can be manufactured by the following processes, for example. The steps shown in FIGS. 1A to 2C are the same. Subsequently, the insulating layers 75 and 76 are laminated on both surfaces of the capacitor built-in wiring board shown in FIG. 2C, and are integrated by pressing and heating press. Next, laser processing is performed on predetermined positions of the insulating layers 75 and 76 to form via holes reaching the patterned copper layers 12a and 33a. Further, the conductive compositions 93 and 94 are filled in the formed via holes.

  Subsequently, a copper foil, which is a previous stage of the wiring patterns 71a and 72a, is laminated on the insulating layers 75 and 76, and integrated by pressing and heating press. Finally, the copper foil which is the outermost layer after lamination is etched using a well-known photolithography method, for example, to form wiring patterns (second wiring layers) 71a and 72a. In this manufacturing method, the process is slightly more complicated than the embodiment shown in FIG. 4, but similarly, there are less restrictions on layout as a multilayer wiring board.

  Or it can also manufacture as follows. 1 (a) to 2 (c) are the same, and then insulating layers 75 and 76 are prepared, and through holes are formed at predetermined positions by laser processing. Then, the through hole is filled with a conductive paste. Subsequently, the insulating layers 75 and 76, and the copper foil, which is the previous stage of the wiring patterns 71a and 72a, are arranged and laminated on both sides of the capacitor built-in wiring board shown in FIG. Integration by heating press. Finally, the copper foil which is the outermost layer after lamination is etched using a well-known photolithography method, for example, to form wiring patterns (second wiring layers) 71a and 72a. In this manufacturing method, the outer layer is formed by a single lamination and integration process, and the process becomes simpler.

  Next, a capacitor built-in wiring board according to still another embodiment of the present invention will be described with reference to FIG. FIG. 7 is a cross-sectional view showing a schematic configuration of a capacitor built-in wiring board according to still another embodiment of the present invention, and the same reference numerals are given to the same parts as those already described. The description of that part is omitted. As shown in the figure, this capacitor built-in wiring board has truncated cone-shaped interlayer connectors 103 and 104 whose axial directions coincide with the layer direction as interlayer connectors instead of the conductive bumps 73 and 74 of FIG. It is. The frustoconical interlayer connectors 103 and 104 are empty inside, and are therefore recessed when viewed from above.

  Such a structure can be manufactured by the following processes, for example. The steps shown in FIGS. 1A to 2C are the same. Subsequently, the process proceeds in the same manner as in the embodiment shown in FIG. 5, and predetermined positions of the insulating layers 75 and 76 are laser processed to form via holes reaching the patterned copper layers 12a and 33a. In this laser processing, processing is adjusted so that the via hole has a truncated cone shape.

  Next, a conductive plating layer (metal layer) is formed on the inner wall of each via hole to obtain interlayer connectors 103 and 104. For this formation, for example, a well-known two-step plating layer forming method of non-electrolytic plating and electrolytic plating can be used. Finally, the copper foil which is the outermost layer is etched using a well-known photolithography method, for example, to form wiring patterns (second wiring layers) 71a and 72a. As in the embodiment shown in FIG. 5, this embodiment is not suitable for the case where the portion immediately above the interlayer connection bodies 103 and 104 is used as a component mounting land or an arrangement position of the interlayer connection body when further stacking. It is simple as a manufacturing process.

The process figure which shows the manufacturing process of the wiring board with a built-in capacitor based on one Embodiment of this invention with a typical cross section. FIG. 2 is a continuation diagram of FIG. 1, and a process diagram showing a manufacturing process of a capacitor built-in wiring board according to an embodiment of the present invention in a schematic cross section. FIG. 3 is a continuation diagram of FIG. 2, and is a process diagram schematically showing a manufacturing process of the capacitor built-in wiring board according to one embodiment of the present invention. Sectional drawing which shows the typical structure of the wiring board with a built-in capacitor which concerns on one Embodiment of this invention. Sectional drawing which shows the typical structure of the wiring board with a built-in capacitor which concerns on another embodiment of this invention. Sectional drawing which shows the typical structure of the wiring board with a built-in capacitor which concerns on another embodiment of this invention. Sectional drawing which shows the typical structure of the wiring board with a built-in capacitor which concerns on another embodiment of this invention.

Explanation of symbols

  1, 2, 3 ... Copper-clad high relative dielectric constant resin sheet, 4, 5 ... High relative dielectric constant resin sheet, 6a, 6b, 7 ... Through-hole, 8a, 8b, 8c ... Plating layer, 11, 21, 31 ... high relative dielectric constant resin layer, 12, 13, 22, 23, 32, 33 ... copper layer (conductive layer), 12a, 13a, 22a, 23a, 32a, 33a ... patterned copper layer, 71, 72 ... Copper foil, 71a, 72a ... wiring pattern, 73, 74 ... conductive bumps, 75, 76 ... insulating layer, 83, 84 ... interlayer connection body filled with a conductive composition, 93, 94 ... interlayers filled with a conductive composition Connection body, 103, 104 ... Interlayer connection body by plating.

Claims (11)

At least three electrode plates;
A dielectric resin layer provided between each of the electrode plates, each being a plate substrate as a wiring board;
A wiring board with a built-in capacitor, comprising: an interlayer connection that penetrates through the dielectric resin layer and connects the electrode plates so as to be electrically separate nodes alternately in the layer direction. A wiring layer including the outermost one in the layer direction among the electrode plates;
An insulating layer laminated on a side of the wiring layer opposite to the side on which the dielectric resin layer is provided;
A second wiring layer laminated on the side of the insulating layer opposite to the side where the wiring layer is located;
2. The capacitor built-in wiring board according to claim 1, further comprising: a second interlayer connection body that connects the wiring layer and the second wiring layer through the insulating layer. 3.   3. The second interlayer connector connects the wiring layer in a portion that is not removed as a pattern and the second wiring layer in a portion that is not removed as a pattern. Capacitor built-in wiring board.   The said 2nd interlayer connection body is a shape which consists of an electroconductive composition, and has the axis | shaft which corresponds to a layer direction, and the diameter is changing in the direction of the said axis | shaft. Capacitor built-in wiring board.   The said 2nd interlayer connection body is a shape which consists of an electroconductive composition, and has the axis | shaft which corresponds to a layer direction, and the diameter does not change to the direction of the said axis | shaft. Capacitor built-in wiring board.   4. The capacitor built-in wiring board according to claim 3, wherein the second interlayer connection body is made of metal and has a columnar shape or a truncated cone shape having an axis coinciding with the layer direction.   3. The capacitor built-in wiring board according to claim 2, wherein the second interlayer connection body is made of a conductive composition and has a columnar shape whose axial direction coincides with the layer direction.   The said 2nd interlayer connection body consists of a metal, and is the shape of a truncated cone in which the direction of an axis corresponds to a layer direction, The inside of the said truncated cone is empty. Capacitor built-in wiring board.   3. The capacitor built-in wiring according to claim 2, wherein the second interlayer connection body uses a portion of the wiring layer which is the electrode plate as a connection portion in the interlayer connection to the second wiring layer. Board. Patterning the conductive layer provided on the dielectric resin sheet to be part of the electrode plate;
A second dielectric provided with a non-patterned conductive layer on the dielectric resin sheet provided with the patterned conductive layer so that a non-patterned conductive layer is disposed in the outermost layer direction. Laminating and integrating at least one body resin sheet;
An interlayer connector is formed through the integrated dielectric resin sheet and the second dielectric resin sheet so that the patterned conductive layers are electrically separated from each other in the layer direction alternately. Process,
In order to make the outermost conductive layer in the layer direction another part of the electrode plate, the outermost conductive layer in the layer direction and the patterned conductive layer are electrically separated in the layer direction alternately. And a step of patterning the outermost conductive layer in the layer direction. A method of manufacturing a wiring board with a built-in capacitor.   11. The method of manufacturing a wiring board with a built-in capacitor according to claim 10, further comprising a step of forming a layer having an insulating layer and a conductive layer on the pattern-formed outermost conductive layer in the layer direction. .

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