JP2007019495A - Improved-type electrode, internal layer, capacitor, electronic device, and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent shrinkage between an electrode inside thick-film dielectric and the dielectric and cracks in the dielectric caused by difference in temperature expansion coefficients. <P>SOLUTION: The method for imbedding a fired capacitor 200 on a thick-film foil comprises covering a whole dielectric with an enclosed electrode. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The technical field is embedded capacitors in printed wiring boards (PWB). More particularly, the technical field includes embedded capacitors in printed wiring boards made from thick film dielectrics and electrodes.

  By embedding a high capacitance density capacitor in the printed wiring board, the circuit size can be reduced and the circuit performance can be improved. Capacitors are usually stacked and embedded in panels connected by interconnect circuits, and stacking the panels forms a multilayer printed wiring board. The stacked panels are sometimes referred to as “inner panel”.

  Passive circuit components embedded in printed wiring boards formed by fired-on-foil techniques are known. A “separately fired-on-foil” capacitor is formed by depositing and drying at least one thick film dielectric layer on a metal foil substrate, followed by a thick film electrode material. Is deposited on the thick film capacitor dielectric layer and dried, followed by firing the capacitor structure under copper thick film firing conditions. Such a process is disclosed in US Pat. Nos. 5,099,086 and 5,047,942 (No. EL-0495) by Borland (simultaneous firing is divided).

  After firing, the resulting article can be laminated to a prepreg dielectric layer, and the metal foil is etched to form capacitors and any associated circuit electrodes to form an inner panel containing thick film capacitors Can do. The inner layer panel can then be laminated and interconnected to other inner layer panels to form a multilayer printed wiring board.

  The thick film dielectric material should have a high dielectric constant (K) after firing. A high-K thick film dielectric paste suitable for screen printing can be formed by mixing high dielectric constant powder ("functional phase") with glass powder and dispersing the mixture in a thick film screen printing medium. The glass may be glassy or crystalline depending on its composition.

  During firing of the thick film dielectric material, the glass component of the dielectric material softens and flows before reaching the peak firing temperature. While held at the peak temperature, it coalesces to encapsulate the functional phase and form a fired-on-foil capacitor structure. Thereafter, the glass can crystallize to precipitate any desired phase.

  Copper is a preferred material for forming the electrodes. A thick film copper electrode paste suitable for screen printing can be formed by mixing copper powder with a small amount of glass powder and dispersing the mixture in a thick film screen printing medium. However, due to the large difference in coefficient of thermal expansion (TCE) between thick film copper and thick film capacitor dielectrics and the difference in shrinkage during firing, tensile stress often appears in the dielectric just outside the periphery of the electrode. Arise. As a result of the tensile stress, a dielectric crack occurs at the periphery of the electrode, as shown in FIGS. 1A and 1B. Under extreme conditions, cracks can extend to the copper foil. Such cracks are undesirable because they can affect the long-term reliability of the capacitor. An alternative capacitor structure design that eliminates such cracking conditions would be advantageous.

US Patent Application Publication No. 2004/09999999 US Patent Application Publication No. 2004/0233611 US patent application Ser. No. 10 / 801,326 US patent application Ser. No. 10 / 801,257

  The inventors have provided a novel method of forming electrodes and inner layers, embedding fired-on-foil capacitors and forming printed wiring boards to avoid this crack in the dielectric. . Furthermore, the present inventors have developed an electrode, an inner layer, a capacitor, and a printed wiring board formed by such a method.

The first embodiment of the present invention is a method of forming an embedded capacitor, comprising:
Providing a metal foil, forming a dielectric layer on the metal foil, forming a first electrode on the entire dielectric layer and at least a part of the metal foil, firing the embedded capacitor And a method comprising etching a metal foil to form a second electrode.

  The second embodiment of the present invention is a method for producing a device, which is provided with a metal foil, a dielectric is formed on the metal foil, and a component side and a foil side of the metal foil are formed. Forming the first electrode on the entire dielectric and part of the metal foil, laminating the component side of the metal foil on at least one prepreg material, etching the metal foil to form the second electrode The method includes forming a first electrode, a dielectric, and a second electrode that include forming a capacitor.

  The present invention is further directed to various devices and capacitors formed using the methods described above and in the detailed description of the invention below. Furthermore, the present invention is directed to a device comprising a capacitor as detailed above and below in the detailed description of the invention.

  In the detailed description, reference is made to the drawings.

  According to common practice, the various features of the drawings are not necessarily drawn to scale. The dimensions of the various features may be expanded or reduced to more clearly illustrate embodiments of the present invention.

  The first embodiment is a method of creating a fired capacitor structure on a foil with a single dielectric layer, including providing a metal foil, forming a capacitor dielectric on the metal foil, Forming a first electrode on part or all of the metal foil and firing the capacitor structure under copper thick film firing conditions.

  According to the second embodiment, a method for producing a fired capacitor structure on a foil with a single dielectric layer is provided by providing a metal foil, forming an insulating separation layer on the metal foil, and an insulating separation layer. Forming a capacitor dielectric on the metal foil within the enclosure, forming a first electrode on the entire dielectric and part or all of the insulating isolation layer, and the capacitor under copper thick film firing conditions Firing the structure.

  According to a third embodiment, which is a modification of the second embodiment, a method for producing a single dielectric layer fired capacitor structure on foil includes providing a metal foil and forming an insulating isolation layer on the metal foil. Forming a capacitor dielectric on the metal foil within the enclosure created by the insulating isolation layer, first over the entire dielectric and part or all of the insulating isolation layer and part of the metal foil. Forming electrodes and firing the capacitor structure under copper thick film firing conditions.

  According to the fourth embodiment, a method for creating a fired capacitor structure on a foil of a bi-dielectric layer is provided by providing a metal foil, forming an insulating separation layer on the metal foil, and an insulating separation layer. Forming a capacitor dielectric on the metal foil within the enclosure, forming a first electrode on the entire dielectric, part or all of the isolation layer and part of the metal foil, copper thick film firing Firing the first capacitor structure under conditions, forming a second capacitor dielectric layer on the first electrode, part of the second capacitor dielectric layer, part of the insulating isolation layer and part of the foil. Forming a second electrode thereon and firing the structure under copper thick film firing conditions.

  According to the fifth embodiment, a method for producing a fired bi-dielectric layer capacitor structure on foil includes providing the article of the first embodiment, and forming an insulating isolation layer on the first electrode and surrounding the area. Forming a first electrode in an enclosed area defined by the isolation layer; forming a second capacitor dielectric layer over a portion of the isolation layer; and the entire second capacitor dielectric layer; Forming a second electrode covering a portion of the insulating isolation layer, and firing the structure under copper thick film firing conditions.

  According to another embodiment, the method for creating an on-foil fired embedded capacitor inner layer is obtained by laminating the component side of the on-foil fired capacitor structure on the prepreg material and etching the metal foil in the case of the first embodiment. Includes forming first and second electrodes, or in the case of the second embodiment, first, second and third electrodes.

  According to another embodiment, a method of making a device comprising a fired embedded capacitor on foil, including but not limited to a multilayer printed wiring board, laminates an inner layer of fired embedded capacitor on foil to an additional prepreg material, and Forming at least one via through the prepreg material to connect with at least one electrode.

  According to the above embodiment, the electrode covers the entire dielectric and encapsulates the dielectric. The encapsulating electrode applies compressive stress over the entire range of the dielectric so that tensile stress is avoided. As a result, it is possible to manufacture a fired capacitor on a foil without cracks, and it is possible to embed a capacitor without cracks inside a multilayer printed wiring board. Further, in the above embodiment, the isolation layer can be used as a barrier layer to protect the capacitor dielectric from the etch chemistry. Thereby, the capacitor reliability is improved.

  Although the present invention will be described in terms of printed wiring board formation, embodiments of the present invention are useful in a variety of devices including interposers, printed wiring boards, multichip modules, area array packages, system on packages, and system in packages. It should be understood by those skilled in the art.

  The present invention is further a method of making a device, comprising providing a metal foil having a component side and a foil side, forming an insulating separation layer on the metal foil, and forming a dielectric on the metal foil The dielectric is surrounded by the insulating isolation layer and is in contact with the insulating isolation layer, and the first electrode is formed on the entire dielectric, part of the insulating isolation layer, and part of the metal foil. Forming an encapsulating electrode, laminating a component side of the metal foil on at least one prepreg material, etching the metal foil to form a second electrode, The method is such that one electrode, a dielectric, and a second electrode form a capacitor.

  Another embodiment of the present invention is a device comprising at least one capacitor embedded in at least one layer of dielectric material, the capacitor comprising a metal foil, at least one layer of dielectric material, and a dielectric A first electrode formed from a printed electrode covering the entire first layer of material and a portion of the metal foil; a second layer of dielectric material adjacent to the first electrode; A device comprising: a first layer of dielectric material; and a second electrode adjacent to the second layer of dielectric material.

  In another embodiment, the invention comprises a device comprising at least one capacitor embedded in at least one layer of dielectric material, the capacitor comprising a metal foil, at least one layer of dielectric material, An insulating isolation layer; a first electrode formed from a printed electrode covering the entire first layer of dielectric material, a portion of the insulating isolation layer, and a portion of the metal foil; the first electrode and the insulating isolation A device comprising: a second layer of dielectric material adjacent to a layer; and a second electrode formed from the metal foil and adjacent to the first layer of dielectric material and the second layer of dielectric material. To do.

  Those skilled in the art will appreciate the above and other advantages of the present invention as well as the benefits of various additional embodiments when reading the detailed description of the embodiments below.

  FIGS. 2A to 2K produce a multilayer printed wiring board 2000 (FIG. 2K) having an embedded capacitor having a fired-on-foil capacitor on a metal foil design, and a printed electrode covering the entire dielectric and part of the metal foil. A first method is shown. In this description, two embedded capacitors are illustrated as formed in FIGS. However, one, two, three, or more capacitors can be formed on the foil by the methods described herein. The following description is directed to the formation of only one of the illustrated capacitors for the sake of brevity. 2A to 2D and 2F to 2I and 2K are front sectional views. FIG. 2E is a top view of FIG. 2D. FIG. 2J is a bottom view of FIG. 2I.

  In FIG. 2A, a metal foil 210 is provided. Metal foil 210 may be of a type commonly available in the art. For example, the metal foil 210 may be copper, copper-invar-copper, invar, nickel, nickel-coated copper, or other metals, and alloys having a melting point above the firing temperature for thick film pastes. Suitable foils include mostly copper foils, such as reverse processed copper foils, double processed copper foils, and other copper foils commonly used in the multilayer printed wiring board industry. The thickness of the metal foil 210 may be in the range of about 1 to 100 microns, for example. Other thickness ranges include 3-75 microns, more specifically 12-36 microns. These thickness ranges correspond to about 1/3 ounce and 1 ounce copper foil.

  In some embodiments, the foil 210 can be pretreated by applying an underprint 212 to the foil 210 and firing. The underprint 212 is shown as a surface coating in FIG. 2A and may be a relatively thin layer that adheres to the component side surface of the foil 210. Underprint 212 adheres well to metal foil 210 and the layer deposited on underprint 212. For example, the underprint 212 can be formed from a paste applied to the foil 210 that is fired at a temperature below the melting point of the foil 210. The underprint paste can be printed as an unlimited (open) coating that covers the entire surface of the foil 210 or can be printed over selected areas of the foil 210. It is generally more economical to print over selected areas of the foil 210 than to print the underprint paste over the entire foil 210. However, when oxygen-doped firing is used with copper foil 210, it may be preferable to cover the entire surface of foil 210 because the glass content in the underprint retards oxidative corrosion of copper foil 210.

  One thick film copper paste suitable for use as an underprint (disclosed in U.S. Patent No. 5,047,097, Borland et al., Incorporated herein by reference) has the following composition ( (Mass ratio).

In this composition,
Glass A contains lead germanate of composition Pb ₅ Ge ₃ O ₁₁ ,
The medium is ethyl cellulose N200 11%
Including TEXANOL® 89%,
Surfactants include VARIQUAT® CC-9 NS surfactant.

  TEXANOL (registered trademark) is a product of Eastman Chemical Co. VARIQUAT® CC-9 NS is available from Ashland Inc. Is available from

  Capacitor dielectric material 220 is deposited over the underprint 212 of the pretreated foil 210 to form a first capacitor dielectric material layer 220 as shown in FIG. 2A. For example, the capacitor dielectric material may be a thick film capacitor paste that is screen printed or stencil printed on the foil 210. The first capacitor dielectric material layer 220 is then dried. In FIG. 2B, a second capacitor dielectric material layer 225 is then applied and dried. In an alternative embodiment, a single layer of capacitor dielectric material can be deposited to a thickness equal to the two layers 220, 225 in a single screen printing step. One thick film capacitor material suitable for use in firing on foil embodiments (disclosed in U.S. Pat. No. 5,087,047, Borland et al., Incorporated by reference) has the following composition ( (Mass ratio).

In this composition,
Glass A contains lead germanate of composition Pb ₅ Ge ₃ O ₁₁ ,
Glass B contains Pb ₄ BaGe _1.5 Si _1.5 O ₁₁ ,
Glass C includes Pb ₅ GeSiTiO ₁₁ ,
The medium is ethyl cellulose N200 11%
Containing 89% TEXANOL® solvent,
The oxidizing agent is barium nitrate powder 84%
Contains 16% medium.

  In FIG. 2C, a conductive material layer 230 is formed over the entire second capacitor dielectric material layer 225 and a portion of the metal foil at the periphery of the capacitor dielectric to form the first electrode; Dried. For example, the conductive material layer 230 can be formed by screen printing a thick metal paste on the second capacitor dielectric material layer 225. The paste used to form the underprint 212 is also suitable for forming the conductive material layer 230.

  The first capacitor dielectric material layer 220, the second capacitor dielectric material layer 225, and the conductive material layer 230 forming the first electrode are then co-fired and the resulting structure is sintered together. The FIG. 2D shows a front cross section of the fired structure. Since the boundary between capacitor dielectric layers 220 and 225 is effectively removed during co-firing, firing results in a single capacitor dielectric 228 formed from capacitor dielectric layers 220 and 225. A top electrode 232 encapsulating the capacitor dielectric layer 228 is also obtained as a result of the co-firing step. The surface area of the capacitor dielectric layer 228 is smaller than the surface area of the conductive material layer 232 when viewed from the top view shown in FIG. 2E. When fired on copper foil in nitrogen for about 10 minutes at a peak temperature of about 900 ° C., the resulting capacitor dielectric 228 can have a dielectric constant of about 3000 and a dissipation factor of about 2.5%. Alternate firing conditions may be used to obtain different material properties for the capacitor dielectric 228.

  In FIG. 2F, the foil is laminated with the prepreg material 240 with the first electrode 232 facing the prepreg material and covering the capacitor dielectric 228. For example, lamination can be performed using FR4 prepreg in a standard printed wiring board process. In one embodiment, 106 epoxy prepregs can be used. Suitable lamination conditions are, for example, 185 ° C., 208 psig, 1 hour in a vacuum chamber evacuated to 28 inches of mercury. A foil 250 can be attached to the opposite side of the laminate material 240 to provide a surface for making circuit components. A silicone rubber press pad and a smooth PTFE filled glass release sheet can be contacted with the foils 210 and 250 to prevent the epoxy resin from adhering the laminate together. Laminate material 240 may be, for example, standard epoxy resin, high Tg epoxy resin, polyimide, polytetrafluoroethylene, cyanate ester resin, filled resin system, BT epoxy resin, and other resins and laminates that provide insulation between circuit layers Any type of dielectric material such as a plate may be used.

  Referring to FIG. 2G, after lamination, a photoresist is applied to foil 210 and foil 250. The photoresist is imaged and developed to form photoresist patterns 260 and 262.

  Referring to FIG. 2H, foils 210 and 250 are etched and photoresists 260 and 262 are stripped using, for example, standard printed wiring board processing conditions to form the article shown in FIG. 2I. By etching, a groove 215 is formed in the foil 210, and a second capacitor foil electrode 218 separated from the remaining portion of the foil and the first electrode 232 is obtained. Second capacitor foil electrode 218, dielectric 228, and first electrode 232 form capacitor 200. The etching process also produces copper pads 217 and 219 from the foil 210 that can serve as pads for vias to connect to the capacitor electrode 232. Circuit components 252, 254, 256 are also formed from foil 250.

  FIG. 2J is a bottom view of the article shown in FIG. 2I. In FIG. 2J, two capacitors 200 are shown as formed by etching the grooves 215 in the foil 210. However, this number is exemplary and any number of capacitors can be formed from the foil in accordance with the embodiments discussed herein. Although FIG. 2J shows two similarly configured capacitors 200, this embodiment allows the formation of capacitors of different sizes and / or shapes.

  Referring to FIG. 2K, additional laminate and copper foil pairs can be laminated to the article shown in FIG. 2I, and microvias 2010 and 2020 can be drilled and plated. Photoresist can be added to the external copper layer, imaged and developed. Then, using standard printed wiring conditions, the outer layer copper foil is etched and the remaining photoresist is stripped to complete the printed wiring board 2000.

  The described manufacturing process is suitable for a four-metal layer printed wiring board 2000 shown in FIG. 2K with an embedded capacitor 200 in a layer adjacent to the outer layer of the printed circuit board 2000. However, the manufacturing order can be changed and the printed wiring board can have any number of layers. Also, the embedded capacitor according to this embodiment can be located in any layer in the multilayer printed circuit board. A mechanical perforated plated through-hole via can also be used as a replacement for the microvia 2020 to connect the circuit with the capacitor foil electrode 232.

  3A-3J includes a multilayer printed wiring board 3000 (FIG. 3J) having an embedded capacitor having a fired-on-foil capacitor on a metal foil design, and a printed electrode covering the entire dielectric and part of the insulating isolation layer. A second method of manufacturing is shown. In this description, two embedded capacitors are illustrated as formed in FIGS. However, one, two, three, or more capacitors can be formed on the foil by the methods described herein. The following description is directed to the formation of only one of the illustrated capacitors for the sake of brevity. 3A and 3C-3J are front cross-sectional views. FIG. 3B is a top view of FIG. 3A.

  In FIG. 3A, a metal foil 310 is provided. The metal foil 310 may be of the type generally described in the first embodiment, and may be pretreated by attaching an underprint 312 to the foil 310 and firing the same as described in the first embodiment. it can.

  An insulating isolation layer 313 is deposited over the underprint 312 thereby forming an enclosure. A suitable insulating separation layer may be an insulating ceramic filled glass composition that does not crack when cofired with copper under copper thick film firing conditions. A top view of the resulting article is shown in FIG. 3B. Referring to FIG. 3C, the capacitor dielectric material described in the first embodiment is deposited in the enclosed area formed by the insulating isolation layer 313 on the underprint 312 of the foil 310 after the pretreatment, A first capacitor dielectric material layer 320 is formed. The first capacitor dielectric material layer 320 is then dried. A second capacitor dielectric material layer 325 is then applied and dried. In an alternative embodiment, a single layer of capacitor dielectric material can be deposited to a thickness equal to the two layers 320, 325 in a single screen printing step.

  In FIG. 3D, a conductive material layer 330 is formed over the entire second dielectric material layer 325 and a portion of the insulating isolation layer 313 and dried. For example, the conductive material layer 330 can be formed by screen printing the thick film metal paste described in the first embodiment on the second dielectric material layer 325.

  The insulating isolation layer 313, the first capacitor dielectric material layer 320, the second capacitor dielectric material layer 325, and the conductive material layer 330 forming the first electrode are then co-fired and the resulting structure is sintered together. The FIG. 3E shows a front cross section of the fired structure. Since the boundary between capacitor dielectric layers 320 and 325 is effectively removed during co-firing, firing results in a single capacitor dielectric 328 formed from capacitor dielectric layers 320 and 325. An insulating isolation layer 314 bonded to a single capacitor dielectric 328 is obtained as a result of firing. A top electrode 332 encapsulating the capacitor dielectric layer 328 is also obtained as a result of the co-firing step. The surface area of the capacitor dielectric layer 328 is smaller than the surface area of the conductive material layer 332. When fired on copper foil in nitrogen for about 10 minutes at a peak temperature of about 900 ° C., the resulting capacitor dielectric 328 can have a dielectric constant of about 3000 and a dissipation factor of about 2.5%. Alternative firing conditions may be used to obtain different material properties for the capacitor dielectric 328.

  In FIG. 3F, the foil is laminated with the prepreg material 340 with the first electrode 332 facing the prepreg material and covering the capacitor dielectric 328. Lamination can be performed with the materials and processes described in the first embodiment. A foil 350 can be attached to the opposite side of the laminate material 340 to provide a surface for making circuit components.

  Referring to FIG. 3G, after lamination, a photoresist is applied to foil 310 and foil 350. The photoresist is imaged and developed to form a photoresist pattern 360. In this manufacturing sequence, the copper foil 350 is typically patterned during the final outer layer processing, so the photoresist 362 on the foil 350 may not be imaged and developed at this stage.

  The foil 310 is etched and the photoresists 360 and 362 are stripped using, for example, standard printed wiring board processing conditions to form the article shown in FIG. 3H. Etching forms a trench 316 in the foil 310, resulting in a defined second capacitor foil electrode 318 that is separated from the rest of the foil without the need for etch chemistry to contact the capacitor dielectric. Second capacitor foil electrode 318, dielectric 328, and first electrode 332 form capacitor 300.

  Referring to FIG. 3I, additional laminate 345 and copper foil 370 may be laminated to the article shown in FIG. 3H. Referring to FIG. 3J, microvias 3010 and through-hole vias 3020 are drilled and plated. Photoresist can be added to the outer copper layers 350 and 370, imaged and developed. Then, as shown in FIG. 3J, using standard printed wiring conditions, the outer layer copper foil is etched to create a circuit 385, and the remaining photoresist is stripped to complete the circuit board 3000.

  The described manufacturing process is suitable for a three-metal layer printed wiring board comprising an embedded capacitor 300 in the middle of the printed circuit board 3000. However, the manufacturing order can be changed, and the printed wiring board 3000 can have any number of layers. The embedded capacitor according to the present embodiment can be located in any layer in the multilayer printed circuit board.

  4A-4L include an embedded capacitor having a fired-on-foil capacitor, the printed electrode covers the entire dielectric, a portion of the insulating isolation layer, and a portion of the metal foil, and the capacitor dielectric is an etching chemical. 4 illustrates an alternative method of manufacturing a multilayer printed wiring board 4000 (FIG. 4L) where the isolation layer also acts as a barrier layer so that it is protected from In this description, two embedded capacitors are illustrated as formed in FIGS. However, one, two, three, or more capacitors can be formed on the foil by the methods described herein. The following description is directed to the formation of only one of the illustrated capacitors for the sake of brevity. 4A and 4C to 4E and 4G to 4I and 4K to 4L are front sectional views. 4B is a top view of FIG. 4A, FIG. 4F is a bottom view of FIG. 4E, and FIG. 4J is a bottom view of FIG. 4I.

  In FIG. 4A, a metal foil 410 is provided. The metal foil 410 may be of the type generally described in the first embodiment, and may be pretreated by attaching an underprint 412 to the foil 410 and firing it, as described in the first embodiment. it can.

  An insulating isolation layer 413 is deposited over the underprint 412 thereby forming an enclosure. A suitable insulating separation layer may be an insulating ceramic filled glass composition that does not crack when cofired with copper under copper thick film firing conditions. A top view of the resulting article is shown in FIG. 4B. Referring to FIG. 4C, the capacitor dielectric material described in the first embodiment is deposited in the enclosed area formed by the insulating separation layer 413 on the underprint 412 of the foil 410 after the pretreatment, A first capacitor dielectric material layer 420 is formed. The first capacitor dielectric material layer 420 is then dried. A second capacitor dielectric material layer 425 is then applied and dried. In an alternative embodiment, a single layer of capacitor dielectric material can be deposited to a thickness equal to the two layers 420, 425 in a single screen printing step.

  In FIG. 4D, a conductive material layer 430 is formed over the entire second dielectric material layer 425, a portion of the insulating isolation layer 413, and a portion 410 of the metal foil and dried. For example, the conductive material layer 430 can be formed by screen printing the thick film metal paste described in the first embodiment on the second dielectric material layer 425.

  The insulating isolation layer 413, the first capacitor dielectric material layer 420, the second capacitor dielectric material layer 425, and the conductive material layer 430 forming the first electrode are then fired together and the resulting structure is sintered together. The FIG. 4E shows a front cross section of the fired structure. Since the boundary between capacitor dielectric layers 420 and 425 is effectively removed during co-firing, firing results in a single capacitor dielectric 428 formed from capacitor dielectric layers 420 and 425. An insulating isolation layer 414 is formed from the isolation layer 413 and is bonded to a single capacitor dielectric 428. A top electrode 432 encapsulating the capacitor dielectric layer 428 is also obtained as a result of the co-firing step. A top view of the article of FIG. 4E is shown in FIG. 4F. The surface area of the capacitor dielectric layer 428 is smaller than the surface area of the conductive material layer 432. When fired on copper foil in nitrogen for about 10 minutes at a peak temperature of about 900 ° C., the resulting capacitor dielectric 428 can have a dielectric constant of about 3000 and a dissipation factor of about 2.5%. Alternate firing conditions can be used to obtain different material properties for the capacitor dielectric 428.

  In FIG. 4G, the foil is laminated with prepreg material 440 with the first electrode 432 facing the prepreg material and covering the capacitor dielectric 428. Lamination can be performed with the materials and processes described in the first embodiment. A foil 450 can be attached to the opposite side of the laminate material 440 to provide a surface for making circuit components.

  Referring to FIG. 4H, after lamination, a photoresist is applied to foil 410 and foil 450. The photoresist is imaged and developed to form a photoresist pattern 460. In this manufacturing sequence, the copper foil 450 is typically patterned during the final outer layer processing, so the photoresist 462 on the foil 450 may not be imaged and developed at this stage.

  The foil 410 is etched and the photoresists 460 and 462 are stripped using, for example, standard printed wiring board processing conditions to form the article shown in FIG. 4I. Etching forms a groove 415 in the foil 410, resulting in a capacitor foil electrode 418 that is separated from the remainder of the foil. Second capacitor foil electrode 418, dielectric 428, and first electrode 432 form capacitor 400. A bottom view of the resulting article is shown in FIG. 4J.

  Referring to FIG. 4K, additional laminate 445 and copper foil 470 can be laminated to the article shown in FIG. 4I. Referring to FIG. 4L, through-hole vias 4010 and 4020 are drilled and plated. Photoresist can be added to the outer copper layers 450 and 470, imaged and developed. Then, using standard printed wiring conditions, the outer layer copper foil is etched to create the circuit component 485, and the remaining photoresist is stripped to complete the circuit board 4000.

  The described manufacturing process is suitable for a three-metal layer printed wiring board comprising an embedded capacitor 400 in the middle of the printed circuit board 4000. However, the manufacturing order can be changed and the printed wiring board 4000 can have any number of layers. The embedded capacitor according to the present embodiment can be located in any layer in the multilayer printed circuit board.

  FIGS. 5A to 5O include an embedded capacitor having a fired bi-dielectric layer capacitor on a foil on a metal foil design, and the printed first electrode includes the entire first dielectric, a part of the isolation insulating layer, and the metal foil. A method of manufacturing a multilayer wiring board 5000 (FIG. 5O) that covers a portion and a second printed electrode covers the entire second dielectric layer, a portion of the insulating isolation layer, and a portion of the metal foil. Show. In this description, two embedded capacitors are illustrated as formed in FIGS. However, one, two, three, or more capacitors can be formed on the foil by the methods described herein. The following description is directed to the formation of only one of the illustrated capacitors for the sake of brevity. 5A, 5C-5D, 5F-5L, and FIGS. 5N-5O are front cross-sectional views. 5B is a top view of FIG. 5A, FIG. 5E is a top view of FIG. 5D, and FIG. 5M is a bottom view of FIG. 5L.

  In FIG. 5A, a metal foil 510 is provided. The metal foil 510 may be of the type generally described in the first embodiment, and may be pretreated by attaching an underprint 512 to the foil 510 and firing the same as described in the first embodiment. it can.

  An insulating isolation layer 513 is deposited over the underprint 512, thereby forming an enclosure. A suitable insulating separation layer may be an insulating ceramic filled glass composition that does not crack when cofired with copper under copper thick film firing conditions. A top view of the resulting article is shown in FIG. 5B. Referring to FIG. 5C, the capacitor dielectric material described in the first embodiment is deposited in the enclosed area formed by the insulating isolation layer 513 on the underprint 512 of the foil 510 after pretreatment, A first capacitor dielectric material layer 520 is formed. The first capacitor dielectric material layer 520 is then dried. A second capacitor dielectric material layer 525 is then applied and dried. In an alternative embodiment, a single layer of capacitor dielectric material can be deposited to a thickness equal to the two layers 520, 525 in a single screen printing step.

  In FIG. 5D, the conductive material layer 530 is over the entire second dielectric material layer 525, a portion of the insulating isolation layer 513, a portion of the metal foil 510, and another portion of the insulating isolation layer 513. Formed and dried. For example, the conductive material layer 530 can be formed by screen printing the thick film metal paste described in the first embodiment on the second dielectric material layer 525. A top view of the resulting article is shown in FIG. 5E.

  Next, the insulating isolation layer 513, the first capacitor dielectric material layer 520, the second capacitor dielectric material layer 525, and the conductive material layer 530 forming the first electrode are simultaneously fired, and the resulting structure is combined. FIG. 5F shows a front cross section of the fired structure. Since the boundary between capacitor dielectric layers 520 and 525 is effectively removed during co-firing, firing results in a single capacitor dielectric 528 formed from capacitor dielectric layers 520 and 525. An insulating isolation layer 514 is formed from the isolation layer 513 and is bonded to a single capacitor dielectric 528. A top electrode 532 encapsulating the capacitor dielectric layer 528 is also obtained as a result of the co-firing step. The surface area of the capacitor dielectric layer 528 is smaller than the surface area of the conductive material layer 532. When fired on copper foil in nitrogen for about 10 minutes at a peak temperature of about 900 ° C., the resulting capacitor dielectric 528 can have a dielectric constant of about 3000 and a dissipation factor of about 2.5%. Alternate firing conditions may be used to obtain different material properties for the capacitor dielectric 528.

  Referring to FIG. 5G, a capacitor dielectric material is deposited on the first electrode 532 to form a capacitor dielectric layer 534. A second capacitor dielectric layer 535 is deposited over the first capacitor dielectric layer 534 and dried. In an alternative embodiment, a single layer of capacitor dielectric can be deposited to a thickness equal to the two layers 534 and 535. A conductive layer 536 is formed over the entire capacitor dielectric layer 535. As shown in the front view of FIG. 5H, the conductive layer 536 extends over the capacitor dielectric 535 and partially extends over the insulating isolation layer 514 and the foil 510.

  The capacitor dielectric layer 534, the second capacitor dielectric layer 535, and the conductive layer 536 are then cofired under copper thick film firing conditions, and the resulting structure is sintered together. FIG. 5I shows a front cross section of the fired structure. Since the boundary between capacitor dielectric layers 534 and 535 is effectively removed during cofiring, firing results in a single capacitor dielectric 538 formed from capacitor dielectric layers 534 and 535. As a result of firing, a top electrode 539 that encapsulates the capacitor dielectric layer 538 is also obtained. When fired on copper foil in nitrogen for about 10 minutes at a peak temperature of about 900 ° C., the resulting capacitor dielectric 538 can have a dielectric constant of about 3000 and a dissipation factor of about 2.5%. Alternate firing conditions may be used to obtain different material properties for the capacitor dielectric 538.

  In FIG. 5J, the foil 510 is laminated with the prepreg material 540 with the second electrode 539 facing the prepreg material and covering the dielectric 538. For example, lamination can be performed using the materials and processes described in the first embodiment. A foil 550 may be attached to the opposite side of the laminate material 540 to provide a surface for creating circuit components.

  After lamination, a photoresist is applied to the foils 510 and 550. The photoresist is imaged and developed to form a patterned photoresist 560 shown in FIG. 5K. In this manufacturing sequence, the copper foil 550 is typically patterned during the final outer layer processing, so the photoresist 562 on the foil 550 may not be imaged and developed at this stage.

  The foil 510 is etched and the photoresists 560 and 562 are stripped using standard printed wiring board processing materials and conditions to form the article shown in FIG. 5L. By etching, a groove 515 is formed in the foil 510 to form a capacitor foil electrode 518 separated from the remaining portion of the foil and the first electrode 532. The first capacitor electrode 532, the second capacitor electrode 539, the capacitor foil electrode 518, the first dielectric 528, and the second dielectric 538 form the structure of the bi-dielectric layer capacitor 500. A bottom view of the resulting article is shown in FIG. 5M.

  Referring to FIG. 5N, additional laminate 545 and copper foil 570 can be laminated to the article shown in FIG. 5L. Through-hole vias 5010 and 5020 can then be drilled and plated. A photoresist can then be applied to the outer copper foils 510 and 570. The photoresist is imaged and developed, the copper foil is etched, the remaining photoresist is stripped, and the external circuit components are completed, resulting in the article shown in FIG. The circuit board can be subjected to additional processing such as anti-fogging coating to complete the circuit board 5000.

  The described manufacturing process is suitable for a three-metal layer printed wiring board having an embedded capacitor 500 in the middle layer of the printed circuit board 5000. However, the manufacturing order can be changed and the printed wiring board 5000 can have any number of layers. The embedded capacitor according to the present embodiment can be located in any layer in the multilayer printed circuit board.

  FIGS. 6A-6K comprise an embedded capacitor having a fired bi-dielectric layer capacitor on foil on a metal foil design, the printed first electrode covering the entire first dielectric layer and part of the metal foil, FIG. 6 illustrates another alternative method of manufacturing a multilayer wiring board 6000 (FIG. 6K) in which a second printed electrode covers the entire second dielectric layer and a portion of the insulating barrier layer. In this description, two embedded capacitors are illustrated as formed in FIGS. However, one, two, three, or more capacitors can be formed on the foil by the methods described herein. The following description is directed to the formation of only one of the illustrated capacitors for the sake of brevity. 6A-6B, 6D-6H, 6J, and 6K are front cross-sectional views. 6C is a top view of FIG. 6B, and FIG. 6I is a bottom view of FIG. 6H.

  In FIG. 6A, an article generally represented in FIG. 2D is provided. An insulating isolation layer 633 is deposited over the electrode 632 covering the entire capacitor dielectric 628 and dried. A top view of the resulting article is shown in FIG. 6C. The insulating separation layer 633 forms an enclosure on the encapsulating electrode 632. A suitable insulating separation layer may be an insulating filled glass composition that does not crack when cofired with copper under copper thick film firing conditions. In FIG. 6D, the capacitor dielectric material described in the first embodiment is deposited on the first electrode 632 and in the enclosure formed by the insulating isolation layer 633 to form the capacitor dielectric layer 634. A second capacitor dielectric layer 635 is deposited over the first capacitor dielectric layer 634 and dried. In an alternative embodiment, a single layer of capacitor dielectric can be deposited to a thickness equal to the two layers 634,635. A conductive layer 636 is formed over the entire capacitor dielectric layer 635 using the conductive materials described in the first embodiment. Conductive layer 636 extends over capacitor dielectric 635 and partially extends over isolation layer 633.

  The insulating isolation layer 633, capacitor dielectric layer 634, second capacitor dielectric layer 635, and conductive layer 636 are then cofired under copper thick film firing conditions, and the resulting structure is sintered together. FIG. 6E shows a front cross section of the fired structure. Since the boundary between capacitor dielectric layers 634 and 635 is effectively removed during co-firing, firing results in a single capacitor dielectric 638 formed from capacitor dielectric layers 634 and 635. As a result of firing, an insulating separation layer 637 that does not crack during the firing process is obtained. A top electrode 639 encapsulating the capacitor dielectric layer 638 is also obtained as a result of the co-firing step. When fired on copper foil in nitrogen for about 10 minutes at a peak temperature of about 900 ° C., the resulting capacitor dielectric 638 can have a dielectric constant of about 3000 and a dissipation factor of about 2.5%. Alternate firing conditions can also be used to obtain different material properties for the capacitor dielectric 638.

  In FIG. 6F, the foil 610 is laminated with the prepreg material 640 with the second electrode facing the prepreg material and covering the dielectric 638. For example, lamination can be performed using the materials and processes described in the first embodiment. A foil 650 can be attached to the opposite side of the laminate material 640 to provide a surface for creating circuit components.

  After lamination, a photoresist is applied to the foils 610 and 650. The photoresist is imaged and developed to form the patterned photoresist 660 shown in FIG. 6G. In this manufacturing sequence, the copper foil 650 is typically patterned during the final outer layer processing, so the photoresist 662 on the foil 650 may not be imaged and developed at this stage.

  The foil 610 is etched and the photoresists 660 and 662 are stripped using standard printed wiring board processing materials and conditions to form the article shown in FIG. 6H. The etching forms a groove 615 in the foil 610 to form a third capacitor foil electrode 618 that is separated from the remaining portion of the foil and the first electrode 632. The first capacitor electrode 632, the second capacitor electrode 639, the third capacitor electrode 618, the first dielectric 628, and the second dielectric 638 form the structure of the two-dielectric layer capacitor 600.

  FIG. 6I is a bottom view of the article shown in FIG. 6H. In FIG. 6I, two capacitor structures 600 are illustrated as formed by etching grooves 615 in foil 610. However, this number is exemplary and any number of capacitors can be formed in accordance with the embodiments discussed herein. FIG. 6I shows two capacitors 600 with a similar configuration, but this embodiment allows for the configuration of capacitors of different sizes and / or shapes.

  Referring to FIG. 6J, additional laminate 645 and copper foil 670 can be laminated to the article shown in FIG. 6H. The through-hole via 6010 and microvia 6020 can then be drilled and plated. A photoresist can then be applied to the outer layer copper foils 610 and 670. The photoresist is imaged and developed, the copper foil is etched, the remaining photoresist is stripped, and the external circuit components are completed, resulting in the article shown in FIG. 6K. The board can be subjected to additional processing such as anti-fogging coating to complete the circuit board 6000.

  The described manufacturing process is suitable for a three-metal layer printed wiring board comprising an embedded capacitor 600 in the middle of the printed circuit board 6000. However, the manufacturing order can be changed and the printed wiring board 6000 can have any number of layers. The embedded capacitor according to the present embodiment can be located in any layer in the multilayer printed circuit board.

  In the above embodiments, the thick film paste can include ceramic, glass, metal, or other solid finely divided particles. The particles can have a size on the order of 1 micron or less and can be dispersed in an “organic medium” comprising a polymer dissolved in a mixture of a dispersant and an organic solvent.

  The thick film dielectric material can have a high dielectric constant (K) after firing. For example, a high K thick film dielectric can be formed by mixing a high dielectric constant powder (“functional phase”) with a dopant and glass powder and dispersing the mixture in a thick film screen printing medium. During firing, before reaching the peak firing temperature, the glass component of the capacitor material softens and flows, coalesces, encapsulates the functional phase, and forms a capacitor composite after firing.

High-K functional phases include crystalline barium titanate (BT), lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), lead magnesium niobate (PMN), and barium strontium titanate (BST). Includes perovskites of the general formula ABO ₃ . Since barium titanate is relatively unaffected by the reduced state used in the firing process, barium titanate is advantageous for use in copper foil firing applications.

Typically, the thick glass component of the dielectric material is inert to the high K functional phase and essentially serves to adhesively bond the composites together and bond the capacitor composite to the substrate. It is preferable to use a small amount of glass so that the dielectric constant of the high K functional phase is not excessively weakened. For example, the glass may be calcium aluminum borosilicate, lead barium borosilicate, magnesium aluminum silicate, rare earth borates, or other similar compositions. The use of glass having a relatively high dielectric constant is preferred. This is because the dilution effect is not so remarkable and the high dielectric constant of the composite can be maintained. Lead germanate of composition Pb ₅ Ge ₃ O ₁₁ is a ferroelectric glass having a dielectric constant of about 150 and is therefore suitable. A modified version of lead germanate is also suitable. For example, lead may be partially replaced with barium and germanium may be partially replaced with silicon, zirconium, and / or titanium.

  The paste used to form the electrode layer can be based on a metal powder of a copper, nickel, silver, silver-palladium composition, or a mixture of these compounds. A copper powder composition is preferred.

  The desired sintering temperature is determined by the metal substrate melting temperature, the electrode melting temperature, and the chemical and physical properties of the dielectric composition. For example, one set of sintering conditions suitable for use in the above embodiment is a nitrogen firing process having a peak temperature of about 900 ° C. and a residence time of 10 minutes.

  The above description of the invention illustrates and describes the present invention. Further, although this disclosure shows and describes only selected preferred embodiments of the present invention, the present invention can be used in various other combinations, modifications, and environments, and is described herein. It should be understood that changes or modifications within the scope of the expressed inventive concept, changes or modifications equivalent to the above teachings, and / or changes or modifications within the skill or knowledge of the related art are possible. .

  The above-described embodiments are illustrative of the best method of practicing the invention, and those skilled in the art will need the invention in such or other embodiments, in particular applications or applications of the invention. It can be used with various changes. Accordingly, the description is not intended to limit the invention to the form disclosed herein. Furthermore, the appended claims are intended to include alternative embodiments not explicitly defined in the detailed description.

  A PWB (printed wiring board) substrate was fabricated having embedded capacitors in which the screen printed electrodes completely encapsulate the dielectric. A four-layer design with ceramic capacitors on layer 2 (L2) was used for PWB construction. First, an inner layer containing L2 / L3 was created and then laminated with layers 1 and 4 to complete a PWB laminate. A 1 oz NT-TOI copper foil was used at L2. The TOI foil is a one-sided Zn-free treated electrode deposited foil and was designed to provide high bond strength to a wide range of organic substrates. Therefore, it was not necessary to subject the inner layer with capacitors to an oxide process to compensate for sufficient adhesion to the 1080 FR4 prepreg used to build the plate. To avoid causing mechanical damage to the ceramic capacitor, a low stacking pressure of 125 psi was used for both the inner layer and the final stack. The height of the capacitor was approximately 35 μm, including 10 μm of the screen printed electrode that completely encapsulates the dielectric and 20 μm of the ceramic dielectric. The two stacks of FR4 in each layer were ~ 150 μm on the finished plate.

  The external finish on the plate was ENIG (electroless Ni / Au). All copper etching was performed with an alkaline etchant. A microvia was used to connect the embedded capacitor to a copper pad on the surface of the substrate.

  A total of 39 finished PWB panels were produced. Each panel had 6 coupons with capacitors having the design discussed in this patent. Each coupon had 18 capacitors.

FIG. 2 is a diagram showing cracks observed in a prior art design of a fired-on-foil capacitor. FIG. 2 is a diagram showing cracks observed in a prior art design of a fired-on-foil capacitor. It is a figure which shows the method of manufacturing a printed wiring board provided with the on-foil embedded capacitor which has the printed electrode which covers the whole dielectric material. It is a figure which shows the method of manufacturing a printed wiring board provided with the on-foil embedded capacitor which has the printed electrode which covers the whole dielectric material. It is a figure which shows the method of manufacturing a printed wiring board provided with the on-foil embedded capacitor which has the printed electrode which covers the whole dielectric material. It is a figure which shows the method of manufacturing a printed wiring board provided with the on-foil embedded capacitor which has the printed electrode which covers the whole dielectric material. It is a figure which shows the method of manufacturing a printed wiring board provided with the on-foil embedded capacitor which has the printed electrode which covers the whole dielectric material. It is a figure which shows the method of manufacturing a printed wiring board provided with the on-foil embedded capacitor which has the printed electrode which covers the whole dielectric material. It is a figure which shows the method of manufacturing a printed wiring board provided with the on-foil embedded capacitor which has the printed electrode which covers the whole dielectric material. It is a figure which shows the method of manufacturing a printed wiring board provided with the on-foil embedded capacitor which has the printed electrode which covers the whole dielectric material. It is a figure which shows the method of manufacturing a printed wiring board provided with the on-foil embedded capacitor which has the printed electrode which covers the whole dielectric material. It is a figure which shows the method of manufacturing a printed wiring board provided with the on-foil embedded capacitor which has the printed electrode which covers the whole dielectric material. It is a figure which shows the method of manufacturing a printed wiring board provided with the on-foil embedded capacitor which has the printed electrode which covers the whole dielectric material. It is a figure which shows the method of manufacturing a printed wiring board provided with the insulation isolation layer of the peripheral part of a dielectric material, and the baking embedding capacitor on foil which has the printed electrode which covers the whole dielectric material. It is a figure which shows the method of manufacturing a printed wiring board provided with the insulation isolation layer of the peripheral part of a dielectric material, and the baking embedding capacitor on foil which has the printed electrode which covers the whole dielectric material. It is a figure which shows the method of manufacturing a printed wiring board provided with the insulation isolation layer of the peripheral part of a dielectric material, and the baking embedding capacitor on foil which has the printed electrode which covers the whole dielectric material. It is a figure which shows the method of manufacturing a printed wiring board provided with the insulation isolation layer of the peripheral part of a dielectric material, and the baking embedding capacitor on foil which has the printed electrode which covers the whole dielectric material. It is a figure which shows the method of manufacturing a printed wiring board provided with the insulation isolation layer of the peripheral part of a dielectric material, and the baking embedding capacitor on foil which has the printed electrode which covers the whole dielectric material. It is a figure which shows the method of manufacturing a printed wiring board provided with the insulation isolation layer of the peripheral part of a dielectric material, and the baking embedding capacitor on foil which has the printed electrode which covers the whole dielectric material. It is a figure which shows the method of manufacturing a printed wiring board provided with the insulation isolation layer of the peripheral part of a dielectric material, and the baking embedding capacitor on foil which has the printed electrode which covers the whole dielectric material. It is a figure which shows the method of manufacturing a printed wiring board provided with the insulation isolation layer of the peripheral part of a dielectric material, and the baking embedding capacitor on foil which has the printed electrode which covers the whole dielectric material. It is a figure which shows the method of manufacturing a printed wiring board provided with the insulation isolation layer of the peripheral part of a dielectric material, and the baking embedding capacitor on foil which has the printed electrode which covers the whole dielectric material. It is a figure which shows the method of manufacturing a printed wiring board provided with the insulation isolation layer of the peripheral part of a dielectric material, and the baking embedding capacitor on foil which has the printed electrode which covers the whole dielectric material. An alternative method (for the method described in FIGS. 3A-3J) for manufacturing a printed wiring board comprising an insulating isolation layer at the periphery of a dielectric and a fired embedded capacitor on foil having printed electrodes covering the entire dielectric. FIG. An alternative method (for the method described in FIGS. 3A-3J) for manufacturing a printed wiring board comprising an insulating isolation layer at the periphery of a dielectric and a fired embedded capacitor on foil having printed electrodes covering the entire dielectric. FIG. An alternative method (for the method described in FIGS. 3A-3J) for manufacturing a printed wiring board comprising an insulating isolation layer at the periphery of a dielectric and a fired embedded capacitor on foil having printed electrodes covering the entire dielectric. FIG. An alternative method (for the method described in FIGS. 3A-3J) for manufacturing a printed wiring board comprising an insulating isolation layer at the periphery of a dielectric and a fired embedded capacitor on foil having printed electrodes covering the entire dielectric. FIG. An alternative method (for the method described in FIGS. 3A-3J) for manufacturing a printed wiring board comprising an insulating isolation layer at the periphery of a dielectric and a fired embedded capacitor on foil having printed electrodes covering the entire dielectric. FIG. An alternative method (for the method described in FIGS. 3A-3J) for manufacturing a printed wiring board comprising an insulating isolation layer at the periphery of a dielectric and a fired embedded capacitor on foil having printed electrodes covering the entire dielectric. FIG. An alternative method (for the method described in FIGS. 3A-3J) for manufacturing a printed wiring board comprising an insulating isolation layer at the periphery of a dielectric and a fired embedded capacitor on foil having printed electrodes covering the entire dielectric. FIG. An alternative method (for the method described in FIGS. 3A-3J) for manufacturing a printed wiring board comprising an insulating isolation layer at the periphery of a dielectric and a fired embedded capacitor on foil having printed electrodes covering the entire dielectric. FIG. An alternative method (for the method described in FIGS. 3A-3J) for manufacturing a printed wiring board comprising an insulating isolation layer at the periphery of a dielectric and a fired embedded capacitor on foil having printed electrodes covering the entire dielectric. FIG. An alternative method (for the method described in FIGS. 3A-3J) for manufacturing a printed wiring board comprising an insulating isolation layer at the periphery of a dielectric and a fired embedded capacitor on foil having printed electrodes covering the entire dielectric. FIG. An alternative method (for the method described in FIGS. 3A-3J) for manufacturing a printed wiring board comprising an insulating isolation layer at the periphery of a dielectric and a fired embedded capacitor on foil having printed electrodes covering the entire dielectric. FIG. An alternative method (for the method described in FIGS. 3A-3J) for manufacturing a printed wiring board comprising an insulating isolation layer at the periphery of a dielectric and a fired embedded capacitor on foil having printed electrodes covering the entire dielectric. FIG. Printed wiring comprising a fired embedded bi-dielectric layer capacitor on foil having printed electrodes covering the entire first and second dielectric layers, the isolation layer also serving as a barrier layer protecting the capacitor dielectric from etch chemistry It is a figure which shows the method of manufacturing a board. Printed wiring comprising a fired embedded bi-dielectric layer capacitor on foil having printed electrodes covering the entire first and second dielectric layers, the isolation layer also serving as a barrier layer protecting the capacitor dielectric from etch chemistry It is a figure which shows the method of manufacturing a board. Printed wiring comprising a fired buried bi-dielectric layer capacitor on foil with printed electrodes covering the entire first and second dielectric layers, the isolation layer also acting as a barrier layer protecting the capacitor dielectric from etch chemistry It is a figure which shows the method of manufacturing a board. Printed wiring comprising a fired embedded bi-dielectric layer capacitor on foil having printed electrodes covering the entire first and second dielectric layers, the isolation layer also serving as a barrier layer protecting the capacitor dielectric from etch chemistry It is a figure which shows the method of manufacturing a board. Printed wiring comprising a fired embedded bi-dielectric layer capacitor on foil having printed electrodes covering the entire first and second dielectric layers, the isolation layer also serving as a barrier layer protecting the capacitor dielectric from etch chemistry It is a figure which shows the method of manufacturing a board. Printed wiring comprising a fired embedded bi-dielectric layer capacitor on foil having printed electrodes covering the entire first and second dielectric layers, the isolation layer also serving as a barrier layer protecting the capacitor dielectric from etch chemistry It is a figure which shows the method of manufacturing a board. Printed wiring comprising a fired embedded bi-dielectric layer capacitor on foil having printed electrodes covering the entire first and second dielectric layers, the isolation layer also serving as a barrier layer protecting the capacitor dielectric from etch chemistry It is a figure which shows the method of manufacturing a board. Printed wiring comprising a fired embedded bi-dielectric layer capacitor on foil having printed electrodes covering the entire first and second dielectric layers, the isolation layer also serving as a barrier layer protecting the capacitor dielectric from etch chemistry It is a figure which shows the method of manufacturing a board. Printed wiring comprising a fired embedded bi-dielectric layer capacitor on foil having printed electrodes covering the entire first and second dielectric layers, the isolation layer also serving as a barrier layer protecting the capacitor dielectric from etch chemistry It is a figure which shows the method of manufacturing a board. Printed wiring comprising a fired embedded bi-dielectric layer capacitor on foil having printed electrodes covering the entire first and second dielectric layers, the isolation layer also serving as a barrier layer protecting the capacitor dielectric from etch chemistry It is a figure which shows the method of manufacturing a board. Printed wiring comprising a fired embedded bi-dielectric layer capacitor on foil having printed electrodes covering the entire first and second dielectric layers, the isolation layer also serving as a barrier layer protecting the capacitor dielectric from etch chemistry It is a figure which shows the method of manufacturing a board. Printed wiring comprising a fired embedded bi-dielectric layer capacitor on foil having printed electrodes covering the entire first and second dielectric layers, the isolation layer also serving as a barrier layer protecting the capacitor dielectric from etch chemistry It is a figure which shows the method of manufacturing a board. Printed wiring comprising a fired embedded bi-dielectric layer capacitor on foil having printed electrodes covering the entire first and second dielectric layers, the isolation layer also serving as a barrier layer protecting the capacitor dielectric from etch chemistry It is a figure which shows the method of manufacturing a board. Printed wiring comprising a fired embedded bi-dielectric layer capacitor on foil having printed electrodes covering the entire first and second dielectric layers, the isolation layer also serving as a barrier layer protecting the capacitor dielectric from etch chemistry It is a figure which shows the method of manufacturing a board. Printed wiring comprising a fired embedded bi-dielectric layer capacitor on foil having printed electrodes covering the entire first and second dielectric layers, the isolation layer also serving as a barrier layer protecting the capacitor dielectric from etch chemistry It is a figure which shows the method of manufacturing a board. FIG. 6 shows an alternative method of manufacturing a printed wiring board comprising fired embedded bi-dielectric layer capacitors on foil having printed electrodes covering the entire first and second dielectric layers. FIG. 6 shows an alternative method of manufacturing a printed wiring board comprising fired embedded bi-dielectric layer capacitors on foil having printed electrodes covering the entire first and second dielectric layers. FIG. 6 shows an alternative method of manufacturing a printed wiring board comprising fired embedded bi-dielectric layer capacitors on foil having printed electrodes covering the entire first and second dielectric layers. FIG. 5 shows an alternative method of manufacturing a printed wiring board comprising fired embedded bi-dielectric layer capacitors on foil having printed electrodes covering the entire first and second dielectric layers. FIG. 6 shows an alternative method of manufacturing a printed wiring board comprising fired embedded bi-dielectric layer capacitors on foil having printed electrodes covering the entire first and second dielectric layers. FIG. 6 shows an alternative method of manufacturing a printed wiring board comprising fired embedded bi-dielectric layer capacitors on foil having printed electrodes covering the entire first and second dielectric layers. FIG. 6 shows an alternative method of manufacturing a printed wiring board comprising fired embedded bi-dielectric layer capacitors on foil having printed electrodes covering the entire first and second dielectric layers. FIG. 6 shows an alternative method of manufacturing a printed wiring board comprising fired embedded bi-dielectric layer capacitors on foil having printed electrodes covering the entire first and second dielectric layers. FIG. 6 shows an alternative method of manufacturing a printed wiring board comprising fired embedded bi-dielectric layer capacitors on foil having printed electrodes covering the entire first and second dielectric layers. FIG. 6 shows an alternative method of manufacturing a printed wiring board comprising fired embedded bi-dielectric layer capacitors on foil having printed electrodes covering the entire first and second dielectric layers. FIG. 6 shows an alternative method of manufacturing a printed wiring board comprising fired embedded bi-dielectric layer capacitors on foil having printed electrodes covering the entire first and second dielectric layers.

Explanation of symbols

200 capacitor 210 metal foil 212 underprint 215 groove 217 copper pad 218 second capacitor foil electrode 219 copper pad 220 first capacitor dielectric material layer 225 second capacitor dielectric material layer 228 capacitor dielectric 230 conductive material layer 232 top electrode (Conductive material layer) / first electrode 240 prepreg material (laminated material)
250 Foil 252 Circuit component 254 Circuit component 256 Circuit component 260 Photoresist pattern 262 Photoresist pattern 2000 Multilayer printed wiring board 2010 Microvia 2020 Microvia 300 Capacitor 310 Metal foil 312 Underprint 313 Insulating separation layer 314 Insulating separation layer 316 Groove 318 First Two-capacitor foil electrode 320 First capacitor dielectric material layer 325 Second capacitor dielectric material layer 328 Capacitor dielectric 330 Conductive material layer 332 Top electrode (first electrode)
340 Prepreg material (laminate material)
345 Laminated plate 350 Foil 360 Photoresist pattern 362 Photoresist 370 Copper foil 385 Circuit component 3000 Multilayer printed wiring board 3010 Micro via 3020 Through hole via 400 Capacitor 410 Metal foil 412 Underprint 413 Insulating separation layer 414 Insulating separation layer 415 Groove 418 First Two-capacitor foil electrode 420 First capacitor dielectric material layer 425 Second capacitor dielectric material layer 428 Capacitor dielectric 430 Conductive material layer 432 Top electrode (first electrode)
440 Prepreg material (laminate material)
445 Laminated plate 450 Foil 460 Photoresist pattern 462 Photoresist 470 Copper foil 485 Circuit component 4000 Multi-layer printed wiring board 4010 Through-hole via 4020 Through-hole via 500 Bi-dielectric layer capacitor 510 Metal foil 512 Underprint 513 Insulating separation layer 514 Insulating separation Layer 515 Groove 518 Capacitor foil electrode 520 First capacitor dielectric material layer 525 Second capacitor dielectric material layer 528 Capacitor dielectric 530 Conductive material layer 532 Conductive material layer (first electrode)
534 First capacitor dielectric layer 535 Second capacitor dielectric layer 536 Conductive layer 538 Capacitor dielectric 539 Top electrode (second electrode)
540 Prepreg material (laminate material)
545 Laminated plate 550 Foil 560 Patterned photoresist 562 Photoresist 570 Copper foil 5000 Multilayer printed wiring board 5010 Through hole via 5020 Through hole via 600 Capacitor 610 Foil 615 Groove 618 Third capacitor electrode 628 Capacitor dielectric (first dielectric)
632 electrode (first capacitor electrode)
633 Insulation isolation layer 634 First capacitor dielectric layer 635 Second capacitor dielectric layer 636 Conductive layer 637 Insulation isolation layer 638 Capacitor dielectric (second dielectric)
639 Top electrode (second capacitor electrode)
640 Prepreg material (laminated material)
645 Laminated plate 650 Copper foil 660 Patterned photoresist 662 Photoresist 670 Copper foil 6000 Multilayer printed wiring board 6010 Through-hole via 6020 Micro via

Claims (17)

A method of forming an embedded capacitor comprising:
Providing a metal foil;
Forming a dielectric layer on the metal foil;
Forming a first electrode on the entire dielectric layer and at least a portion of the metal foil;
Firing the embedded capacitor;
Etching the metal foil to form a second electrode.   The method of claim 1, further comprising forming an insulating isolation layer on the metal foil before forming the dielectric layer on the metal foil.   The method of claim 1, further comprising forming an insulating isolation layer over the dielectric layer. Forming a second capacitor dielectric layer on the first electrode;
Forming a second electrode on the entire second capacitor dielectric layer, at least a portion of the insulating isolation layer, and at least a portion of the metal foil, thereby forming a bi-dielectric layer structure;
4. The method according to any one of claims 2 and 3, further comprising firing the structure. The method of claim 4, further comprising forming a second insulating separation layer on the first electrode.   A capacitor formed by the method according to claim 1.   A device comprising the capacitor according to claim 6. A method of creating a device,
Providing a metal foil;
Forming a dielectric on the metal foil to form a component side and a foil side of the metal foil;
Forming a first electrode on the entire dielectric and a portion of the metal foil;
Laminating the component side of the metal foil to at least one prepreg material;
Etching the metal foil to form a second electrode;
And the encapsulating first electrode, the dielectric, and the second electrode form a capacitor. 9. The method of claim 8, comprising forming one or more vias in the one or more prepreg materials that connect to the capacitor. A device comprising at least one capacitor embedded in at least one layer of dielectric material, the capacitor comprising:
A first electrode formed from a metal foil, at least one layer of dielectric material, and a printed electrode covering the entire first layer of dielectric material and a portion of the metal foil;
A second layer of dielectric material adjacent to the first electrode;
A device comprising a second electrode formed from the metal foil and adjacent to the first layer of dielectric material and the second layer of dielectric material. A method of creating a device,
Providing a metal foil having a component side and a foil side;
Forming an insulating separation layer on the metal foil;
Forming a dielectric on the metal foil, wherein the dielectric is surrounded by an insulating isolation layer and in contact with the insulating isolation layer;
Forming a first electrode on the whole dielectric, a part of the insulating separation layer, and a part of the metal foil to form an encapsulating electrode;
Laminating the component side of the metal foil to at least one prepreg material;
Etching the metal foil to form a second electrode;
And encapsulating the first electrode, the dielectric, and the second electrode to form a capacitor.   The method of claim 11, wherein the insulating layer also serves as a barrier layer to prevent etching chemicals from contacting the capacitor dielectric.   12. The method of claim 11, wherein after etching the metal foil, the device is laminated to at least one additional prepreg material. 14. The method of claim 13, comprising forming one or more vias in the prepreg material that connect the capacitors. A device comprising at least one capacitor embedded in at least one layer of dielectric material, the capacitor comprising:
Printed over metal foil, at least one layer of dielectric material, insulating isolation layer, the entire first layer of dielectric material, part of the insulating isolation layer, and part of the metal foil A first electrode formed from an electrode;
A second layer of dielectric material adjacent to the first electrode and the insulating isolation layer;
A device comprising a second electrode formed from the metal foil and adjacent to the first layer of dielectric material and the second layer of dielectric material.   15. A device formed by the method of any one of claims 8, 11 or 14. 16. The device according to any one of claims 7, 10, or 15, wherein the device is selected from an interposer, a printed wiring board, a multichip module, an area array package, a system on package, and a system in package.

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