JP2005303186A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2005303186A JP2005303186A JP2004120286A JP2004120286A JP2005303186A JP 2005303186 A JP2005303186 A JP 2005303186A JP 2004120286 A JP2004120286 A JP 2004120286A JP 2004120286 A JP2004120286 A JP 2004120286A JP 2005303186 A JP2005303186 A JP 2005303186A
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- H01L2224/45001—Core members of the connector
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
【解決手段】最上層1層目のメタル配線近傍まで層間膜であるlow−k膜5を形成し、最上層1層目のメタル配線よりも下方位置にて形成の層間膜上にレジスト21を形成する。パッド上方より露光22により、レジスト21がない部分のみエッチングされ、さらにレジスト21を除去して、low−k膜5の表面のみに段差23を形成する。TEOS材料膜4の層間膜を形成するとlow−k膜5とTEOS材料膜4の境界面に凹凸部24を形成できる。最上層メタル配線のCu膜3、電極パッドのAL膜2、電極パッド保護膜のSiN膜1を形成して電極パッド構造を形成する。この電極パッド構造によりボンディング工法のワイヤーを電極パッドのAL膜2に接着直後の引張り応力の電極パッドダメージによる影響を防ぐ。
【選択図】図1
Description
2 AL膜(電極パッド)
3 Cu膜(最上層メタル配線)
4 TEOS材料膜
5 low−k膜(低誘電率材料)
6 電極ビア
7 配線層
11 ワイヤー
12 金ボール
13 金バンプ
14 引張り応力
15 剥離
16 クラック
21 レジスト
22 露光
23 段差
24 凹凸部
Claims (2)
- 電極パッドの下部に形成される少なくとも2層の層間絶縁膜同士の境界面が凹凸部を含む平面であることを特徴とする半導体装置。
- 電極パッドの下部に形成される第1の層間絶縁膜の表面に凹凸部を形成し、前記第1の層間絶縁膜の上に第2の層間絶縁膜を形成することを特徴とする半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004120286A JP2005303186A (ja) | 2004-04-15 | 2004-04-15 | 半導体装置およびその製造方法 |
Applications Claiming Priority (1)
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---|---|---|---|
JP2004120286A JP2005303186A (ja) | 2004-04-15 | 2004-04-15 | 半導体装置およびその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2005303186A true JP2005303186A (ja) | 2005-10-27 |
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ID=35334295
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Application Number | Title | Priority Date | Filing Date |
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JP2004120286A Withdrawn JP2005303186A (ja) | 2004-04-15 | 2004-04-15 | 半導体装置およびその製造方法 |
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JP (1) | JP2005303186A (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100714478B1 (ko) | 2006-02-10 | 2007-05-04 | 삼성전자주식회사 | 와이어 본딩 신뢰성이 향상된 반도체 소자 및 그 제조 방법 |
US9741805B2 (en) | 2014-12-04 | 2017-08-22 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the semiconductor device |
US11640950B2 (en) | 2020-09-09 | 2023-05-02 | Samsung Electronics Co., Ltd. | Semiconductor chip and semiconductor package |
-
2004
- 2004-04-15 JP JP2004120286A patent/JP2005303186A/ja not_active Withdrawn
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100714478B1 (ko) | 2006-02-10 | 2007-05-04 | 삼성전자주식회사 | 와이어 본딩 신뢰성이 향상된 반도체 소자 및 그 제조 방법 |
US9741805B2 (en) | 2014-12-04 | 2017-08-22 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the semiconductor device |
US11640950B2 (en) | 2020-09-09 | 2023-05-02 | Samsung Electronics Co., Ltd. | Semiconductor chip and semiconductor package |
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