JP2005285950A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the variation of effective gate length for each product, while enhancing the breakdown voltage between the drain region and channel. <P>SOLUTION: The semiconductor device is provided with a source region 4; a drain region 3; a first gate electrode 8 formed via gate oxidized film above the channel between the source region 4 and the drain region 3; and a second gate electrode 9 formed via gate oxidized film 7 above a part of the drain region 3 and a part of the first gate electrode 8. The drain region 3 is constituted of a deep low concentration diffusion region 3B, and a shallow high concentration diffusion domain 3A which is the same conductivity type as that of the low concentration diffusion region 3B and arranged in the low concentration diffusion region 3B. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a two-layer structure in which a drain region has a deep low-concentration diffusion region and a shallow high-concentration diffusion region, and a manufacturing method thereof.

  For the purpose of improving the element breakdown voltage of a semiconductor device such as a MOSFET, a semiconductor device having a structure in which, for example, a low concentration region is additionally formed in a drain region has been proposed (see Patent Document 1). An example of a semiconductor device (MOSFET) having such a structure is shown in FIG. In this MOSFET, the silicon (Si) semiconductor substrate 101 used is p-type, and an n-type well 102 is deeply formed on this surface. A p-channel MOSFET (hereinafter referred to as “PMOS”) is formed on the surface of the n-type well 102. On the surface of the n-type well 102, a p + type high concentration diffusion region 103A formed shallow as a PMOS drain region 103, and a p− type low concentration diffusion region 103B formed deeper than the high concentration diffusion region 103A, Is formed. Further, a p + type source region 104 is formed shallow in the n type well 102. Further, in a predetermined region of the n-type well 102, a back gate n + -type diffusion region 105 for applying a bias voltage to the n-type well 102 is formed shallow.

The surface of the semiconductor substrate 101 is separated between the element regions and between the drain region 103 and the n + -type diffusion region 105 for the back gate by a thick field oxide film (SiO ₂ ) 106. A gate electrode 108 made of polycrystalline silicon is formed on the gate oxide film 107, and a channel region is formed below the gate electrode 108. An insulating film 109 such as BPSG (borophosphosilicate glass) is laminated on the entire surface of the semiconductor substrate 101. A metal wiring layer 110 such as aluminum is laminated on the insulating film 109. The metal wiring layer 110 is connected to the high-concentration diffusion region 103A, the source region 104, and the back gate n + diffusion region 105 in the drain region 103 through contact holes 111 formed in the insulating film 109, respectively.

  In the semiconductor device shown in FIG. 3 described above, for example, a p-type silicon single crystal is cut into a wafer, the surface is mirror-polished, the wafer is exposed to a high-temperature oxygen atmosphere, and a silicon oxide film is grown. A pattern to be an n-type well region is formed on the oxide film using a resist, doped with n-type well impurities, thermally diffused to form an n-type well (n-type well formation step), It is manufactured by a process as shown in FIG.

  First, as shown in FIG. 4A, a pad oxide film 120 is formed on the well 102 and the semiconductor substrate 101, and a resist 121 is formed on the pad oxide film 120. Then, B (boron) is ion-implanted through the pad oxide film 120 from the opening of the resist 121 in order to form a low-concentration drain region at a necessary portion of the n-type well 102.

  Next, as shown in FIGS. 4B and 4C, a nitride film 122 is formed on the low-concentration drain region, and heat is applied to the field oxide film 106 using the nitride film 122. Form. At the same time, the implanted B ions are diffused to form a p-type low concentration diffusion region 103B of PMOS.

Further, as shown in FIG. 4D, after removing the nitride film 122 and the pad oxide film 120 and forming the gate oxide film 107, a conductive polycrystalline silicon layer is formed on the upper surface, and the polycrystalline silicon layer is formed. The gate electrode 108 is formed by removing unnecessary portions. The periphery of the gate electrode 108 is covered with an oxide film such as SiO ₂ .

  Next, as shown in FIG. 4E, in order to form a high concentration diffusion region in the low concentration diffusion region 103B of the drain region 103 and to form a source region in the n-type well 102, the semiconductor substrate 101 is formed. Then, a resist 123 is formed at the necessary locations, and B (boron) ions are implanted through the gate oxide film 120 from the openings of the resist 123, the field oxide film 106 and the gate electrode 108.

  Next, as shown in FIG. 4F, in order to form an n + -type diffusion region for the back gate in the well 102, a resist 124 is formed at a necessary portion of the semiconductor substrate 101, and a gate oxide film is formed from the opening of the resist 124. Through 120, P (phosphorus) is ion-implanted.

  Next, as shown in FIG. 4G, the semiconductor substrate 101 is heat-treated to diffuse the implanted B ions and P ions, thereby forming a p + type high concentration diffusion region 103A and a source region 104 in the drain region 103. And n + type diffusion region 105 for back gate is formed shallowly.

  Finally, an insulating film 109 is laminated on the entire surface of the semiconductor substrate 101, and then a contact hole 111 is formed in the insulating film 109, and a metal wiring layer 110 having a predetermined pattern is formed on the insulating film 109, as shown in FIG. Such a MOSFET is formed.

According to this semiconductor device, the drain region 103 has a two-layer structure of the high-concentration diffusion region 103A and the low-concentration diffusion region 103B, so that the electric field gradient between the drain region 103 and the channel is moderated and the high breakdown voltage is reduced. Trying to get.
JP 2000-340676 A

  In the semiconductor device shown in FIG. 3, the distance between the lower end of the gate electrode 108 of the low concentration diffusion region 103B of the drain region 103 and the lower end of the gate electrode 108 of the source region 104 is the effective gate. Become long. This effective gate length depends on the alignment accuracy in the photolithography process of the resist 121 in the B ion implantation process in FIG. 4A and the patterning accuracy of the gate electrode 108 in FIG. When the deviation occurs, there is a problem that the effective gate length varies for each product and the characteristics vary.

  Therefore, the present invention has been proposed in view of such a conventional situation, and a semiconductor device having a high breakdown voltage between the drain region and the channel and capable of suppressing fluctuations in the effective gate length for each product. The purpose is to provide. Another object of the present invention is to provide a semiconductor device manufacturing method capable of manufacturing a semiconductor device having a high breakdown voltage between a drain region and a channel while suppressing variation in effective gate length for each product. And

  In order to solve the above-described problem, a semiconductor device according to the present invention includes a source region, a drain region, and a channel formed between a source region and the drain region above a channel via a gate oxide film. And a second gate electrode formed through an oxide film above a part of the drain region and a part of the first gate electrode, the drain region having a depth of A deep low concentration diffusion region, and a shallow high concentration diffusion region having the same conductivity type as the low concentration diffusion region and provided in the low concentration diffusion region, and a low concentration diffusion region having a deep depth of the drain region Is formed by ion implantation using the first gate electrode as a mask, and a second gate electrode is formed so as to cover a portion of the deep low-concentration diffusion region, and the drain region has a shallow high-concentration diffusion. Territory And the source region is characterized by being formed by ion implantation using as a mask the first gate electrode and the second gate electrode.

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming a gate oxide film on a semiconductor substrate and then forming a first gate electrode on the gate oxide film, and a region other than a region where a drain region is formed. Ion implantation into a region of the semiconductor substrate where the drain region is formed using the resist to be covered and the first gate electrode as a mask, and forming a deep low-concentration diffusion region in the drain region; Forming a second gate electrode so as to cover a part of the low concentration diffusion region of the substrate and a part of the first gate electrode; and using the first gate electrode and the second gate electrode as a mask, the low concentration A step of implanting ions of the same conductivity type as the low-concentration diffusion region into a region where the diffusion region and the source region of the semiconductor substrate are formed to form the high-concentration diffusion region and the source region. It is characterized in.

  In the semiconductor device of the present invention, since the low concentration diffusion region is additionally formed in the drain region, the electric field gradient between the drain region and the channel during operation is alleviated and the breakdown voltage is increased. However, when such a two-layer structure is adopted, the effective gate length is likely to vary depending on the alignment accuracy. Therefore, in the present invention, in a semiconductor device having a drain region having a two-layer structure, a low-concentration diffusion region that constitutes one end that determines the effective gate length is formed deep using the self-alignment of the first gate electrode. . Further, the source region constituting the other end that determines the effective gate length is shallowly formed using the self-alignment of the first gate electrode and the second gate electrode. By adopting such a method, the variation in effective gate length is determined only by the processing accuracy of the first gate electrode. Therefore, fluctuations in the effective gate length due to the position shift of the end portion of the low concentration diffusion region are suppressed.

  According to the semiconductor device of the present invention, since the drain region has a two-layer structure of the low concentration diffusion region and the high concentration diffusion region, the element breakdown voltage can be increased. Further, according to the semiconductor device of the present invention, since the variation of the effective gate length due to the positional deviation of the end portion of the low concentration diffusion region is suppressed, the device breakdown voltage is high, the characteristic variation is small, and the excellent quality is achieved. A semiconductor device can be provided.

  According to the method for manufacturing a semiconductor device of the present invention, since the drain region has a two-layer structure of a low concentration diffusion region and a high concentration diffusion region, a semiconductor device with a high element breakdown voltage can be manufactured. . In addition, according to the method for manufacturing a semiconductor device of the present invention, in manufacturing a semiconductor device having a structure in which the drain region has a two-layer structure of a low concentration diffusion region and a high concentration diffusion region, self-alignment by the first gate electrode is performed. Since both the low-concentration diffusion region and the source region are formed by using, the variation in the effective gate length due to the position shift of the end portion of the low-concentration diffusion region can be suppressed, the variation in characteristics is small, and excellent A quality semiconductor device can be manufactured.

  Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to the drawings.

  As an example of the semiconductor device of the present invention, a semiconductor device including a high voltage MOSFET is shown in FIG. This semiconductor device has a structure in which a low concentration diffusion region is additionally formed in the drain region. In this semiconductor device, a silicon (Si) semiconductor substrate 1 to be used is p-type, and an n-type well 2 is deeply formed on this surface. A p-channel MOSFET (PMOS) is formed on the surface of the n-type well 2. On the surface of the n-type well 2, a p + type high concentration diffusion region 3A formed shallow as a PMOS drain region 3, and a p− type low concentration diffusion region 3B formed deeper than the high concentration diffusion region 3A Is formed. A p + type source region 4 is shallowly formed in the n type well 2. Further, in a predetermined region of the n-type well 2, an n + -type diffusion region 5 that is a back gate for applying a bias voltage to the n-type well 2 is formed shallow.

The surface of the semiconductor substrate 1 is separated by a thick field oxide film (SiO ₂ ) 6 between the element regions and between the drain region 3 and the n + -type diffusion region 5 for the back gate. On the gate oxide film 7, a first gate electrode 8 for a high voltage MOSFET made of, for example, polycrystalline silicon is formed, and a channel region is formed below the first gate electrode 8.

  Further, a second gate electrode 9 for a standard withstand voltage MOSFET made of, for example, polycrystalline silicon is formed above the low concentration diffusion region 3B and the first gate electrode 8. The second gate electrode 9 is formed with a step so as to extend over both the low-concentration diffusion region 3 </ b> B and the first gate electrode 8.

  An insulating film 10 such as BPSG is stacked on the entire surface of the semiconductor substrate 1. A metal wiring layer 11 such as aluminum is laminated on the insulating film 10. The metal wiring layer 11 is connected to the high-concentration diffusion region 3A, the source region 4 and the back gate n + diffusion region 5 in the drain region 3 through contact holes 12 formed in the insulating film 10, respectively.

The semiconductor device having the above configuration is manufactured by, for example, a process as shown in FIG. First, a p-type silicon single crystal is cut into a wafer, the surface is mirror-polished, the wafer is exposed to a high-temperature oxygen atmosphere, a silicon oxide film is grown, and then an n-type is formed on the oxide film using a photoresist. A pattern to be a well region is formed, an n-type well impurity is doped, and thermal diffusion is performed to form an n-type well 2 in a predetermined region of the semiconductor substrate 1 (n-type well formation step). Next, on the n-type well 2 and the semiconductor substrate 1, a gate oxide film 7, a field oxide film (SiO ₂ ) 6 separating each element and between the drain region 3 and the n + -type diffusion region 5 for the back gate, One gate electrode 8 is formed. The first gate electrode 8 is formed by patterning a polycrystalline silicon layer deposited on the gate oxide film 7 by photolithography and etching.

  Next, as shown in FIG. 2B, in order to form a low concentration diffusion region in the n-type well 2, a resist 20 is formed at a necessary portion, and the gate is formed using the self-alignment of the first gate electrode 8. Boron (B) ions are implanted through the oxide film 7.

  Next, as shown in FIG. 2C, the resist 20 is removed, the semiconductor substrate 1 is heat-treated, the implanted B ions are diffused, and the p − type low concentration diffusion region 3B of the drain region 3 is formed. Form deeply.

Further, as shown in FIG. 2D, the periphery of the first gate electrode 8 is covered with an oxide film such as SiO ₂ . Then, the second gate electrode 9 having a stepped structure is formed so as to extend over both the low concentration diffusion region 3 </ b> B and the first gate electrode 8. The second gate electrode 9 is formed by patterning the deposited polycrystalline silicon layer by photolithography and etching.

  Next, as shown in FIG. 2E, in order to form the high concentration diffusion region 3A in the low concentration diffusion region 3B of the drain region 3 and to form the source region in the n-type well 2, a necessary portion is resisted. Then, boron (B) is ion-implanted through the gate oxide film 7 using the self-alignment of the first gate electrode 8 and the second gate electrode 9.

  Next, as shown in FIG. 2 (f), in order to form an n + -type diffusion region for the back gate in the n-type well 2, a necessary portion of the semiconductor substrate 1 is covered with a resist 22, and the gate is opened from the opening of the resist 22. P (phosphorus) ions are implanted through the oxide film 7.

  Next, as shown in FIG. 2G, the semiconductor substrate 1 is heat-treated, and the implanted B ions and P ions are diffused to form a p + type high concentration diffusion region 3A and a source region 4 in the drain region 3. And n + type diffusion region 5 for back gate is formed shallowly.

  Finally, an insulating film 10 is stacked on the entire surface of the semiconductor substrate 1, and then a contact hole 12 is formed in the insulating film 10 to form a metal wiring layer 11 having a predetermined pattern on the insulating film 10, thereby forming the structure shown in FIG. Such a p-MOS device is formed.

  In the semiconductor device of the present invention manufactured as described above, a reverse electric field is applied between the low concentration diffusion region 3B of the drain region 3 and the channel during operation, and a depletion layer is generated at that time. The depletion layer increases in the direction of the low concentration diffusion region 3B of the drain region 3, and as a result, the electric field gradient between the drain region 3 and the channel is relaxed and the breakdown voltage is increased.

  Further, in this PMOS device, since both the low concentration diffusion region 3B and the source region 4 in the drain region 3 are formed in self-alignment with the first gate electrode 8 for high breakdown voltage, the variation of the effective gate length is the first gate. It is determined by the processing accuracy of the electrode 8. Accordingly, since photolithography of the resist mask for ion implantation is not required as in the prior art, the influence of the positional deviation due to the alignment accuracy of photolithography is eliminated, and the positional deviation of the end portion on the gate electrode side of the low concentration diffusion region 3B is eliminated. Variations in the effective gate length due to this can be suppressed.

  In the above description, a p-MOS is taken as an example, but the present invention can be similarly applied to an n-MOS.

It is a principal part schematic sectional drawing which shows an example of the semiconductor device to which this invention is applied. It is a principal part schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device to which this invention is applied. It is a principal part schematic sectional drawing which shows an example of the conventional semiconductor device. It is a principal part schematic sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device.

Explanation of symbols

1 semiconductor substrate, 2 n-type well, 3 drain region, 3A p + type high concentration diffusion region, 3B p− type low concentration diffusion region, 4 source region, 5 n + type diffusion region for back gate, 6 field oxide film, 7 gate Oxide film, 8 First gate electrode, 9 Second gate electrode, 10 Insulating film, 11 Metal wiring layer, 12 Contact hole

Claims (2)

A source region, a drain region, a first gate electrode formed above a channel between the source region and the drain region via a gate oxide film, a portion above the drain region, and the first region A second gate electrode formed above a part of the gate electrode,
The drain region is composed of a deep low-concentration diffusion region and a shallow high-concentration diffusion region that has the same conductivity type as the low-concentration diffusion region and is provided in the low-concentration diffusion region,
A low concentration diffusion region having a deep depth of the drain region is formed by ion implantation using the first gate electrode as a mask, and the second gate electrode covers a portion of the deep low concentration diffusion region. Formed,
The shallow high-concentration diffusion region and the source region of the drain region are formed by ion implantation using the first gate electrode and the second gate electrode as a mask. Forming a gate oxide film on the semiconductor substrate and then forming a first gate electrode on the gate oxide film;
Using the resist covering the region other than the region where the drain region is formed and the first gate electrode as a mask, ions are implanted into the region of the semiconductor substrate where the drain region is to be formed, and the low-density diffusion having a deep depth in the drain region. Forming a region;
Forming a second gate electrode so as to cover a part of the low-concentration diffusion region of the semiconductor substrate and a part of the first gate electrode;
Using the first gate electrode and the second gate electrode as a mask, ions having the same conductivity type as the lightly doped region are implanted into the lightly doped region and the source region of the semiconductor substrate. And a step of forming a source region.

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