JP2005260081A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability in a semiconductor device in a chip size package-type and in a manufacturing method of the device. <P>SOLUTION: A glass substrate 56 is bonded to a surface of a silicon wafer 51 where pad electrodes 53 are formed. Via holes VH reaching the pad electrodes 53 from a backside of the silicon wafer 51 are formed. Buffer layers 60 are formed and wiring layers 63 which extend to the backside of the silicon wafer 51 from the via holes VH and are connected to the pad electrodes 53 are formed. Reinforcement layers 64 are formed on the wiring layers 63 so that they are covered. A roughening processing is performed on the surfaces of the reinforcement layers 64 so that fine concaves and convexes are formed. Solder masks 65 are formed on the reinforcement layers 64 which are roughened, and openings K are arranged in a part of the reinforcement layers 64 and the solder masks 65. Solder balls 66 are formed in the openings K. The silicon wafer 51 is divided into individual silicon chips 51A by dicing. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a chip size package type semiconductor device and a manufacturing method thereof.

  In recent years, CSP (Chip Size Package) has attracted attention as a three-dimensional mounting technique and a new packaging technique. The CSP refers to a small package having an outer dimension substantially the same as the outer dimension of a semiconductor chip.

  Conventionally, a BGA type semiconductor device is known as a kind of CSP. In this BGA type semiconductor device, a plurality of ball-shaped conductive terminals made of a metal member such as solder are arranged in a lattice pattern on one main surface of a package, and electrically connected to a semiconductor chip mounted on the other surface of the package. Is connected to.

  When incorporating this BGA type semiconductor device into an electronic device, each conductive terminal is crimped to a wiring pattern on the printed circuit board, thereby electrically connecting the semiconductor chip and the external circuit mounted on the printed circuit board. Connected.

  Such a BGA type semiconductor device is provided with a larger number of conductive terminals than other CSP type semiconductor devices such as SOP (Small Outline Package) and QFP (Quad Flat Package) having lead pins protruding from the side. It has the advantage that it can be reduced in size. This BGA type semiconductor device has an application as an image sensor chip of a digital camera mounted on a mobile phone, for example.

  FIG. 18 shows a schematic configuration of a conventional BGA type semiconductor device, and FIG. 18A is a perspective view of the surface side of the BGA type semiconductor device. FIG. 18B is a perspective view of the back side of the BGA type semiconductor device.

  In this BGA type semiconductor device 101, a semiconductor chip 104 is sealed between first and second glass substrates 102 and 103 via epoxy resins 105a and 105b. A plurality of conductive terminals 106 are arranged in a grid pattern on one main surface of the second glass substrate 103, that is, on the back surface of the BGA type semiconductor device 101. The conductive terminal 106 is connected to the semiconductor chip 104 via the second wiring 110. The plurality of second wirings 110 are connected to the first wirings drawn from the inside of the semiconductor chip 104, respectively, and each conductive terminal 106 and the semiconductor chip 104 are electrically connected.

  The cross-sectional structure of the BGA type semiconductor device 101 will be described in more detail with reference to FIG. FIG. 19 is a cross-sectional view of the BGA type semiconductor device 101 divided into individual chips along the dicing line.

  A first wiring 107 is provided on the insulating film 108 disposed on the surface of the semiconductor chip 104. The semiconductor chip 104 is bonded to the first glass substrate 102 by a resin layer 105a. Further, the back surface of the semiconductor chip 104 is bonded to the second glass substrate 103 by a resin layer 105b.

  One end of the first wiring 107 is connected to the second wiring 110. The second wiring 110 extends from one end of the first wiring 107 to the surface of the second glass substrate 103. A ball-shaped conductive terminal 106 is formed on the second wiring 110 extending on the second glass substrate 103.

The above-described technique is described in Patent Document 1 below, for example.
JP-T-2002-512436

  However, in the BGA type semiconductor device 101 described above, since the contact area between the first wiring 107 and the second wiring 110 is very small, the second wiring 110 may be disconnected at this contact portion. . There was also a problem with the step coverage of the second wiring 110.

  Further, since the strength of the second wiring 110 is not sufficient, the second wiring 110 is distorted due to shear stress (force applied from the horizontal direction) or impact generated when the semiconductor device as a main body is mounted on a printed circuit board. As a result, problems such as deformation, breakage, or movement of the second wiring 110 have occurred. As a result, the reliability of the semiconductor device has been reduced.

  Therefore, the present invention aims to improve reliability in a chip size package type semiconductor device and a method for manufacturing the same.

  The semiconductor device of the present invention has been made in view of the above problems, and a pad electrode formed on the first main surface of the semiconductor chip and a support bonded to the first main surface of the semiconductor chip. A via hole penetrating from the second main surface of the semiconductor chip to the surface of the pad electrode, and a barrier layer (for example, electrically connected to the pad electrode through the via hole and extending from the via hole onto the second main surface of the semiconductor chip) A layer of titanium nitride), a wiring layer formed on the barrier layer (for example, made of copper), and a reinforcing layer (for example, formed to cover the barrier layer and the wiring layer and reinforcing the wiring layer) And a protective layer formed on the reinforcing layer. The surface of the reinforcing layer in contact with the protective layer is roughened. Size is a packaged semiconductor device.

  The semiconductor device according to the present invention includes a pad electrode formed on the first main surface of the semiconductor chip, a support bonded to the first main surface of the semiconductor chip, and a second main surface of the semiconductor chip. A via hole penetrating from the first main surface of the semiconductor chip to the via hole, an insulating film formed from the second main surface of the semiconductor chip to the via hole, and being electrically connected to the pad electrode through the via hole, and from the via hole to the second main surface of the semiconductor chip. A barrier layer (for example, made of titanium nitride) extending on the surface, a wiring layer (for example, made of copper) formed on the barrier layer, and a protective layer formed on the wiring so as to cover the wiring layer The surface of the insulating film in contact with the protective layer, or the surfaces of the insulating film and the wiring layer is roughened, and is a chip size package type semiconductor device.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: preparing a semiconductor substrate on which a pad electrode is formed; and bonding a support to the first main surface of the semiconductor substrate; Forming a via hole reaching the surface of the pad electrode; forming a barrier layer electrically connected to the pad electrode through the via hole and extending from the via hole onto the second main surface of the semiconductor substrate; and on the barrier layer A step of forming a wiring layer, a step of forming a reinforcing layer for reinforcing the wiring layer so as to cover the wiring layer on the wiring layer, and a step of roughening the surface of the reinforcing layer. And a step of forming a protective layer on the roughened reinforcing layer.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: preparing a semiconductor substrate on which a pad electrode is formed; and bonding a support to the first main surface of the semiconductor substrate; Forming a first insulating film on the semiconductor substrate; forming a via hole reaching the surface of the pad electrode from the second main surface of the semiconductor substrate; electrically connecting to the pad electrode through the via hole; A step of forming a barrier layer extending on the second main surface of the substrate; a step of forming a wiring layer on the barrier layer; and a surface of the first insulating film, or a surface of the first insulating film and the wiring layer. And a step of roughening the surface, and a step of forming a protective layer on the first insulating film and the wiring layer so as to cover the wiring layer.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: preparing a semiconductor substrate on which a pad electrode is formed; and bonding a support to the first main surface of the semiconductor substrate; Forming a via hole reaching the surface of the pad electrode; forming an insulating film on the second main surface of the semiconductor substrate including the via hole; removing the bottom of the via hole; Forming a barrier layer and a wiring layer connected to each other and extending from the via hole onto the second main surface of the semiconductor substrate, and a step of roughening the surface of the insulating film or the surface of the insulating film and the wiring layer And a step of forming a protective layer on the insulating film and the wiring layer so as to cover the wiring layer.

  Here, the roughening treatment of the production method of the present invention is performed by dry etching or wet etching.

  According to the present invention, since the wiring layer from the pad electrode of the semiconductor chip to the conductive terminal is formed through the via hole, disconnection of the wiring layer and deterioration of the step coverage can be prevented.

  In addition, since the wiring layer is covered with a reinforcing layer that reinforces the strength of the wiring layer, the wiring layer is distorted by shear stress (force applied in the horizontal direction) generated when the semiconductor device is mounted on a printed circuit board or by impact ( It is possible to improve durability against deformation or movement of the wiring layer and corrosion of the wiring layer. Furthermore, since the surface of the reinforcing layer is roughened, the adhesion with the protective layer formed thereon is improved.

  Further, in the case where the reinforcing layer is not formed, the insulating film formed on the back surface of the semiconductor chip, or the insulating film and the wiring layer is roughened on the surface, so that the protective layer formed thereon Adhesion is improved.

  As a result, a highly reliable chip size package type semiconductor device can be obtained.

  Next, a first embodiment of the present invention will be described with reference to the drawings. First, the structure of this semiconductor device will be described. FIG. 12 is a cross-sectional view of this semiconductor device, in which a semiconductor substrate that has undergone the steps described later, that is, a silicon wafer 51 is divided into individual semiconductor chips along a dicing line center DS in a dicing line region DL (not shown). Show.

  The silicon chip 51A, which is a semiconductor chip, is, for example, a CCD (Charge Coupled Device) image sensor chip, and a pad electrode 53 is formed on the surface that is the first main surface via an interlayer insulating film 52 such as BPSG. Has been. The pad electrode 53 is obtained by extending a pad electrode used for normal wire bonding to a dicing line region DL (not shown), and is also called an extended pad electrode.

  The pad electrode 53 is covered with a passivation film 54 such as a silicon nitride film. A glass substrate 56 as a support is bonded to the surface of the silicon chip 51A on which the pad electrode 53 is formed via a resin layer 55 made of, for example, an epoxy resin. The glass substrate 56 as a support has a function of supporting the silicon chip 51A and protecting the silicon chip 51A.

  When the silicon chip 51A is a CCD image sensor chip, it is necessary to receive light from the outside with a CCD device on the surface of the silicon chip 51A, so a transparent substrate such as a glass substrate 56 or a translucent substrate is used. There is a need. In the case where the silicon chip 51A does not receive or emit light, not only the glass substrate but also an opaque substrate may be used. For example, a substrate made of a metal or an organic material or a tape may be used.

  A via hole VH reaching the pad electrode 53 is formed from the back surface which is the second main surface of the silicon chip 51A. A sidewall insulating film 59A is formed on the sidewall of the via hole VH. The side wall insulating film 59A electrically insulates a wiring layer 63 described later and the silicon chip 51A.

  A buffer layer 60 is formed on the back surface of the silicon chip 51A in the region adjacent to the via hole VH via the first insulating film 57 and the second insulating film 59. The buffer layer 60 is preferably made of, for example, an organic insulating material, an inorganic insulating material, a photoresist, or the like that is rich in elasticity. Note that the first insulating film 57 is not necessarily formed.

  A barrier layer 61 that is electrically connected to the pad electrode 53 through the via hole VH and extends from the via hole VH to the back surface of the silicon chip 51A is formed. The barrier layer 61 is a metal layer made of, for example, titanium nitride (TiN). Alternatively, the barrier layer 61 may be made of a metal other than titanium nitride (TiN) as long as it functions as a barrier layer. For example, the barrier layer 61 may be composed of titanium tungsten (TiW), tantalum nitride (TaN), and a compound of the above metal.

  Further, on the barrier layer 61, a wiring layer 63 (also referred to as a rewiring layer) made of, for example, copper (Cu) is formed. Here, the barrier layer 61 and the wiring layer 63 extend on the back surface of the silicon chip 51 </ b> A so as to cover the buffer layer 60. A seed layer (not shown) is provided below the wiring layer 63, and this is a metal layer serving as a plating electrode used when the wiring layer 63 is formed by electrolytic plating. A seed layer (not shown) is made of, for example, copper (Cu).

In general, the wiring layer 63 as described above is distorted by shearing stress (force applied in the horizontal direction) or impact generated when a semiconductor device is mounted on a printed circuit board due to its metallic characteristics. There is a risk of deformation, damage or movement. That is, the strength of the wiring layer 63 was not sufficient. Therefore, in the present embodiment, the reinforcing layer 64 for reinforcing the strength of the wiring layer 63 is formed on the wiring layer 63 and the first insulating film 57 so as to cover the wiring layer 63. As a result, the strength of the wiring layer 63 against the above-described shear stress and impact is improved, and deformation, breakage, or movement of the wiring layer 63 can be suppressed as much as possible. Further, the occurrence of damage such as corrosion in the wiring layer 63 can be suppressed. The reinforcing layer 64 is preferably made of, for example, a silicon oxide film (SiO ₂ film) or a silicon nitride film (SiN film).

  Here, the reinforcing layer 64 is roughened so that fine irregularities are formed on the surface thereof. Further, a solder mask 65 that is a protective layer is formed on the reinforcing layer 64 so as to cover the surface of the roughened reinforcing layer 64. In the reinforcing layer 64 and the solder mask 65, an opening K is formed in a portion on the buffer layer 60. A solder ball 66 as a conductive terminal is mounted through the opening K of the solder mask 65. Thereby, the solder ball 66 and the wiring layer 63 are electrically connected. A BGA structure can be obtained by forming a plurality of such solder balls 66.

  Thus, wiring from the pad electrode 53 of the silicon chip 51A to the solder ball 66 formed on the back surface thereof is possible. Further, since the wiring layer 63 is formed through the via hole VH, the wiring layer 63 is not easily disconnected, and the step coverage is excellent.

  Further, since the wiring layer 63 is covered with the reinforcing layer 64, the wiring layer 63 is corroded, and the wiring layer 63 is distorted by shearing stress or impact generated when the semiconductor device is mounted on the printed circuit board (the wiring layer 63 Durability against deformation and movement is improved. Further, since the surface of the reinforcing layer 64 is roughened, the adhesion between the reinforcing layer 64 and the solder mask 65 is improved as compared with the case where the surface is not roughened. In addition, since the reinforcing layer 64 covers the entire surface of the back surface of the silicon wafer 51, the entire surface in contact with the solder mask 65 becomes a roughened surface. Thereby, the adhesiveness of the solder mask 65 improves.

  Further, since the solder ball 66 is disposed on the buffer layer 60, when the semiconductor device is mounted on the printed circuit board via the solder ball 66, the buffer layer 60 acts as a kind of cushion, and the impact is reduced. The solder ball 66 and the semiconductor device as the main body are prevented from being damaged.

  Further, the solder ball 66 is formed at a position higher than the back surface of the silicon chip 51A by the thickness of the buffer layer 60. This prevents the solder ball 66 and the silicon chip 51A from being damaged by the stress and impact caused by the difference in thermal expansion coefficient between the printed board and the solder ball 66 when the semiconductor device is mounted on the printed board. .

  The silicon chip 51A may be a semiconductor chip made of another material such as GaAs, Ge, Si—Ge. The glass substrate 56 preferably has a thermal expansion coefficient Kg close to the thermal expansion coefficient Ks of the silicon chip 51A. The range of the thermal expansion coefficient Kg is within ± 30% of the thermal expansion coefficient Ks of Si (2.6 to 3.0 ppm / ° K). That is, if the thermal expansion coefficient Kg of the glass substrate and the thermal expansion coefficient Ks of the silicon chip 51A are set, a relationship of 0.7 Ks ≦ Kg ≦ 1.3 Ks is established.

  Thereby, the curvature of the glass substrate 56 due to the difference in thermal expansion coefficient between the glass substrate 56 and the silicon chip 51A is prevented as much as possible. The same can be said when the silicon chip 51A is a semiconductor chip of another material.

  Next, a method for manufacturing the semiconductor device according to the first embodiment of the present invention described above will be described with reference to the drawings. The semiconductor device manufacturing method according to the present embodiment is performed, for example, as follows. 1 to 12 show a cross section of a silicon wafer 51 that is a semiconductor substrate, and shows a cross section of a boundary between adjacent chips (that is, near the dicing line region DL) that is to be divided in a dicing process described later. Yes. 1 to 12, it is assumed that a semiconductor integrated circuit (for example, a CCD image sensor) (not shown) is formed on the first main surface, that is, the surface of the silicon wafer 51.

  First, as shown in FIG. 1, a pair of pad electrodes 53 is formed on the surface of a silicon wafer 51 via an interlayer insulating film 52 such as BPSG. The pair of pad electrodes 53 is made of a metal layer such as aluminum, an aluminum alloy, or copper, and has a thickness of about 1 μm. Further, the pair of pad electrodes 53 is extended to the dicing line region DL, and the extended end portion is disposed before the dicing line center DS of the dicing line region DL.

  Then, a passivation film 54 such as a silicon nitride film covering the pair of pad electrodes 53 is formed, and a resin layer 55 made of, for example, an epoxy resin is applied on the passivation film 54.

  Then, the glass substrate 56 is bonded to the surface of the silicon wafer 51 through the resin layer 55. The glass substrate 56 has a function of supporting and protecting the silicon wafer 51. Then, with the glass substrate 56 adhered, the back surface etching of the silicon wafer 51, so-called back grinding, is performed as necessary, and the thickness is processed to about 150 μm.

  Thereafter, the silicon wafer 51 is etched by about 20 μm using an acid (for example, a mixed solution of HF and nitric acid) as an etchant. Thereby, the mechanical damage layer of the silicon wafer 51 generated by the back grinding is removed, and the characteristics of the device formed on the surface of the silicon wafer 51 are improved. In the present embodiment, the final thickness of the silicon wafer 51 is about 130 μm, but this can be appropriately selected according to the type of device.

Then, a first insulating film 57 is formed on the entire back surface of the silicon wafer 51 whose back surface has been cut by the above process. The first insulating film 57 is formed by, for example, a plasma CVD method, and a PE-SiO ₂ film or a PE-SiN film is suitable. The formation of the first insulating film 57 may be omitted.

  Next, as shown in FIG. 2, a photoresist layer 58 is selectively formed on the first insulating film 57. That is, the photoresist layer 58 is formed with an opening at a position corresponding to the pad electrode 53. Using the photoresist layer 58 as a mask, the first insulating film 57 and the silicon wafer 51 are etched. By this etching, a via hole VH penetrating the silicon wafer 51 is formed. Here, the interlayer insulating film 52 is exposed at the bottom of the via hole VH, and the pad electrode 53 is in contact therewith.

  When the formation of the first insulating film 57 is omitted, the silicon wafer 51 is etched using the photoresist layer 58 directly formed on the silicon wafer 51 as a mask.

  In order to form the via hole VH, there are a method of etching using a laser beam and a method of using dry etching. The cross-sectional shape of the via hole VH may be processed into a forward tapered shape in order to improve the coverage of a seed layer described later.

Next, as shown in FIG. 3, a second insulating film 59 is formed on the entire back surface of the silicon wafer 51 in which the via hole VH is formed. The second insulating film 59 is formed by, for example, a plasma CVD method, and a PE-SiO ₂ film or a PE-SiN film is suitable. The second insulating film 59 is formed on the bottom of the via hole VH, the side wall, and the first insulating film 57.

  When the formation of the first insulating film 57 is omitted, the second insulating film 59 is formed on the back surface of the silicon wafer 51 including the bottom and side walls of the via hole VH.

  Next, as shown in FIG. 4, a buffer layer 60 is formed on the second insulating film 59 adjacent to the via hole VH. The buffer layer 60 can be formed in a predetermined region by mask exposure and development processing using a film resist. The buffer layer 60 is not limited to this, and various materials such as an organic insulator, an inorganic insulator, a metal, silicon, and a photoresist can be used. However, in order to function as a cushion, an organic insulator rich in elasticity is used. Inorganic insulators and photoresists are suitable.

  Next, as shown in FIG. 5A, anisotropic dry etching is performed on the back surface of the silicon wafer 51 without using a photoresist layer. As a result, the second insulating film 59 remains only on the side wall of the via hole VH, and this becomes the side wall insulating film 59A. Further, the second insulating film 59 and the interlayer insulating film 52 located at the bottom of the via hole VH are removed by etching. The pad electrode 53 is exposed at the bottom of the via hole VH.

  As described above, in the present embodiment, after the formation of the via hole VH, the second insulating film 59 is formed in the via hole VH, and after the buffer layer 60 is formed, the second insulating film 59 positioned at the bottom of the via hole VH and The interlayer insulating film 52 is removed by etching, and the pad electrode 53 is exposed.

  On the contrary, it is possible to form the buffer layer 60 after etching the bottom of the via hole VH to expose the pad electrode 53, but in this case, when the buffer layer 60 is formed, the exposed via hole is exposed. There is a possibility that the bottom of the VH is contaminated and the electrical connection between the wiring layer 63 and the pad electrode 53 to be formed in the via hole VH later becomes poor. Therefore, it is preferable to etch the bottom of the via hole VH after the formation of the buffer layer 60 as in this embodiment in order to obtain a good electrical connection between the wiring layer 63 and the pad electrode 53.

  In addition, the etching after the formation of the buffer layer 60 described above has an advantage that the surface of the buffer layer 60 becomes rough and adhesion to a barrier layer 61 described later is improved.

  When the formation of the first insulating film 57 is omitted, as shown in FIG. 5B, the first insulating film 57 is formed on the back surface of the silicon wafer 51 including the via hole VH without using the photoresist layer. Anisotropic etching is performed on the second insulating film 59a. As a result, the second insulating film 59a remains on the side wall of the via hole VH, and this becomes the side wall insulating film 59a. Further, since the second insulating film 59a formed on the back surface of the silicon wafer 51 is formed thicker than the second insulating film 59a located at the bottom of the via hole VH, the anisotropic etching is performed. After that, it remains as an insulating film. That is, only the second insulating film 59a located at the bottom of the via hole VH is removed.

  Next, as shown in FIG. 6, a barrier layer 61 made of, for example, titanium nitride (TiN) is formed on the back surface of the silicon wafer 51 including the buffer layer 60. The barrier layer 61 may be made of a metal other than titanium nitride (TiN) as long as it functions as a barrier layer. For example, the barrier layer 61 may be composed of titanium tungsten (TiW), tantalum nitride (TaN), and a compound of the above metal.

  Further, a seed layer (not shown) is formed on the barrier layer 61 including the inside of the via hole VH from the back surface side of the silicon wafer 51 by any method such as sputtering, MOCVD, or electroless plating.

  This seed layer (not shown) serves as a plating electrode for plating growth during later-described electrolytic plating. Its thickness may be about 1 μm. When the via hole VH is processed to have a forward taper, a sputtering method can be used to form a seed layer (not shown).

  Then, copper (Cu) electroplating is performed on a seed layer (not shown), but before that, as shown in FIG. 7, a photoresist layer 62 is selectively formed in a region where electroplating is not performed. To do. This region is a region on the back surface of the silicon wafer 51 excluding the region where the wiring layer 63 and the solder ball 66 are formed.

  Next, as shown in FIG. 8, the wiring layer 63 is formed by performing electrolytic plating of copper (Cu). The wiring layer 63 extends from the via hole VH to the back surface of the silicon wafer 51 and covers the buffer layer 60. As a result, the wiring layer 63 is electrically connected to the pad electrode 53 via the seed layer and barrier layer 61 (not shown).

  Note that a desired number of wiring layers 63 can be formed in a desired region on the back surface of the silicon wafer 51.

  In FIG. 8, the wiring layer 63 is completely embedded in the via hole VH, but may be embedded incompletely by adjusting the plating time. The wiring layer 63 is formed so as to be embedded in the bihole VH by electrolytic plating of copper (Cu), but is not limited to this, and may be formed by other methods. For example, the wiring layer 63 may be formed by performing plating formation of copper (Cu) after plating formation of tin (Sn). Alternatively, the wiring layer 63 may be formed by a method of embedding a metal such as copper (Cu) in the via hole VH by a CVD method or an MOCVD method. The wiring layer 63 may be formed by sputtering using a metal such as aluminum (Al).

  Then, the photoresist layer 62 is removed, and the seed layer and the barrier layer 61 (not shown) remaining under the photoresist layer 62 are removed by etching using the wiring layer 63 as a mask. At this time, the wiring layer 63 is also etched, but there is no problem because the wiring layer 63 is thicker than the seed layer.

  7 and 8, the photoresist layer 62 is formed in a partial region on the back side of the silicon wafer 51, and then the wiring layer 63 is formed using this as a mask. However, the present invention is not limited to this. Instead, the wiring layer 63 may be formed as follows, for example. That is, although not shown, after a metal layer for the wiring layer 63 is formed on the entire back surface of the silicon wafer 51 including the via hole VH, a photoresist layer is formed on the metal layer, and patterning is performed using the photoresist layer as a mask. Thus, the wiring layer 63 may be formed.

Next, as shown in FIG. 9, a silicon oxide film (SiO ₂ film) or a silicon nitride film (SiN film) is formed on the wiring layer 63 and the first insulating film 57 so as to cover the wiring layer 63. A reinforcing layer 64 is formed. Further, a roughening process is performed on the reinforcing layer 64 to form fine irregularities on the surface.

This roughening treatment is performed using, for example, any one of a mixed gas of CHF ₃ gas and CF ₄ gas, a mixed gas of CF ₄ gas and O ₂ gas, or a mixed gas of C ₄ F ₈ gas and SF ₆ gas. It is performed by the dry etching used. Note that these mixed gases may contain Ar gas for dilution. Alternatively, for example, it is performed by wet etching using NH ₄ F (ammonium fluoride) and H ₂ O ₂ (hydrogen peroxide) as an etching solution. Alternatively, for example, the sputtering may be performed using Ar gas or O ₂ gas. The surface of the roughened reinforcing layer 64 is shown in an enlarged view in FIG.

  Next, as shown in FIG. 10, a solder mask 65, which is a protective layer, is formed on the roughened reinforcing layer 64. Here, since the surface of the reinforcing layer 64 in contact with the solder mask 65 is a rough surface, that is, a surface on which fine irregularities are formed, the reinforcing layer 64 is reinforced as compared with the case where the surface is not roughened. The adhesion of the solder mask 65 to the layer 64 is ensured.

  The reinforcing layer 64 covers the entire surface on the back surface of the silicon wafer 51. As a result, the entire surface of the solder mask 65 covering the back side of the silicon wafer 51 is deposited in contact with the surface of the reinforcing layer 64 that has been roughened. Accordingly, the adhesion of the solder mask 65 is improved.

  Thereafter, a part of the solder mask 65 and the reinforcing layer 64 corresponding to the formation position of the buffer layer 60 is selectively removed by, for example, etching or the like, and an opening K that exposes the wiring layer 63 is provided at the part. .

  Next, as shown in FIG. 11, using a screen printing method, solder is printed on a predetermined region of the wiring layer 63, that is, on the wiring layer 63 exposed at the opening K, and the solder is reflowed by heat treatment. Thus, the solder ball 66 is formed. The solder ball 66 is not limited to solder, and may be formed using a lead-free low melting point metal material. Further, by appropriately selecting the number of openings K and formation regions, the solder balls 66 can be formed by freely selecting the number and formation regions. Instead of forming the solder balls 66 by solder, conductive terminals (provided at the locations where the solder balls 66 are formed) may be formed by plating.

  Then, as shown in FIG. 12, a dicing process is performed along a dicing line center DS in a dicing line region DL (not shown) to divide the silicon wafer 51 into a plurality of silicon chips 51A. In this dicing process, cutting is performed using a dicing blade.

  Next, a second embodiment of the present invention will be described with reference to the drawings. First, the structure of this semiconductor device will be described. FIG. 16 is a cross-sectional view of this semiconductor device, in which a semiconductor substrate that has undergone the steps described later, that is, a silicon wafer 51 is divided into individual semiconductor chips along a dicing line center DS in a dicing line region DL (not shown). Show. Note that the same components as those in FIG. 12 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the present embodiment, the reinforcing layer 64 is not formed on the wiring layer 63. That is, a solder mask 65 as a protective layer is formed on the wiring layer 63 so as to cover the wiring layer 63. Here, the surface of the first insulating film 57 in contact with the solder mask 65 or the surface of the first insulating film 57 and the wiring layer 63 is roughened so that fine unevenness (not shown) is formed. Yes. Thereby, the adhesion between the wiring layer 63 and the protective layer 65 is improved as compared with the case where the surface roughening treatment is not performed. About the structure concerning a point other than this, it is the same as 1st Embodiment.

  Next, a method for manufacturing a semiconductor device according to the second embodiment of the present invention described above will be described with reference to the drawings. In the manufacturing method of the semiconductor device according to the present embodiment, the photoresist layer 62 is selectively formed on the seed layer (not shown) excluding the formation region of the wiring layer 63 and the solder ball 66 from the first step (step shown in FIG. 1). The process up to the step of forming (step shown in FIG. 7) is the same as that of the first embodiment.

  After forming a photoresist layer 62 in a region on the seed layer (not shown), a wiring layer 63 is formed by electrolytic plating of copper (Cu) as shown in FIG. The method for forming the wiring layer 63 is the same as the method for forming the wiring layer 63 in the first embodiment.

  Then, the photoresist layer 62 is removed, and the seed layer and the barrier layer 61 (not shown) remaining under the photoresist layer 62 are removed by etching using the wiring layer 63 as a mask. At this time, the wiring layer 63 is also etched, but there is no problem because the wiring layer 63 is thicker than the seed layer.

  Here, a seed layer (not shown) and the barrier layer 61 remaining under the photoresist layer 62 are removed by the etching, and fine irregularities are formed on the surface of the first insulating film 57 exposed at the position. A roughening process is performed so as to form. Alternatively, the roughening treatment is performed on the surfaces of both the first insulating film and the wiring layer 63 exposed at that position. The surface of the first insulating film 57 and the wiring layer 63 when this roughening treatment is performed is shown in an enlarged view in FIG. Note that in the case where the formation of the first insulating film 57 is omitted, the surface of the second insulating film 59a is roughened.

This roughening treatment is performed using, for example, any one of a mixed gas of CHF ₃ gas and CF ₄ gas, a mixed gas of CF ₄ gas and O ₂ gas, or a mixed gas of C ₄ F ₈ gas and SF ₆ gas. It is performed by the dry etching used. Note that these mixed gases may contain Ar gas for dilution. Alternatively, for example, it is performed by wet etching using NH ₄ F (ammonium fluoride) and H ₂ O ₂ (hydrogen peroxide) as an etching solution. Alternatively, for example, sputtering may be performed using Ar or O ₂ .

  Next, as shown in FIG. 14, a solder mask 65 as a protective layer is formed on the first insulating film 57 and the wiring layer 63 subjected to the roughening process so as to cover the wiring layer 63. Here, the surface of the first insulating film 57 in contact with the solder mask 65 or the surfaces of the first insulating film 57 and the wiring layer 63 is a rough surface, that is, a surface on which fine irregularities are formed. Compared to the case where the surface roughening treatment is not performed, the adhesion of the solder mask 65 to the first insulating film 57 or the first insulating film 57 and the wiring layer 63 is improved.

  Thereafter, a part of the solder mask 65 corresponding to the formation position of the buffer layer 60 is selectively removed by, for example, etching, and an opening K that exposes the wiring layer 63 is provided at the part.

  Next, as shown in FIG. 15, using a screen printing method, solder is printed on a predetermined region of the wiring layer 63, that is, on the wiring layer 63 exposed at the opening K, and the solder is reflowed by heat treatment. Thus, the solder ball 66 is formed. Then, as shown in FIG. 16, a dicing process is performed along a dicing line center DS in a dicing line region DL (not shown) to divide the silicon wafer 51 into a plurality of silicon chips 51A.

  As described above, in the present embodiment, since the surface of the first insulating film 57 or the surface of the first insulating film and the wiring layer 63 is roughened, the surface roughening is not performed. Compared to the case, the adhesion of the solder mask 65 to the first insulating film 57 or the first insulating film and the wiring layer 63 is improved.

In both the first and second embodiments described above, the barrier layer 61 is made of titanium nitride (TiN), and NH ₄ F (ammonium fluoride) and H ₂ O ₂ (hydrogen peroxide) are etched into the etching solution. When the wet etching is performed, the first insulating film 57 (the second insulating film 59a when the formation of the first insulating film 57 is omitted) is roughened. The reason is considered as follows.

  The crystal structure of the barrier layer 61 in this case has a columnar structure composed of crystal grain boundaries as shown in the schematic diagram of the crystal structure of the titanium nitride layer in FIG. Then, during etching when removing the barrier layer 61, the etching solution exudes unevenly under the barrier layer 61 through the crystal grain boundaries. This non-uniformly exuded etching solution is a first insulating film 57 that is a roughened film formed under the barrier layer 61 (when the formation of the first insulating film 57 is omitted). It is considered that the surface is roughened by reaching the surface of the second insulating film 59a) and performing etching non-uniformly.

  The roughening treatment of the first insulating film 57 (the second insulating film 59a when the formation of the first insulating film 57 is omitted) is performed on the wiring layer 63 shown in FIG. This is performed in the process related to the formation and removal of the barrier layer 61.

  In both the first and second embodiments described above, the pad electrode 53 formed by extending the pad electrode used for normal wire bonding to the dicing line region DL is formed. However, the present invention is not limited to this. Instead of the pad electrode 53, a pad electrode used for normal wire bonding that is not expanded to the dicing line region DL may be used as it is. In this case, the formation position of the via hole VH may be aligned with this pad electrode, and the other steps are exactly the same.

  Although the present invention is applied to the BGA type semiconductor device in which the solder ball 66 is formed and the manufacturing method thereof, the present invention is not limited to this. That is, the present invention is also applicable to a semiconductor device in which solder balls are not formed and a method for manufacturing the same as long as it has a wiring layer formed in a via hole penetrating a silicon wafer. For example, the present invention is also applied to an LGA (Land Grid Array) type semiconductor device and a manufacturing method thereof.

It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing explaining the semiconductor device which concerns on the 1st Embodiment of this invention, and its manufacturing method. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing explaining the semiconductor device which concerns on the 2nd Embodiment of this invention, and its manufacturing method. It is a crystal structure schematic diagram of a titanium nitride layer. It is a figure explaining the conventional semiconductor device. It is a figure explaining the conventional semiconductor device.

Claims (22)

A pad electrode formed on the first main surface of the semiconductor chip;
A support bonded to the first main surface of the semiconductor chip;
A via hole penetrating from the second main surface of the semiconductor chip to the surface of the pad electrode;
A wiring layer electrically connected to the pad electrode through the via hole and extending from the via hole onto the second main surface of the semiconductor chip;
A reinforcing layer that is formed so as to cover the wiring layer and reinforces the wiring layer;
A protective layer formed on the reinforcing layer,
A surface of the reinforcing layer in contact with the protective layer is roughened. An insulating film formed from the second main surface of the semiconductor chip to the sidewall of the via hole;
An opening for opening a part of the reinforcing layer and the protective layer;
A conductive terminal formed on the wiring layer exposed at the opening,
The semiconductor device according to claim 1, wherein the wiring layer extends from the via hole onto a second main surface of the semiconductor chip including the insulating film. 3. The semiconductor device according to claim 1, wherein the reinforcing layer is made of a silicon oxide film or a silicon nitride film. A pad electrode formed on the first main surface of the semiconductor chip;
A support bonded to the first main surface of the semiconductor chip;
A via hole penetrating from the second main surface of the semiconductor chip to the surface of the pad electrode;
An insulating film formed from the second main surface of the semiconductor chip to the sidewall of the via hole;
A wiring layer electrically connected to the pad electrode through the via hole and extending from the via hole onto the second main surface of the semiconductor chip;
A protective layer formed on the wiring layer so as to cover the wiring layer;
The surface of the insulating film in contact with the protective layer or the surfaces of the insulating film and the wiring layer is roughened. A buffer layer provided on the insulating film;
An opening for opening a part of the protective layer;
A conductive terminal formed on the wiring layer exposed at the opening,
The semiconductor device according to claim 4, wherein the wiring layer extends from the via hole onto a second main surface of the semiconductor chip including the buffer layer. The semiconductor device according to claim 1, wherein the wiring layer is made of copper. The semiconductor device according to claim 1, wherein a barrier layer is formed under the wiring layer. 8. The semiconductor device according to claim 7, wherein the barrier layer is made of titanium nitride. Prepare a semiconductor substrate on which pad electrodes are formed,
Adhering a support to the first main surface of the semiconductor substrate;
Forming a via hole reaching the surface of the pad electrode from the second main surface of the semiconductor substrate;
Forming a barrier layer electrically connected to the pad electrode through the via hole and extending from the via hole onto the second main surface of the semiconductor substrate;
Forming a wiring layer on the barrier layer;
Forming a reinforcing layer on the wiring layer to reinforce the wiring layer so as to cover the wiring layer;
A step of roughening the surface of the reinforcing layer;
And a step of forming a protective layer on the reinforcing layer. Forming the first insulating film on the second main surface of the semiconductor substrate after bonding the support to the first main surface of the semiconductor substrate;
Forming a second insulating film on the entire second main surface of the semiconductor substrate including the inside of the via hole after forming the via hole;
Anisotropically etching the second insulating film to remove the second insulating film located at the bottom of the via hole, and forming a sidewall insulating film on the sidewall of the via hole;
After forming the reinforcing layer and the protective layer, etching the part of the reinforcing layer and the protective layer to form an opening exposing a part of the wiring layer;
Forming a conductive terminal on the wiring layer exposed at the opening;
The method for manufacturing a semiconductor device according to claim 9, further comprising: dividing the semiconductor substrate into a plurality of semiconductor chips. Forming an insulating film on the entire second main surface of the semiconductor substrate including the inside of the via hole after forming the via hole;
Anisotropically etching the insulating film, removing the insulating film located at the bottom of the via hole, and forming a sidewall insulating film on the side wall of the via hole;
After forming the reinforcing layer and the protective layer, etching the part of the reinforcing layer and the protective layer to form an opening exposing a part of the wiring layer;
Forming a conductive terminal on the wiring layer exposed at the opening;
The method for manufacturing a semiconductor device according to claim 9, further comprising a step of dividing the semiconductor substrate into a plurality of semiconductor chips. 11. The method of manufacturing a semiconductor device according to claim 9, wherein the reinforcing layer is made of a silicon oxide film or a silicon nitride film. The barrier layer is made of titanium nitride,
The method of manufacturing a semiconductor device according to claim 9, wherein the wiring layer is made of copper. 14. The method of manufacturing a semiconductor device according to claim 13, wherein the roughening process is performed by dry etching. The method of manufacturing a semiconductor device according to claim 13, wherein the roughening treatment is performed by wet etching. Prepare a semiconductor substrate on which pad electrodes are formed,
Adhering a support to the first main surface of the semiconductor substrate;
Forming a first insulating film on a second main surface of the semiconductor substrate;
Forming a via hole reaching the surface of the pad electrode from the first insulating film;
Forming a barrier layer electrically connected to the pad electrode through the via hole and extending from the via hole onto the second main surface of the semiconductor substrate;
Forming a wiring layer on the barrier layer;
Roughening the surface of the first insulating film or the surfaces of the first insulating film and the wiring layer;
And a step of forming a protective layer on the first insulating film and the wiring layer so as to cover the wiring layer. Forming a second insulating film on the entire second main surface of the semiconductor substrate including the inside of the via hole after forming the via hole;
Forming a buffer layer on the second insulating film;
Anisotropically etching the second insulating film to remove the second insulating film located at the bottom of the via hole, and forming a sidewall insulating film on the sidewall of the via hole;
After forming the barrier layer, the wiring layer and the protective layer, etching a part of the protective layer to form an opening exposing a part of the wiring layer;
Forming a conductive terminal on the wiring layer exposed at the opening;
The method of manufacturing a semiconductor device according to claim 16, further comprising: dividing the semiconductor substrate into a plurality of semiconductor chips. Prepare a semiconductor substrate on which pad electrodes are formed,
Adhering a support to the first main surface of the semiconductor substrate;
Forming a via hole reaching the surface of the pad electrode from the second main surface of the semiconductor substrate;
Forming an insulating film on a second main surface of the semiconductor substrate including the via hole;
Anisotropically etching the insulating film, removing the insulating film located at the bottom of the via hole, and forming a sidewall insulating film on the side wall of the via hole;
Forming a barrier layer electrically connected to the pad electrode through the via hole and extending from the via hole onto the second main surface of the semiconductor substrate;
Forming a wiring layer on the barrier layer;
Roughening the surface of the insulating film or the surfaces of the insulating film and the wiring layer;
And a step of forming a protective layer on the insulating film and the wiring layer so as to cover the wiring layer. Forming a buffer layer on the insulating film after forming the insulating film;
After forming the wiring layer and the protective layer, etching a part of the protective layer to form an opening exposing a part of the wiring layer;
Forming a conductive terminal on the wiring layer exposed at the opening;
The method of manufacturing a semiconductor device according to claim 18, further comprising a step of dividing the semiconductor substrate into a plurality of semiconductor chips. The barrier layer is made of titanium nitride,
20. The method of manufacturing a semiconductor device according to claim 16, wherein the wiring layer is made of copper. The method of manufacturing a semiconductor device according to claim 19, wherein the roughening process is performed by dry etching. The method of manufacturing a semiconductor device according to claim 19, wherein the roughening process is performed by wet etching.

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