JP2005254450A - 高電圧薄膜トランジスタを使用するmems装置のための集積化ドライバ電子工学 - Google Patents
高電圧薄膜トランジスタを使用するmems装置のための集積化ドライバ電子工学 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
- B81C1/00246—Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
- H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2203/00—Basic microelectromechanical structures
- B81B2203/01—Suspended structures, i.e. structures allowing a movement
- B81B2203/0118—Cantilevers
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
- B81C2203/0707—Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
- B81C2203/0735—Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
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Abstract
【解決手段】 ドライバ回路は、基板上に形成される複数の高電圧薄膜トランジスタ(HVTFT)を含み、各HVTFTは、制御ゲート電極、ソース電極、及び、該ソース電極が制御ゲート電極から第1の距離だけ離れるように配置されたドレイン電極を含む。このドレイン電極は、ドレイン電極のいずれか一部及び制御ゲート電極の間の最短距離が第1の距離より十分に大きいように、ドレイン電極及びソース電極間の第1の破壊電圧が制御ゲート電極及びソース電極間の第2の破壊電圧より大きいように、制御ゲート電極から離間される。複数の作動MEMS装置は、上記基板上に形成され、複数のHVTFTのうちの関連したHVTFTのドレイン電極にそれぞれ接続される。
【選択図】 図1
Description
Claims (3)
- 基板と、
前記基板上に形成された複数の高電圧薄膜トランジスタ(HVTFT)を含むドライバ回路であって、各HVTFTが、制御ゲート電極、ソース電極、及び、該ソース電極が制御ゲート電極から第1の距離だけ離れるように配置されたドレイン電極を含み、該ドレイン電極が、ドレイン電極の任意の一部分と制御ゲート電極との間の最短距離が前記第1の距離より顕著に大きいように、また、前記ドレイン電極及び前記ソース電極間の第1の破壊電圧が前記制御ゲート電極及び前記ソース電極間の第2の破壊電圧より大きいように制御ゲート電極から離間されている、前記ドライバ回路と、
前記基板上に形成されると共に前記複数のHVTFTの関連したHVTFTのドレイン電極にそれぞれ接続された複数の作動MEMS装置と、
を含むことを特徴とする装置。 - 基板と、
作動MEMS装置であって、前記基板の上に形成された作動電極、および該作動電極に隣接して配置された可動部を含むMEMS構造を含み、前記MEMS構造は、前記電極が第1の静電界を生成するときに前記可動部が前記基板に対して第1の位置に作動され、前記電極が第2の静電界を生成するときに前記可動部が前記基板に対して第2の位置に作動されるように形成された、作動MEMS装置と、
作動回路であって、前記作動電極が前記第1の静電界を生成する第1の作動電圧を前記作動MEMS装置に、または前記作動電極が前記第2の静電界を生成する第2の作動電圧を前記作動電極に、選択的に印加すべく前記基板に設けられた作動回路と、を含み、
前記作動回路は、前記基板上に形成される高電圧薄膜トランジスタ(HVTFT)を含み、該HVTFTは、制御ゲート電極、ソース電極、及び、該ソース電極の一部が前記制御ゲート電極から第1の距離だけ離れているように配置されたドレイン電極を含み、該ドレイン電極は、該ドレイン電極が前記第1の距離よりも顕著に大きいオフセット距離だけ前記制御ゲート電極から横方向にオフセットされるオフセット位置に配置されることを特徴とする装置。 - 最大論理電圧を有する制御信号を生成するための制御論理回路と、
低電圧源と、
前記最大論理電圧より顕著に高い作動電圧を提供するための高電圧源と、
前記制御回路に結合された制御ゲート電極、前記制御ゲート電極に相対的に近接して位置決めされると共に前記低電圧源に結合されたソース電極、及び、前記制御ゲート電極から相対的に離れて位置決めされると共に前記高電圧源に結合されたドレイン電極を含む、第1の高電圧薄膜トランジスタ(HVTFT)と、
第1のHVTFTのドレイン電極に接続される作動MEMS装置と、
を含むことを特徴とする装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US10/799,237 US6912082B1 (en) | 2004-03-11 | 2004-03-11 | Integrated driver electronics for MEMS device using high voltage thin film transistors |
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JP2011253922A Division JP2012076221A (ja) | 2004-03-11 | 2011-11-21 | 高電圧薄膜トランジスタを使用するmems装置のための集積化ドライバ電子工学 |
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JP2005069029A Pending JP2005254450A (ja) | 2004-03-11 | 2005-03-11 | 高電圧薄膜トランジスタを使用するmems装置のための集積化ドライバ電子工学 |
JP2011253922A Pending JP2012076221A (ja) | 2004-03-11 | 2011-11-21 | 高電圧薄膜トランジスタを使用するmems装置のための集積化ドライバ電子工学 |
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JP2011253922A Pending JP2012076221A (ja) | 2004-03-11 | 2011-11-21 | 高電圧薄膜トランジスタを使用するmems装置のための集積化ドライバ電子工学 |
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US (1) | US6912082B1 (ja) |
EP (1) | EP1574475B1 (ja) |
JP (2) | JP2005254450A (ja) |
CN (1) | CN100565924C (ja) |
Cited By (1)
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JP2020537334A (ja) * | 2017-09-26 | 2020-12-17 | ネーデルランドセ・オルガニサティ・フォール・トゥーヘパスト−ナトゥールウェテンスハッペライク・オンデルズーク・テーエヌオー | 高電圧薄膜トランジスタおよびその製造方法 |
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Also Published As
Publication number | Publication date |
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EP1574475B1 (en) | 2013-05-15 |
EP1574475A2 (en) | 2005-09-14 |
CN100565924C (zh) | 2009-12-02 |
CN1693181A (zh) | 2005-11-09 |
EP1574475A3 (en) | 2007-03-21 |
US6912082B1 (en) | 2005-06-28 |
JP2012076221A (ja) | 2012-04-19 |
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