JP2005244158A - 高密度ピンのボンディング構造 - Google Patents
高密度ピンのボンディング構造 Download PDFInfo
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Abstract
【解決手段】 主に公知のリードフレーム交差状ピンに改良を加え、リードフレームは複数排列のブロック状ピンを具え、該ピン底端には少なくとも1個の導接面を形成し、各ピンの導接面に少なくとも1個の絶縁体を設置し、かつ各ピンの絶縁体は間隔を開けた交差設置を呈し、これにより各絶縁体の相互に隣り合った露出状導接面は間隔を開けた交差排列状を呈する。
【選択図】図2
Description
図8及び図9に示すように、ウエハ30を搭載するリードフレーム10のピン20は多量かつ高密度の構造を具えている必要があるため、ソルダリング拡散により2本のピン20が相互接触する瑕疵を引起し易い。このため、市場ではリードフレーム10のピン20構造を製造する時、ピン20底部に突起ブロック201をプレス形成し、これにより該突起ブロック201底端を回路板と溶接する導接面202とし、しかも特に隣り合った別のピン20の突起ブロック201を異なる位置に設置し、これにより交差状排列を形成し、ソルダリングの相互付着を防止する方法がしばしば用いられる。
そのリードフレームの各ピンの突起ブロック構造は交差状排列を金型プレス製造により成型しなければならないため、金型製造が非常に困難である(特に針状のピンのプレス)ばかりでなく、リードフレームのコストを下げることもできない。
しかもプレス時には不良品が出易いため、品質管理コストの増加を招き、ボンディング完成後のICチップの歩留に悪影響を与えている。
本発明は上記構造の問題点を解決した高密度ピンのボンディング構造を提供するものである。
それは主にウエハを搭載し、対外導電性を構成するリードフレームのピンのボンディングに対して応用し、これによりピンは簡単にボンディングされ高密度交差排列構造を呈し、製造が容易となり、製造コスト及び品質管理コストを低下させることができ、
主にリードフレームを含み、該リードフレームは複数排列のブロック状ピンを具え、ピン底端面を対外電性の導接面とし、各ピンの導接面を選び少なくとも1個の絶縁体を設置し、かつ各ピンの絶縁体は間隔交差位置排列を呈し、これにより各絶縁体は相互に隣り合ったの露出状導接面を呈し、間隔交差排列状を形成し、こうしてピンは高密度排列を達成し、製造を簡単にし、しかも回路板の導接点上を選び上記間隔交差位置排列の絶縁体を設置し、ピンの交差排列を達成することを特徴とする高密度ピンのボンディング構造である。
特に、本発明の絶縁体構造及び排列状態の実施は、公知のピンをプレス加工し交差排列状の突起ブロックを成型する製造方式に比べ便利かつ簡単であるだけでなく、交差排列状の突起ブロックを直接するプレス成型するという困難な技術を採用する必要がなくなり、金型コスト、プレス製造コストの低下を実現することができる。しかも、簡単かつ精密に交差排列導接面のボンディングを実施可能で、品質管理を容易にし、ICの歩留及び安定性を増進することができる。
さらに、導接面の面積設計をやや大きくし、さらには回路板接点サイズ及び位置により、該絶縁体が遮蔽する範囲を随時制御可能であるため、露出交差排列状を呈する導接面には規格の弾力化が可能という利点が生じる。よって、回路板など外部設備との対応使用を十分に行うことができる。
該リードフレーム1はチップ3或いは外界電性設備(回路板の排列状接点位置及び数)の必要に応じて、複数の矩形ブロック状を構成する。しかも数列配置の金属ピン11構造を呈し、これによりブロック状ピン11は上端に少なくとも一個のチップ3搭載面111を具える。該ピン11下端面は外界との電性接続の導接面112とする。その排列数及び排列状態は図2及び図7に示すように、二列、四列或いはその他の数とし、平行或いは放射状或いは他の規則的或いは不規則的な形状排列とすることができる。しかも、各ピン11の排列はリードフレーム1の方式を構成し、金属材質を用い製成し、直接該チップ3に搭載し、モールディング4により封入しダイジングした後、ピン11が独立、固定し、対外的に電気的に接続するリードフレーム1を構成する。或いは金属材質によりピン11を製造後、先ずモールディングにより固定しかつダイジング(すなわち、チップ3を搭載する前に先にモールディングによりピン11を固定する)を行い、チップ3を搭載可能なリードフレーム1独立した物品として構成する。
或いは図5に示すように、該ブロック状ピン11は内端及び中央に近い位置においてそれぞれ凹状階段面113cを形成し、これにより2個の間隔が開いた突起ブロック114c及びその底面の導接面112を形成する。これによりそれぞれその中の一個の突起ブロック114の導接面112を選び、遮蔽し交差排列を構成する絶縁体2を設置し、もう一方の突起ブロック114の導接面112は露出し交差排列状を呈する。こうしてピン11間のソルダリング相互付着の発生を防止することができる。本発明ピン11構造は特定のものに限定されず。ピン11底端を対外導接点とすることができる任意の構造形状はすべて上記特徴により絶縁体2遮蔽部分を実施することができる。
すなわち、ピン11の底端導接面112において成形或いは接着固定し、一部分を絶縁遮蔽する実施例においても、本発明の該絶縁体2構造及び交差排置特徴を達成することができる。
11 ピン
111 搭載面
112 導接面
113a、113b、113c 凹状階段面
114a、114b、114c 突起ブロック
2 絶縁体
3 チップ
4 モールディング
5 金属リード
Claims (3)
- 主にリードフレームを含み、
該リードフレームはチップを搭載し外部と電気的に接続させるための物品で、複数の矩形ブロック状でしかも数列配置のピン構造を構成し、該ブロック状ピンは下端面に外界との電性接続を行うための導接面を具え、
少なくとも一個の絶縁体により該導接面の一部分を選び遮蔽し、しかも各ピンの絶縁体は間隔を開け交差する排列状設置を呈し、こうして、各絶縁体は相互に隣り合った露出状を呈し、該導接面も間隔を開け交差する排列状態を形成し、これによりピンは交差露出状排列を構成することを特徴とする高密度ピンのボンディング構造。 - 前記ピンの形状は矩形ブロック状を含み、
また底端に少なくとも一個の凹状階段面を形成し、該凹状階段面の相互に隣り合った位置において突起ブロック及びその底面の一導接面を形成することも可能で、
また底端内側及び中央に近い位置にそれぞれ凹状階段面を形成し、これにより2個の間隔が開いた突起ブロック及びその底面の導接面を形成し、それぞれその中の一個の突起ブロックの導接面を選び遮蔽し絶縁体を設置することを特徴とする請求項1記載の高密度ピンのボンディング構造。 - 前記絶縁体は絶縁膜により接着、点モールディング、或いはモールディングにより構成することができ、前記リードフレームに前記チップを搭載する前、或いは後に実施可能であることを特徴とする請求項1記載の高密度ピンのボンディング構造。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW093104819A TWI253736B (en) | 2004-02-25 | 2004-02-25 | Composition structure of high-density pin |
Publications (1)
Publication Number | Publication Date |
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JP2005244158A true JP2005244158A (ja) | 2005-09-08 |
Family
ID=34859739
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2004238437A Pending JP2005244158A (ja) | 2004-02-25 | 2004-08-18 | 高密度ピンのボンディング構造 |
Country Status (3)
Country | Link |
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US (1) | US20050184365A1 (ja) |
JP (1) | JP2005244158A (ja) |
TW (1) | TWI253736B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008300717A (ja) * | 2007-06-01 | 2008-12-11 | Denso Corp | モールドパッケージ |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6826827B1 (en) | 1994-12-29 | 2004-12-07 | Tessera, Inc. | Forming conductive posts by selective removal of conductive material |
US7453157B2 (en) * | 2004-06-25 | 2008-11-18 | Tessera, Inc. | Microelectronic packages and methods therefor |
US7863737B2 (en) * | 2006-04-01 | 2011-01-04 | Stats Chippac Ltd. | Integrated circuit package system with wire bond pattern |
US9288905B2 (en) | 2013-11-11 | 2016-03-15 | Seagate Technology Llc | Shaped internal leads for a printed circuit substrate |
TWI761052B (zh) * | 2021-01-28 | 2022-04-11 | 瑞昱半導體股份有限公司 | 積體電路導線架及其半導體裝置 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6281568B1 (en) * | 1998-10-21 | 2001-08-28 | Amkor Technology, Inc. | Plastic integrated circuit device package and leadframe having partially undercut leads and die pad |
JP3062192B1 (ja) * | 1999-09-01 | 2000-07-10 | 松下電子工業株式会社 | リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置の製造方法 |
-
2004
- 2004-02-25 TW TW093104819A patent/TWI253736B/zh not_active IP Right Cessation
- 2004-08-18 JP JP2004238437A patent/JP2005244158A/ja active Pending
- 2004-10-07 US US10/959,203 patent/US20050184365A1/en not_active Abandoned
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008300717A (ja) * | 2007-06-01 | 2008-12-11 | Denso Corp | モールドパッケージ |
Also Published As
Publication number | Publication date |
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US20050184365A1 (en) | 2005-08-25 |
TW200414477A (en) | 2004-08-01 |
TWI253736B (en) | 2006-04-21 |
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