JP2005244007A - Method for manufacturing printed wiring board with cavity - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a printed wiring board with a cavity for preventing the disconnection of a wiring layer applied to a cavity peripheral part formed in the cavity. <P>SOLUTION: In the method for manufacturing the printed wiring board with the cavity which is obtained by forming the cavity on which a semiconductor chip, a passive component, etc. are to be mounted by the spotfacing of an NC working machine, a line width correction area is previously formed on a prescribed position of the wiring layer applied to the cavity peripheral part formed by spotfacing and the cavity is formed by the spotfacing to produce the printed wiring board with the cavity. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a printed wiring board with a cavity having a cavity for mounting a semiconductor chip, a passive component, and the like.

  High integration of semiconductor devices tends to increase year by year, and it is required to mount this type of semiconductor device on a printed wiring board at high density. In order to realize high-density mounting of a semiconductor device on a printed wiring board, a packaged semiconductor device is not mounted on a printed wiring board, but semiconductor chips and passive components that are not packaged on the printed wiring board are mounted. Several techniques for direct mounting have been proposed (see, for example, Patent Document 1).

  Also, in the so-called surface mounting, where various electronic components are mounted on the surface of a printed wiring board, two-dimensional mounting structures using a flat surface such as single-sided mounting or double-sided mounting, several types of bare chip mounting are performed within the same plane. Even if it makes full use of it, it has become difficult to respond to further higher density mounting. For this reason, recently, a three-dimensional mounting structure and a stacked mounting structure, in which the mounting form is not limited to the same plane, have been proposed. As a means for realizing a three-dimensional or stacked type mounting structure, a printed wiring board is a multilayer wiring board, and a concave depression called a cavity is applied to the multilayer wiring board in advance, and a semiconductor chip and a cavity are formed in the cavity. A cavity structure for mounting passive components and the like is often used.

FIG. 5 (a) is a schematic cross-sectional view showing an example of a conventional printed wiring board with a cavity, FIG. 5 (b) is a schematic top view of FIG. 5 (a) as seen from the BB ′ plane, respectively. Show.
In FIG. 5A, a printed wiring board 200 with a cavity is formed by forming a cavity 151 at a predetermined position of an insulating material 112. In the cavity 151, an electrode pad 122 ′ and an electrode pad 122 ′ are provided. A connected wiring layer 123 ′ is formed.
Furthermore, a semiconductor chip, passive components, etc. are mounted in the cavity 151, and a cavity type mounting substrate apparatus can be obtained.

Hereinafter, the manufacturing method of the printed wiring board 200 with a cavity is demonstrated.
6 (a) to 6 (e) and FIGS. 7 (f) to (i) are schematic configuration partial cross-sectional views illustrating an example of a method for manufacturing the printed wiring board 200 with a cavity.

First, a double-sided copper-clad laminate in which copper foils 121 are laminated on both sides of an insulating base 111 made of glass epoxy is prepared (see FIG. 6A).
Next, a photosensitive layer 131 is formed on both sides of the double-sided copper-clad laminate by a method such as laminating a dry film (see FIG. 6B), and patterning treatment such as pattern exposure and development is performed. Resist patterns 131a and 131b are formed (see FIG. 6C).

  Next, using the resist patterns 131a and 131b as an etching mask, the copper foil 121 is etched using an etching solution such as ferric chloride solution, and the resist patterns 131a and 131b are stripped with a dedicated stripping solution. A pad electrode 122, a wiring layer 123 and a wiring layer 124 connected to the pad electrode 122 are formed on one surface of the material 111, and a land 125 is formed on the other surface of the insulating substrate 111 (see FIG. 6D).

Next, the prepreg (glass epoxy) sheet and the copper foil 141 are laminated by heating and pressing to obtain a laminate on which the insulating layer 112 and the copper foil 141 are laminated (see FIG. 6D).
Next, the photosensitive layer 1 is laminated by a method such as laminating a dry film on the copper foil 141 of the laminate.
32 is formed (see FIG. 7F), and a patterning process such as pattern exposure and development is performed to form a resist pattern 132a (see FIG. 7G).

  Next, a protective layer 151 is formed by applying a mask tape on the land 125 of the insulating substrate 111, and the copper foil 141 is formed using an etching solution such as cupric chloride using the resist pattern 132a as an etching mask. Etching is performed, and the resist pattern 132a is stripped with a dedicated stripping solution, the protective layer 151 is stripped, and a land 142 is formed at a predetermined position on the insulating layer 112 (see FIG. 7H).

Next, a predetermined position of the insulating layer 112 is countersunk with a router bit to form a cavity 151 (see FIG. 7I).
Here, the pad electrode 122 and the upper portion of the wiring layer 123 connected to the pad electrode 122 are scraped with a router bit in order to secure an electrical connection surface of the pad electrode 122. Although the amount of cutting depends on the thickness of the copper foil 121, it is about 6 to 12 μm. When a 35 μm copper foil is used as the copper foil 121, the film thickness of the pad electrode 122 ′ in the cavity 151 and a part of the wiring layer 123 ′ connected to the pad electrode 122 ′ is 29 to 23 μm.
JP 2001-223322 A

  As described above, the method of forming the cavity by spotting the insulating material with the router bit is that the pad electrode and a part of the wiring layer are scraped when the router bit is spotted and the periphery of the cavity. Then, when the stress of the router bit is greatly applied and the processed surface height varies due to the warping of the laminated board, the wiring layer around the cavity is partially lost or dished down ( There is a case in which a deficient defect such as a dish occurs) and a problem that leads to disconnection of the wiring layer may occur.

  Accordingly, an object of the present invention is to provide a method for manufacturing a printed wiring board with a cavity for preventing disconnection of a wiring layer around the cavity formed in the cavity.

  In order to achieve the above object, the present invention provides a method for manufacturing a printed wiring board with a cavity, in which a cavity for mounting a semiconductor chip, a passive component, and the like is formed by spot facing of an NC processing machine. A printed wiring with a cavity, characterized in that a line width correction region is provided at a predetermined position of the wiring layer on the periphery of the cavity, and the line width of the wiring layer in the line width correction region is increased in advance to perform spot facing processing. This is a method for manufacturing a plate.

  The method for manufacturing a printed wiring board with a cavity according to the present invention provides a predetermined wiring layer applied to the periphery of the cavity when a cavity for mounting a semiconductor chip, a passive component, or the like is formed by spot facing of an NC processing machine. By providing a line width correction area at the position and correcting the line width of the wiring layer in the line width correction area thickly in advance, reliability that does not lead to disconnection of the wiring layer even if loss or dishdown occurs It is possible to provide a printed wiring board having the same.

FIG. 1A is a schematic cross-sectional view showing an example of a printed wiring board with cavities obtained by the method for manufacturing a printed wiring board with cavities of the present invention. FIG. 1B is a schematic top view of FIG. 1A viewed along the plane AA ′, and is an explanatory view showing the shapes of the wiring layer 23 and the line width correction region 23 a around the cavity 51.
A printed wiring board with a cavity 100 shown in FIG. 1A is an example of a four-layer printed wiring board in which a cavity 51 is formed at a predetermined position of an insulating material 12.
FIG. 1B shows the shape of the pad electrode formed in the cavity 51 and the shape of the wiring layer 23 and the line width correction region 23a in the periphery of the cavity 51. It can be seen that a part of the line width of the wiring layer 23 is corrected to be thick.

Hereinafter, a method for producing a printed wiring board with a cavity according to the present invention will be described.
2 (a) to 2 (e) and FIGS. 3 (f) to 3 (i) are schematic cross-sectional views showing an embodiment of the method for producing a printed wiring board with a cavity according to the present invention in the order of steps.

First, a double-sided copper-clad laminate in which copper foils 21 are laminated on both sides of an insulating base material 11 made of glass epoxy or the like is prepared (see FIG. 2 (a)).
Next, on both sides of this double-sided copper-clad laminate, a photosensitive layer 31 is formed by a method such as laminating a dry film or the like (see FIG. 2B), and patterning treatment such as pattern exposure and development is performed. Resist patterns 31a and 31b are formed (see FIG. 2C).

  Next, using the resist patterns 31a and 31b as an etching mask, the copper foil 21 is etched using an etching solution such as ferric chloride, and the resist patterns 31a and 31b are stripped with a dedicated stripping solution to form an insulating group. A pad electrode 22, a wiring layer 23 connected to the pad electrode 22 and a line width correction region 23a are formed on one surface of the material 11, and a wiring layer 25 is formed on the other surface of the insulating base 11 (FIG. 2D). And FIG. 4).

Here, the wiring layer 23 and the line width correction region 23a will be described.
FIG. 4 shows a partially enlarged plan view of the pad electrode 22, the wiring layer 23, and the line width correction region 23 a formed in the cavity on the insulating base material 11.
The wiring layer 23 connected to the pad electrode 22 is normally formed with the same line width. However, when a part of the wiring layer 23 covers the cavity 51 formation region (particularly, the cavity peripheral portion), the cavity is formed. 51. A line width correction region 23a is provided at a predetermined position of the wiring layer 23 around the periphery, and the line width of the wiring layer 23 is corrected to be thick.
The line width of the line width correction region 23 a is preferably about 1.5 to 2 times that of the wiring layer 23.

Next, the prepreg (glass epoxy) sheet and the copper foil 41 are laminated by heating and pressing to obtain a laminate on which the insulating material 12 and the copper foil 41 are laminated (see FIG. 2D).
Next, a photosensitive layer 32 is formed on the copper foil 41 of the laminated board by a method such as laminating a dry film or the like (see FIG. 3F), and patterning treatment such as pattern exposure and development is performed to form a resist. A pattern 32a and a resist pattern 32b are formed (see FIG. 3G).

  Next, using the resist pattern 32a and the resist pattern 32b as an etching mask, the copper foil 41 is etched using an etching solution such as ferric chloride, and the resist pattern 32a and the resist pattern 32b are stripped with a dedicated stripping solution. Then, lands 42 and lands 43 are formed at predetermined positions on the insulating material 12 (see FIG. 3H).

Next, a predetermined position of the insulating material 12 is countersunk with a router bit to form a cavity 51, and a pad electrode 22 ′ in which the upper part of the electrode and wiring layer is scraped off with the router bit in the cavity 51, wiring A layer 23 ′ and a line width correction region 23a ′ are formed (see FIGS. 3I and 1B). Further, in the periphery of the pad electrode 22 ′, the wiring layer 23 ′, and the line width correction region 23 a ′ in the cavity 51, insulation having the same height as the pad electrode 22 ′, the wiring layer 23 ′, and the line width correction region 23 a ′ is provided. Layer 12a is formed.
Here, the pad electrode 22, the wiring layer 23, and the line width correction region 23 formed on the insulating base material 11.
a is a router bit when the insulating material 12 is countersunk with a router bit so that the upper part of the pad electrode 22, the wiring layer 23 and the line width correction region 23 a secures an electrical connection surface above the pad electrode 22. A predetermined amount is cut. Although the amount of cutting depends on the thickness of the copper foil 21, it is about 6 to 12 μm. When a 35 μm copper foil is used as the copper foil 21, the film thicknesses of the pad electrode 22 ′, the wiring layer 23 ′, and the line width correction region 23a ′ in the cavity 51 are 29 to 23 μm.

  As described above, the method for manufacturing a printed wiring board with a cavity according to the present invention has a cavity for mounting a semiconductor chip, a passive component, and the like in a cavity peripheral portion when the cavity is formed by a spot machining of an NC processing machine. By providing a line width correction area at a predetermined position in such a wiring layer and correcting the line width of the wiring layer in the line width correction area to be large in advance, even if a defect or dishdown occurs, the wiring layer is disconnected. It is possible to provide an unreliable printed wiring board.

  First, a photosensitive dry film was laminated at a pressure of 1.5 MPa and a laminating speed of 1.0 m / min on both sides of a double-sided copper-clad laminate obtained by laminating a 35 μm copper foil 21 on an insulating base material 11 made of an epoxy resin. Thus, a photosensitive layer 31 having a thickness of 25 μm was formed (see FIGS. 2A and 2B).

Next, pattern exposure is performed with an ultraviolet ray having an exposure amount of 50 mj / cm ² using an exposure mask, and a 1% sodium carbonate aqueous solution at 30 ° C. is spray-developed at a pressure of 1.5 MPa to form resist patterns 31a and 31b. (See FIG. 2 (c)).

  Next, using the resist patterns 31a and 31b as an etching mask, the copper foil 21 was etched by spray-etching a copper etching solution made of cupric chloride at a pressure of 1.5 MPa for 60 seconds. Further, the resist patterns 31a and 31b are spray-stripped with a 2.5% sodium hydroxide aqueous solution at 50 ° C. and a pressure of 1.5 MPa, and connected to one surface of the insulating substrate 11 with the pad electrode 22 and the pad electrode 22. The wiring layer 25 and the line width correction region 23a thus formed were formed on the other surface of the insulating substrate 11 (see FIG. 2D and FIG. 4).

Next, the prepreg (glass epoxy) sheet and the 35 μm copper foil 41 were heated and pressurized to obtain a laminated plate on which the insulating material 12 and the copper foil 41 were laminated (see FIG. 2D).
Next, the photosensitive dry film was laminated on the copper foil 41 of the laminated plate at a pressure of 1.5 MPa and a lamination speed of 1.0 m / min to form a photosensitive layer 32 having a thickness of 25 μm (FIG. 3F). reference).

Next, pattern exposure is performed with an ultraviolet ray having an exposure amount of 50 mj / cm ² using an exposure mask, and a 1% sodium carbonate aqueous solution at 30 ° C. is spray-developed at a pressure of 1.5 MPa to form resist patterns 32a and 32b. (See FIG. 3 (g)).

  Next, using the resist patterns 32a and 32b as an etching mask, the copper foil 41 was etched by spray-etching a copper etching solution made of cupric chloride at a pressure of 1.5 MPa for 60 seconds. Further, the resist patterns 31a and 31b were spray-peeled with a 2.5% sodium hydroxide aqueous solution at 50 ° C. and a pressure of 1.5 MPa to form lands 42 and lands 43 at predetermined positions on the insulating material 12 (FIG. 3 (h)).

Next, using a router bit having a router bit diameter of 1.0 mmφ attached to the NC processing machine at a predetermined position of the insulating material 12, the insulating material is rotated at a speed of 20000-30000 rpm and a feed rate of 0.1-0.5 m / min. 12 are spot-cut to form a cavity 51, a pad electrode 22 ′, a wiring layer 23 ′, and a line width correction region 23 a ′ are formed in the cavity 51, and a printed wiring board with a cavity is formed. It obtained (refer FIG.3 (i) and FIG.1 (b)).
Here, the thicknesses of the pad electrode 22 ′, the wiring layer 23 ′, and the line width correction region 23a ′ were 26 μm.
The disconnection of the wiring layer 23 ′ and the line width correction region 23a ′ was not confirmed, and a good printed wiring board with a cavity was obtained.

(A) is a schematic structure sectional view showing an example of a printed wiring board with a cavity obtained by the method for producing a printed wiring board with a cavity of the present invention.

(B) is the model top view which looked at (a) in the AA 'surface.
(A)-(e) is a partial composition sectional view showing typically a part of process in a manufacturing method of a printed wiring board with a cavity of the present invention. (F)-(i) is a partial structure sectional view showing typically a part of process in a manufacturing method of a printed wiring board with a cavity of the present invention. It is explanatory drawing which shows an example of the wiring layer concerning a cavity peripheral part, and a line | wire width correction area | region. (A) is a schematic structure sectional view showing an example of a conventional printed wiring board with a cavity.

(B) is the top view which looked at (a) in the BB 'surface.
(A)-(e) is a partial composition sectional view showing typically a part of process in the manufacturing method of the conventional printed wiring board with a cavity. (F)-(i) is a partial composition sectional view showing typically a part of process in the manufacturing method of the conventional printed wiring board with a cavity.

Explanation of symbols

11, 111 ...... Insulating base material 12, 112 ...... Insulating material 12 a, 112 a ...... Insulating layer 21, 41, 121, 141 ...... Copper foil 22, 22 ′, 122 ...... Pad electrode 23, 23 ′, 24, 25, 123, 124 ... wiring layers 23a, 23a '... line width correction regions 31, 32, 131, 132 ... photosensitive layers 31a, 31b, 32a, 32b, 131a, 131b, 132a ... resist patterns 42, 43 , 125 ... Land 51 ... Cavity 100, 200 ... Printed wiring board with cavity 151 ... Protective layer

Claims (1)

  In a method for manufacturing a printed wiring board with a cavity, in which a cavity for mounting a semiconductor chip, passive components, etc. is formed by spot machining of an NC processing machine, wiring around the cavity to be spotted A method of manufacturing a printed wiring board with a cavity, wherein a line width correction region is provided at a predetermined position of a layer, and the line width of the wiring layer in the line width correction region is increased in advance to perform spot facing.

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