JP2005223559A - Solid state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that, if there is a difference between the wiring resistances of vertical signal lines with constant current sources disposed at only first ends of the vertical signal lines, the shading is caused by a difference between the voltage drops on the vertical signal lines according to the distance from the constant current sources. <P>SOLUTION: Constant current sources 17-1 to 17-n, 19-1 to 19-n are disposed each at both ends of vertical signal lines 15-1 to 15-n, and the currents flowing on the vertical signal lines 15-1 to 15-n are reduced to about a half each to reduce the voltage drops due to the currents on the vertical signal lines 15-1 to 15-n to about a half each, thereby suppressing the shading caused by the voltage drops in the vertical direction. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device, and in particular, pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix, and pixel signals are transmitted through signal lines wired for each column with respect to the matrix-like arrangement of the pixels. The present invention relates to a solid-state imaging device configured to output.

  Solid-state imaging devices, such as CMOS (Complementary Metal-Oxide Semiconductor) image sensors, are used as image input devices such as various portable terminal devices, digital still cameras, and digital video cameras. As shown in FIG. 5, the CMOS image sensor has a pixel array unit 102 in which pixels 101 including photoelectric conversion elements are two-dimensionally arranged in a matrix, and wiring is arranged for each column with respect to the matrix arrangement of the pixels 101. The signal of the pixel 101 is output through the vertical signal line 103.

  In a solid-state imaging device represented by this CMOS image sensor that outputs a signal of a pixel 101 through a vertical signal line 103, a constant current source 104 required for signal readout is provided on one end side of the vertical signal line 103. The structure which connected these is taken (for example, refer patent document 1). The constant current source 104 constitutes a source follower circuit with the amplification transistor Q12 in the pixel 101. Then, a voltage change corresponding to the amount of signal charge photoelectrically converted by the photodiode PD which is a photoelectric conversion element is amplified by the amplification transistor Q12 and output to the vertical signal line 103 as a signal of the pixel 101.

Japanese Patent Laid-Open No. 11-103418

  As described above, in the solid-state imaging device in which the constant current source 104 is connected to one end of the vertical signal line 103, the pixels 101 corresponding to the number of pixels in the vertical direction are connected on one vertical signal line 103. For this reason, the constant current source 104 is closer to the pixel that is closer to the constant current source 104 (distance to the constant current source 104 is shorter) and the pixel that is farther from the constant current source 104 (longer to the constant current source 104). Due to the difference in the distance between them, the wiring resistance R and the parasitic capacitance C that are always included in the vertical signal line 103 are also greatly different.

  Specifically, when the resistance value of the wiring resistance R between the middle pixel in the vertical direction and the constant current source 104 is used as a reference value, the distance between the pixel near the constant current source 104 and the constant current source 104 is The resistance value of the wiring resistance R becomes smaller as the distance becomes shorter than the reference value, and the resistance value of the wiring resistance R between the pixel far from the constant current source 104 and the constant current source 104 is smaller than the reference value. Also increases as the distance increases.

  Thus, since the vertical signal line 103 has a wiring resistance component having a resistance value corresponding to the length, when a current flows, a voltage drop occurs in the vertical signal line 103 due to the influence of the resistance component. The voltage drop on the vertical signal line 103 is determined by the wiring resistance R and the parasitic capacitance C. Therefore, if there is a difference in the resistance value of the wiring resistance R due to the difference in the distance between the pixel 101 and the constant current source 104, the voltage drop on the vertical signal line 103 also depends on the distance from the constant current source 104. Therefore, shading (difference in light and darkness) is caused in the vertical direction.

  Further, as shown in FIG. 5, when each of the vertical signal lines 103 is connected to one ground wiring 105 through the constant current source 104 and one end of the ground wiring 105 is grounded, the number of pixels is reduced. In many solid-state imaging devices, the number of vertical signal lines 103 is inevitably large, and a large current flows through the ground wiring 105 at a time. Therefore, the ground wiring 105 separated from the actual ground potential (one end of the ground wiring 105). The potential increases at the upper position, and as a result, the ground level increases at the vertical signal line 103 connected to the position. The increase in the ground level is also caused by the wiring resistance component included in the ground wiring 105. Since the resistance value of the wiring resistance varies depending on the distance, the level of the ground level increases for each vertical signal line 103. A difference is made. This difference in the increase level of the ground level is a factor that causes shading in the horizontal direction.

  Further, the variation in threshold voltage of the MOS transistors constituting the constant current source 104 becomes a current variation for each vertical signal line 103, and the current variation for each vertical signal line 103 causes the generation of vertical streak noise on the captured image. It becomes.

  Therefore, the present invention occurs due to shading caused in the vertical direction due to a voltage drop on the vertical signal line in which a difference occurs according to the distance from the constant current source, and current variation for each vertical signal line. A first object is to provide a solid-state imaging device capable of suppressing vertical streak noise.

  It is a second object of the present invention to provide a solid-state imaging device capable of suppressing shading caused in the horizontal direction due to a difference in the degree of increase in ground level for each vertical signal line.

  In order to achieve the first object, a solid-state imaging device according to the present invention includes a pixel array unit in which pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix, and a matrix of the pixels in the pixel array unit. Wired for each column with respect to the array, a signal line for outputting a signal from the pixel, a first constant current source connected to one end side of the signal line, and connected to the other end side of the signal line And a second constant current source.

  In the solid-state imaging device having the above configuration, each of the first and second constant current sources constitutes an amplification transistor and a source follower circuit in the pixel. When pixels are selected in units of rows, signals are output from the pixels in the selected row to the signal lines, and currents flowing through the signal lines are supplied to the first and second constant current sources provided at both ends of the signal lines. It flows toward. At this time, assuming that the first and second constant current sources have substantially the same characteristics, the current output from the pixel is substantially divided into two and flows into the first and second constant current sources. As a result, a current about half of the current output from the pixel flows through the signal line. Therefore, the voltage drop on the signal line that varies depending on the distance from the constant current source has the greatest difference in potential. Even in some cases, it can be reduced to about half compared to the case where the constant current source is provided only on one end side of the signal line. Further, the current variation is reduced by reducing the current to about half.

  In order to achieve the second object, another solid-state imaging device according to the present invention includes a pixel array unit in which pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix, and the pixels of the pixel array unit. A signal line that is wired for each column with respect to the matrix arrangement and that outputs a signal from the pixel, a first constant current source having one end connected to one end side of the signal line, and the other end of the signal line A second constant current source having one end connected to the side, a first signal processing means for processing a signal output from the one end side of the signal line, and an output from the other end side of the signal line A second signal processing means for processing a signal; a first ground wiring connected to the other end of the first constant current source and wired along a row of the matrix arrangement; and one end grounded; Connected to the other end of the second constant current source and wired along the rows of the matrix array Is, one end of the other end of the first ground wiring has a configuration in which a second ground wiring which is grounded.

  In another solid-state imaging device having the above-described configuration, the signal output from the pixel in the selected row to the signal line is read out in a substantially half-divided state via the first and second signal processing means. The bisected signal is processed by a signal processing system outside the apparatus to become a signal for one pixel. Here, when a large current flows at a time and a potential rise occurs at a position away from the actual ground potential on the first and second ground wirings, the first and second ground wirings are in the pixels of the row. Since the wiring ends opposite to each other in the arrangement direction (row direction) are grounded, the distribution of potential rise in the row direction is opposite between the first ground wiring side and the second ground wiring side. Specifically, taking the wiring end of the first ground wiring on the ground side as an example, the potential rise is almost zero at the wiring end of the first ground wiring because it is closest to the actual ground potential. Thus, the wiring end on the same side as the first ground wiring of the second ground wiring is farthest from the actual ground potential, so that the potential rise is maximum. As a result, the increase in the ground level of the signal line due to the potential increase in the first and second ground wirings is reversed between the signal lines in the row direction, and the increase in the ground level also affects the pixel signal. The reverse is true between pixels in the row direction. Therefore, the pixel signal that has passed through the first and second signal processing means is added in the signal processing system outside the apparatus, for example, to perform an arithmetic process that takes an average to obtain a pixel signal due to an increase in the ground level of the signal line. Can be almost equalized. Further, since the number of ground lines is two, the current that flows through the ground line at a time is almost half that of a single line. Therefore, the potential on the ground line is increased, and the ground level of the signal line is increased. The rise is also reduced to about half.

  According to the present invention, when the constant current source is provided only on one end side of the signal line even when the voltage drop on the signal line that causes a difference according to the distance from the constant current source has the greatest difference in potential. Since it is about half of that, shading caused by the voltage drop in the vertical direction can be suppressed, and current variation is reduced, so that vertical streak noise can be suppressed. In addition, the increase in the ground level of the signal line can be reduced to about half that of a single ground line, and the influence on the pixel signal due to the increase in the ground level of the signal line can be made almost equal. Therefore, shading caused in the horizontal direction due to a difference in the degree of increase in the ground level for each signal line can be suppressed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing a configuration example of a solid-state imaging device, for example, a CMOS image sensor according to the first embodiment of the present invention.

  In FIG. 1, a pixel (pixel circuit) 11 including a photoelectric conversion element, for example, a photodiode PD, is two-dimensionally arranged in a pixel array of m rows and n columns to constitute a pixel array unit 12. In the pixel array section 12, transfer control lines 13-1 to 13-m and reset control lines 14-1 to 14-m are wired for each row with respect to the matrix arrangement of the pixels 11, and a vertical signal is provided for each column. Lines 15-1 to 15-n are wired. The pixel 11 has a three-transistor pixel configuration including, for example, a transfer transistor Q11, an amplification transistor Q12, and a reset transistor Q13 in addition to the photodiode PD. The transfer transistor Q11, the amplification transistor Q12, and the reset transistor Q13 are configured by, for example, Nch MOS transistors.

  In the pixel (pixel circuit) 11, the photodiode PD is provided with the anode electrode grounded. The transfer transistor Q11 has a source connected to the cathode electrode of the photodiode PD, a drain connected to the FD (floating diffusion) portion, and a gate connected to the transfer control lines 13-1 to 13-m. Signal charges (photoelectrons) obtained by the conversion are transferred to the FD section. Here, the FD portion is a diffusion layer having parasitic capacitance. The amplification transistor Q12 has a gate connected to the FD portion, a drain connected to the power supply potential VDD, and a source connected to the vertical signal lines 15-1 to 15-n, and a signal (reset level / signal) corresponding to the potential of the FD portion. Level) is output to the vertical signal lines 15-1 to 15-n. The reset transistor Q13 has a source connected to the FD portion, a drain connected to the power supply potential VDD, and a gate connected to the reset control lines 14-1 to 14-m, and resets the potential of the FD portion to the power supply potential VDD.

  Here, the case of a three-transistor configuration has been described as an example, but the pixel 11 is not limited to this configuration, for example, a four-transistor configuration having a selection transistor for selecting a pixel. It is also possible to use it.

  The vertical drive circuit 16 is configured by a shift register, for example, and selects each pixel 11 of the pixel array unit 12 in units of rows, and transfers the pixels 11 in the selected row through transfer control lines 13-1 to 13-m. The signal TRF is given as a reset signal RST through reset control lines 14-1 to 14-m, respectively. Here, the selection of the pixels 11 in units of rows is performed by a selection signal SEL supplied from a vertical drive circuit 16 to a power supply control circuit (not shown) in synchronization with vertical scanning, and in response to this, from the power supply control circuit. This is performed by supplying the power supply potential VDD to the pixels 11 in the selected row.

  FIG. 2 shows a timing relationship among the selection signal SEL, the reset signal RST, and the transfer signal TRF. Based on the selection signal SEL, the pixels 11 are selected in units of rows. Then, in the selected row, the reset signal RST is given to the pixel 11 so that the potential of the FD portion is reset to the power supply potential VDD, and the potential of the FD portion after the reset is set as a reset level via the amplification transistor Q12. 15-1 to 15-n. Thereafter, the transfer signal RTF is applied to the pixel 11, whereby the signal charge photoelectrically converted by the photodiode PD is transferred to the FD portion, and the potential of the FD portion after the transfer is vertically converted as a signal level through the amplification transistor Q13. It is output to the signal lines 15-1 to 15-n.

  One end of each of the constant current sources 17-1 to 17-n is connected to one end of each of the vertical signal lines 15-1 to 15-n. The constant current sources 17-1 to 17-n are configured by, for example, a current mirror circuit using MOS transistors, and configure an amplification transistor Q12 in the pixel 11 and a source follower circuit. A ground wiring 18 is connected to the other ends of the constant current sources 17-1 to 17-n. The ground wiring 18 is wired in the horizontal direction of the drawing along the rows of the matrix arrangement of the pixels 11, and one end thereof is grounded (connected to the ground potential GND).

  One end of each of the constant current sources 19-1 to 19-n is connected to the other end of each of the vertical signal lines 15-1 to 15-n. The constant current sources 19-1 to 19-n are constituted by, for example, current mirror circuits using MOS transistors, and constitute a source follower circuit with the amplification transistor Q12 in the pixel 11. As the constant current sources 19-1 to 19-n, for example, those having substantially the same characteristics as the constant current sources 17-1 to 17-n are used. A ground wiring 20 is connected to each other end of the constant current sources 19-1 to 19-n. The ground wiring 20 is wired in the horizontal direction of the drawing along the rows of the matrix arrangement of the pixels 11, and one end thereof is grounded.

  Signals taken out from the ends of the vertical signal lines 15-1 to 15-n on the constant current sources 17-1 to 17-n side are, for example, CDS (Correlated Double Sampling) circuits constituting signal processing means. 21-1 to 21-n. These CDS circuits 21-1 to 21-n take in a reset level and a signal level output from each pixel 11 in the selected row, and obtain a pixel signal for one row by taking a difference between these levels. A process of removing the fixed pattern noise of the pixel 11 is performed.

  The pixel signals after the signal processing by the CDS circuits 21-1 to 21-n are sequentially selected by the horizontal selection switches 22-1 to 22-n and output through the horizontal signal line 23. The horizontal selection switches 22-1 to 22-n are selectively driven by horizontal scanning signals φH1 to φHn that are sequentially output from the horizontal scanning circuit 24. The horizontal scanning circuit 24 is configured by, for example, a shift register.

  In the CMOS image sensor according to the first embodiment having the above-described configuration, when the pixels 11 are selected in units of rows by vertical scanning by the vertical drive circuit 16, the vertical signal lines 15-1 to 15-n from the pixels 11 in the selected rows. A signal is output at. At this time, the currents flowing through the vertical signal lines 15-1 to 15-n are constant current sources 17-1 to 17-n and 19-1 to 19-19 provided at both ends of the vertical signal lines 15-1 to 15-n. Flows towards -n. Here, since the constant current sources 17-1 to 17-n and 19-1 to 19-n have substantially the same characteristics, the current output from the pixel 11 is substantially divided into two, and the constant current source 17- 1-17-n, 19-1 to 19-n. As a result, about half of the current output from the pixel 11 flows through the vertical signal lines 15-1 to 15-n.

  The vertical signal lines 15-1 to 15-n have a wiring resistance R and a parasitic capacitance C having resistance values corresponding to the lengths. As a result, when a current flows through the vertical signal lines 15-1 to 15-n, a voltage drop determined by the wiring resistance R and parasitic capacitance C occurs on the vertical signal lines 15-1 to 15-n. At that time, the CMOS image sensor according to the present embodiment has a configuration in which the constant current sources 17-1 to 17-n and 19-1 to 19-n are arranged at both ends of the vertical signal lines 15-1 to 15-n. As a result, the current flowing through the vertical signal lines 15-1 to 15-n is approximately half, so that even when the voltage drop due to the current has the greatest difference in potential, the current flows to one end of the vertical signal line. Only a constant current source is arranged, and it can be suppressed to about half compared with the prior art.

  FIG. 3 shows the currents in the vertical signal lines when two constant current sources are arranged for one vertical signal line (this embodiment) and when one constant current source is arranged (conventional technology). The simulation result which measured the electric potential of the vertical signal line when flowing is shown.

  In FIG. 3, the case where there are two constant current sources is indicated by a solid line, and the case where there is one constant current source is indicated by a dotted line. In either case, the characteristic marked with ○ is the potential at the position closest to the constant current source on the vertical signal line, and the characteristic marked with △ is the potential at the position farthest from the constant current source on the vertical signal line. The characteristics indicated by x indicate the potential at the intermediate position.

  As is clear from the simulation results of FIG. 3, the potential difference between the position closest to the constant current source on the vertical signal line and the position farthest from the constant current source is about 50 [mV when there is one constant current source. In contrast, when the number of constant current sources is two, it is about 25 [mV], and the voltage drop on the vertical signal line due to the current flowing through the vertical signal line is the highest in the potential. It can be seen that even when there is a difference, it can be suppressed to about half compared with the conventional technique in which the constant current source is arranged only on one end side of the vertical signal line. As described above, since the voltage drop occurring on the vertical signal lines 15-1 to 15-n can be greatly reduced, shading caused in the vertical direction due to the voltage drop can be suppressed.

  Further, since the current flowing through the vertical signal lines 15-1 to 15-n is about half that of the conventional technique in which the constant current source is arranged only at one end side of the vertical signal lines, the constant current sources 17-1 to 17-1 are reduced. Since current variations due to variations in threshold voltages of the MOS transistors constituting 17-n and 19-1 to 19-n are also reduced, vertical streak generated on the captured image due to the current variations. Noise can also be suppressed.

  In the present embodiment, the constant current sources 17-1 to 17-n and 19-1 to 19-n provided at both ends of the vertical signal lines 15-1 to 15-n are used by using substantially the same characteristics. In the above description, the configuration in which the current flowing through the vertical signal lines 15-1 to 15-n is suppressed to almost half has been described as a preferable example. Even if the characteristics of 17-1 to 17-n and 19-1 to 19-n are different, current is divided and flows through the vertical signal lines 15-1 to 15-n, so that the vertical signal lines 15- Since the current flowing in 1 to 15-n can be reduced as compared with the case where a constant current source is provided only on one end side, a voltage drop due to the current can also be suppressed.

[Second Embodiment]
FIG. 4 is a block diagram showing a configuration example of a CMOS image sensor according to the second embodiment of the present invention. In FIG. 4, the same parts as those in FIG. Here, for simplification of the drawing, the configuration of the pixel 11, the vertical drive circuit 16, the horizontal selection switches 22-1 to 22-n, the horizontal signal line 23, and the horizontal scanning circuit 24 are omitted.

  In the CMOS image sensor according to this embodiment, in addition to the configuration of the CMOS image sensor according to the first embodiment, first and second signal processing means are provided on both ends of the vertical signal lines 15-1 to 15-n. For example, CDS circuits 21A-1 to 21A-n and 21B-1 to 21B-n are arranged to take out the signal of one pixel 11 from both ends of the vertical signal lines 15-1 to 15-n, and at a constant current. One end of the ground wiring 18 on the sources 17-1 to 17-n side (in this example, the wiring end A on the right side of the figure) is grounded, whereas the ground wiring on the constant current sources 17-1 to 17-n side is grounded. No. 20 has a configuration in which one end on the other end side of the ground wiring 18 (in this example, the wiring end B on the left side of the drawing) is grounded.

  In the CMOS image sensor having the above configuration, when constant current sources 17-1 to 17-n, 19-1 to 19-n having, for example, substantially the same characteristics are used, the signal of one pixel 11 is approximately 2. The divided data are read out through the CDS circuits 21A-1 to 21A-n and 21B-1 to 21B-n, respectively. Then, a signal for one pixel is obtained by performing arithmetic processing in a signal processing system outside the sensor.

  Here, in the CMOS image sensor having a large number of pixels, the number n of the vertical signal lines 15-1 to 15-n is inevitably large, and a large current flows through the ground wirings 18 and 20 at a time. 18 and 20, the potential rises at a position away from the actual ground potential (the ground ends A and B of the ground wirings 18 and 20), and as a result, the vertical signal lines 15-1 to 15-15 connected to the position. At -n, the ground level increases. At this time, since the wiring ends A and B opposite to each other in the row direction (left and right direction in the figure) are grounded, the distribution of the potential rise in the row direction is the same as the ground wiring 18 side and the ground wiring. The opposite is true for the 20 side.

  Specifically, when the wiring end A on the ground side of the ground wiring 18 is taken as an example, the potential rise is almost zero at the wiring end A of the ground wiring 18 because it is closest to the actual ground potential. In the ground wiring 20, the wiring end on the same side as the wiring end A of the ground wiring 18 (the wiring end on the side opposite to the wiring end B) is farthest from the actual ground potential, so that the potential rise is maximum. Conversely, in the case of the wiring end on the opposite side of the ground wiring 18 (wiring end on the side opposite to the wiring end A), the potential rise is maximum because the wiring end is farthest from the actual ground potential. On the other hand, at the wiring end B on the same side as the ground wiring 18 in the ground wiring 20, the potential rise is almost zero because it is closest to the actual ground potential.

  As a result, the degree of the increase in the ground level of the vertical signal lines 15-1 to 15-n due to the increase in the potential of the ground wirings 18 and 20 is reversed between the vertical signal lines 15-1 to 15-n in the row direction. The effect on the pixel signal due to the increase in the ground level is also reversed between the pixels in the row direction. Therefore, the vertical signal line 15 is obtained by performing, for example, arithmetic processing of adding and averaging the pixel signals that have passed through the CDS circuits 21A-1 to 21A-n and 21B-1 to 21B-n in the signal processing system outside the sensor. The influence on the pixel signal due to the increase in the ground level of −1 to 15-n can be made almost equal. As a result, shading caused in the horizontal direction due to a difference in the degree of increase in the ground level for each of the vertical signal lines 15-1 to 15-n can be suppressed.

  In addition, since the two ground wirings 18 and 20 are provided, the current flowing through the ground wirings 18 and 20 is almost half as compared with the case of one ground wiring. The increase in the potential of the vertical signal lines 15-1 to 15-n connected to the ground wirings 18 and 20 can be suppressed to about half. The same applies to the CMOS image sensor according to the first embodiment.

  In each of the above-described embodiments, the case where the present invention is applied to a CMOS image sensor has been described as an example. However, the present invention is not limited to this application example, and the present invention is a two-dimensional array of pixels including photoelectric conversion elements. The present invention is applicable to all solid-state imaging devices that are arranged and output pixel signals through signal lines wired for each column with respect to the matrix-like arrangement of the pixels.

  The solid-state imaging device according to the present invention is used as an image input device such as a mobile terminal device represented by a mobile phone or a PDA (Personal Digital Assistants), a digital still camera, or a digital video camera.

1 is a block diagram illustrating a configuration example of a CMOS image sensor according to a first embodiment of the present invention. 5 is a timing chart showing a timing relationship among a selection signal SEL, a reset signal RST, and a transfer signal TRF. It is a characteristic view showing a simulation result of measuring the potential of the vertical signal line when two constant current sources are arranged for one vertical signal line and when one constant current source is arranged. It is a block diagram which shows the structural example of the CMOS image sensor which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the structural example of the CMOS image sensor which concerns on a prior art example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Pixel (pixel circuit), 12 ... Pixel array part, 15-1 to 15-n ... Vertical signal line, 16 ... Vertical drive circuit, 17-1 to 17-n, 19-1 to 19-n ... Constant current Sources 18, 20 ... ground wiring, 211-1 to 21-n, 21A-1 to 21A-n, 21-1B to 21B-n ... CDS circuit, 22-1 to 22-n ... horizontal selection switch, 23 ... Horizontal signal line, 24 ... horizontal scanning circuit

Claims (5)

A pixel array unit in which pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix;
A signal line that is wired for each column with respect to the matrix arrangement of the pixels of the pixel array unit, and that outputs signals from the pixels;
A first constant current source connected to one end of the signal line;
A solid-state imaging device comprising: a second constant current source connected to the other end of the signal line. The solid-state imaging device according to claim 1, wherein the first and second constant current sources have substantially the same characteristics. A pixel array unit in which pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix;
A signal line that is wired for each column with respect to the matrix arrangement of the pixels of the pixel array unit, and that outputs signals from the pixels;
A first constant current source having one end connected to one end of the signal line;
A second constant current source having one end connected to the other end of the signal line;
First signal processing means for processing a signal output from the one end side of the signal line;
Second signal processing means for processing a signal output from the other end of the signal line;
A first ground wiring connected to the other end of the first constant current source and wired along the rows of the matrix arrangement, and having one end grounded;
A second ground wiring connected to the other end of the second constant current source and wired along the rows of the matrix arrangement, and having one end on the other end side of the first ground wiring grounded. A solid-state imaging device characterized by the above. The solid-state imaging device according to claim 3, wherein the first and second constant current sources have substantially the same characteristics. The solid-state imaging device according to claim 3, wherein the first and second signal processing means process signals of the same pixel.

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