JP5672363B2 - Solid-state imaging device and camera system - Google Patents

Description

  The present invention relates to a solid-state imaging device and a camera system that perform a shutter operation by a rolling shutter system.

In an image sensor in which photoelectric conversion elements are arranged in a matrix, a global shutter system and a rolling shutter (focal plane shutter) system are known as electronic shutter systems.
In the global shutter method, the shutter operation is performed on all pixels simultaneously, whereas in the rolling shutter method, the electronic shutter operation is performed in units of one to several rows.
In many cases, the reading is performed in units of one to several lines in both the global shutter method and the rolling shutter method. The row for electronic shutter and the row for reading in the rolling shutter system shift with time.

FIG. 1 is a diagram for convenience showing shutter and lead operations in the rolling shutter system.
In FIG. 1, the horizontal axis represents time, and the vertical axis represents the address of the read row performing the read operation and the shutter row performing the shutter operation. The unit of the horizontal axis is a horizontal readout period (H) that is a readout period for one row.

In the example of FIG. 1, the accumulation time is Tint, and the timing for accessing the same row address is shifted by the time Tint between the shutter row and the lead row.
The shutter row and the lead row are sequentially selected by shifting the Ln rows from the address LS to the address LE every horizontal readout period (1H).
In this case, the shutter operation is finished earlier than the lead by the time Tint.

As described above, if the shutter is finished before reading, a row where reading and shuttering are simultaneously performed and a row where only reading is performed are formed depending on the address.
In the example of FIG. 1, the shutter and the reading are simultaneously performed in the period t1, and only the reading is performed in the period t2.

As described above, it is known that when the number of shutters is changed in the middle of reading, horizontal band noise called a shutter step or FIBAR (Fixed Integration bar) is generated.
This is due to the fact that the power load changes between the case where the shutter and reading are performed simultaneously and the case where only reading is performed, and the output value to be read changes.

On the other hand, Patent Document 1 discloses a method of making the power load constant by performing a shutter operation of a dummy row.
In this method, as shown in FIG. 1, after the shutter operation from the address LS to LE is completed, the shutter operation of the dummy row is performed so that the power load is constant during the read periods t1 and t2. Yes.

The method described in Patent Document 1 is effective when the accumulation time is always constant between consecutive frames.
However, when the accumulation time is changed between frames, there is a disadvantage that the number of shutters cut together with the lead changes depending on the row, and a shutter step is generated.

  On the other hand, Patent Document 2 discloses a method in which dummy pixels having two or more shutters for two frames are provided and the shutter operation is constantly performed for two frames to make the number of shutters constant.

FIG. 2 is a diagram illustrating an example of shutter and read operations when the shutter operation is always performed for two frames.
In this case, by providing the dummy shutter DST2 in addition to the dummy shutter DST1, the shutter operation for two frames is always performed.

A CMOS (Complimentary Metal Oxide Semiconductor) image sensor (CIS) has a feature that a read address can be set relatively freely with respect to a CCD (Charge Coupled Device) image sensor.
For example, in addition to reading all pixels of a sensor, sensors having functions such as “addition” for simultaneously reading signals of a plurality of pixels and “decimation” for intermittent reading while skipping rows and columns are widely used. .

In an image sensor, a phenomenon called blooming is known in which signal charge overflows from a saturated photodiode (hereinafter referred to as PD) to an adjacent PD and the signal amount changes.
In particular, when the rolling shutter system is employed, blooming occurs and the image quality deteriorates if the charges accumulated in the pixels that are not read out are appropriately discarded during the “thinning” operation.

On the other hand, there has been proposed a method for suppressing blooming by cutting a shutter (hereinafter referred to as blooming prevention shutter) for discarding charges from pixels that are not read (see Patent Document 3).
In the case of releasing the blooming prevention shutter during the “decimation” operation or in the “addition” operation, a plurality of lines are selected simultaneously.

FIG. 3 is a diagram illustrating an example of read and shutter row addresses when two rows are “added” and half of the rows are “thinned”.
In FIG. 3, the unit of the horizontal axis is a horizontal readout period (H) which is a readout period for one row.

In FIG. 3, at time t5, row addresses “n + 9” and “n + 11” are simultaneously selected, added and read.
Row addresses “n + 17” and “n + 19” are readout frame shutters, row addresses “n” and “n + 2” are shutters of the next frame, row addresses “n + 21” and “n + 23”, and “n + 4” and “n + 6” are blooming. It is a prevention shutter.

JP 2001-8109 A JP 2005-269098 A JP 2008-193618 A

As described above, in a CMOS image sensor that performs “addition” and “thinning” operations, the number of shutter rows per frame increases.
For example, at time t5 in FIG. 3, the shutter is performed for eight rows. As the “addition” pixel and “thinning” ratio increase, the number of shutters increases.
Therefore, as described in Patent Document 2, if dummy pixels corresponding to the number of shutter rows for two frames are provided, the number of dummy pixels increases, which disadvantageously increases cost and power consumption.

  An object of the present invention is to provide a solid-state imaging device and a camera system capable of greatly reducing the number of dummy shutters used for suppressing noise in an image generated by a shutter step in one frame period.

A solid-state imaging device according to a first aspect of the present invention includes a pixel unit in which a plurality of pixels that convert an optical signal into an electrical signal and store the electrical signal according to an exposure time are arranged in a matrix, and a plurality of dummy A dummy pixel unit in which pixels are arranged in a matrix , and an electronic shutter operation of the pixel unit and the dummy pixel unit according to a shutter mode switching signal , and an operation of the pixel to perform reading, and a row unit in case of an electronic shutter in a rolling shutter method for performing an electronic shutter, a maximum shutter speed of the frame being read, the image element driving unit that determines whether to perform either a read period the shutter to the dummy pixels, the a flow dummy pixels of the pixel and the dummy pixel unit of the pixel portion includes a photoelectric conversion element for generating a signal charge from incident light, said signal charges A transfer transistor for transferring the I ring diffusions, the floating diffusion anda reset transistor connected to a predetermined potential, the pixel driver, the shutter and the shutter row simultaneously in parallel for the next frame of the frame being read out period In the first period in which the shutter of the frame is performed simultaneously in parallel, the transfer transistor and the reset transistor of the shutter row pixel of the read target frame and the shutter row pixel of the next frame are included. At the same time, the transfer transistor and the reset transistor of the dummy pixel are turned off. In the second period in which the shutters for the frames outside the first period are not performed simultaneously in parallel, the transfer transistors and the reset transistors of the pixels in the shutter row of the readout target frame or the pixels in the shutter row of the next frame are set. At the same time, the transfer transistor and the reset transistor of the dummy pixel are simultaneously turned on .

A camera system according to a second aspect of the present invention includes a solid-state imaging device, an optical system that forms a subject image on the solid-state imaging device, and a signal processing circuit that processes an output image signal of the solid-state imaging device. The solid-state imaging device converts a light signal into an electrical signal, and stores a plurality of pixels that store the electrical signal according to an exposure time in a matrix, and a plurality of dummy pixels in a matrix. In accordance with the arranged dummy pixel unit and the shutter mode switching signal, the electronic shutter operation of the pixel unit and the dummy pixel unit and the operation of the pixel to perform reading are controlled, and the electronic shutter is performed in units of rows. When electronic shuttering is performed using the rolling shutter method, the readout period for shuttering the dummy pixels is determined based on the maximum number of shutters in the frame being read. Has a picture element driving unit that, the dummy pixels of the pixel and the dummy pixel unit of the pixel unit transfers a photoelectric conversion element for generating a signal charge from incident light, said signal charges to the floating diffusion transfer A pixel and a reset transistor that connects the floating diffusion to a predetermined potential , and the pixel driver has a period in which the shutter of the frame during the readout period and the shutter of the next frame are simultaneously performed in parallel. In the first period in which the shutter of the frame is performed simultaneously in parallel, the transfer transistor and the reset transistor of the pixel of the shutter row of the read target frame and the pixel of the shutter row of the next frame are simultaneously turned on, and The transfer transistor of the dummy pixel and the OFF the set transistor. In the second period in which the shutters for the frames outside the first period are not performed simultaneously in parallel, the transfer transistors and the reset transistors of the pixels in the shutter row of the readout target frame or the pixels in the shutter row of the next frame are set. At the same time, the transfer transistor and the reset transistor of the dummy pixel are simultaneously turned on .

  According to the present invention, the number of dummy shutters used for suppressing noise in an image generated by a shutter step in one frame period can be greatly reduced.

It is a figure showing the operation of the shutter and the lead in the rolling shutter system for convenience. It is a figure which shows the example of the operation | movement of a shutter and a lead in the case of always performing the shutter operation | movement for 2 frames. FIG. 10 is a diagram illustrating an example of read and shutter row addresses when two rows are “added” and half of the rows are “thinned”. It is a figure which shows the structural example of the CMOS image sensor (solid-state image sensor) which concerns on the 1st Embodiment of this invention. It is a figure which shows an example of the pixel circuit which concerns on this embodiment. It is a figure which shows an example of the dummy pixel circuit which concerns on this embodiment. 3 is a timing chart of the CMOS image sensor according to the present embodiment. FIG. 4 is an explanatory diagram of pixel signal reading (reading) and a shutter according to the embodiment. It is a figure showing and showing operation of a shutter and lead in this embodiment for convenience. It is a figure which shows an example of a structure of the camera system with which the solid-state image sensor which concerns on the 2nd Embodiment of this invention is applied.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The description will be given in the following order.
1. First Embodiment (Configuration Example of CMOS Image Sensor (Solid-State Imaging Device))
2. Second Embodiment (Configuration Example of Camera System)

<1. First Embodiment>
FIG. 4 is a diagram illustrating a configuration example of a CMOS image sensor (solid-state imaging device) according to the embodiment of the present invention.

The CMOS image sensor 100 includes a pixel array unit 110, a dummy pixel array unit 120, a row selection circuit 130, a dummy selection circuit 140, a row selection control circuit 150, and a readout circuit (AFE) 160.
The row selection circuit 130, the dummy selection circuit 140, and the row selection control circuit 150 constitute a pixel driver.

  Further, the CMOS image sensor 100 includes an input terminal T101 for an operation mode selection signal MDS, a data output terminal T102, a pixel power supply terminal T103, and a row selection circuit power supply terminal T104.

The pixel array section 110 of the CMOS image sensor 100, the dummy pixel array section 120, a row selection circuit 130, Oyo the beauty dummy selection circuit 140, an external power supply 170 through the pixel power supply terminal T103, and the row selection circuit the power supply terminal T104 Power is being supplied from.
Ideally, it is desirable that there is no wiring impedance between the power supply 170 and each block constituting the CMOS image sensor 100.
However, since finite impedances Zall, Zpx, and Zrs actually exist, noise may propagate to the pixel power supply when the row selection circuit 130 operates.
In the configuration example of FIG. 4, the pixel power supply and the row selection circuit power supply are supplied from separate PADs (terminals) 103 and 104. However, two power supplies are connected in the CMOS image sensor 100, and one external power supply is connected. You may supply with PAD.

  In the pixel array unit 110, a plurality of pixel circuits are arranged in a two-dimensional shape (matrix shape) of M rows × N columns.

  FIG. 5 is a circuit diagram illustrating an example of a pixel circuit according to the present embodiment.

This pixel circuit 110A has a photoelectric conversion element (hereinafter sometimes simply referred to as PD) made of, for example, a photodiode (PD).
Each of the photoelectric conversion elements PD has one transfer transistor TRG-Tr, one reset transistor RST-Tr, one amplification transistor AMP-Tr, and one selection transistor SEL-Tr.

The photoelectric conversion element PD generates and accumulates signal charges (here, electrons) corresponding to the amount of incident light.
Hereinafter, a case where the signal charge is an electron and each transistor is an N-type transistor will be described. However, the signal charge may be a hole or each transistor may be a P-type transistor.
This embodiment is also effective when a plurality of photoelectric conversion elements share each transistor or when a three-transistor (3Tr) pixel that does not have a selection transistor is employed.

The transfer transistor TRG-Tr is connected between the photoelectric conversion element PD and the FD (Floating Diffusion) and is controlled through the control line TRG.
The transfer transistor TRG-Tr is selected when the control line TRG is in the high level (H) and becomes conductive, and transfers the electrons photoelectrically converted by the photoelectric conversion element PD to the FD.

The reset transistor RST-Tr is connected between the power supply lines VRst and FD, and is controlled through the control line RST.
The reset transistor RST-Tr becomes conductive when the control line RST is selected during the H period, and resets the FD to the potential of the power supply line VRst.

The amplification transistor AMP-Tr and the selection transistor SEL-Tr are connected between the power supply line VDD and the vertical signal line LSGN.
An FD is connected to the gate of the amplification transistor AMP-Tr, and the selection transistor SEL-Tr is controlled through a control line SEL.
The selection transistor SEL-Tr is selected when the control line SEL is H and becomes conductive. Thereby, the amplification transistor AMP-Tr outputs a signal VSL corresponding to the potential of the FD to the vertical signal line LSGN.

  Since the pixel array 110A has M rows × N columns arranged in the pixel array unit 110, there are M control lines SEL, RST, and TRG, respectively, and N vertical signal lines LSGN of the signal VSL.

  In the dummy pixel array unit 120, dummy pixel circuits are arranged in a matrix of MD rows × N columns.

  FIG. 6 is a diagram illustrating an example of the dummy pixel circuit according to the present embodiment.

The dummy pixel circuit 120A includes at least a dummy transfer transistor DTRG-Tr and a dummy reset transistor DRST-Tr.
The dummy pixel circuit 120A preferably includes a dummy photoelectric conversion element DPD, a dummy selection transistor DSEL-Tr, and a dummy amplification transistor DAMP-Tr.

The dummy transfer transistor DTRG-Tr is connected between the dummy photoelectric conversion elements DPD and FD, and is controlled through the control line DUMMY_TRG.
The transfer transistor DTRG-Tr is in a conductive state when the control line DUMMY_TRG is selected to be H, and transfers the electrons photoelectrically converted by the dummy photoelectric conversion element DPD to the FD.

The dummy reset transistor DRST-Tr is connected between the power supply lines VRst and FD, and is controlled through the control line DUMMY_RST.
The dummy reset transistor DRST-Tr is selected during the period when the control line DUMMY_RST is H and resets the FD to the potential of the power supply line VRst.

With the configuration as described above, the load (resistance / capacitance) of the control line DUMMY_RST is approximately the same as that of the control line RST. Further, the load (resistance / capacitance) of the control line DUMMY_TRG is approximately the same as that of the control line TRG.
If the loads on the control line DUMMY_RST and the control line RST, the control line DUMMY_TRG, and the control line TRG are approximately the same, the dummy photoelectric conversion element DPD, the dummy selection transistor DSEL-Tr, and the dummy amplification transistor DAMP-Tr may be omitted. Absent.

The row selection circuit 130 selects pixels of the pixel array unit 110 according to the row selection control signal SCTL from the row selection control circuit 150.
The row selection circuit 130 has a function of performing pixel drive control by switching the exposure method to a rolling shutter method in which exposure is performed for each row or a global shutter method in which all pixels are exposed simultaneously in accordance with a shutter mode switching signal.

  The dummy selection circuit 140 selects a dummy pixel of the dummy pixel array unit 120 according to the row selection control signal SCTL from the row selection control circuit 150.

The row selection control circuit 150 controls which row is selected in accordance with an operation mode selection signal MDS that is an external control signal.
The row selection control circuit 150 has a function of determining the maximum number of shutter rows in a frame and determining the number of shutter rows of dummy pixels when performing electronic shutter using the rolling shutter method.
When the shutter of the frame being read out in the frame and the shutter of the next frame are simultaneously performed, the row selection control circuit 150 is a dummy pixel so that the number of shutter rows in the read period in the frame is always two frames. Control the shutter operation.
When the shutter of the frame being read out in the frame and the shutter of the next frame are not simultaneously released, the row selection control circuit 150 performs a dummy so that the number of shutter rows in the read period in the frame is always one frame. Controls the shutter operation of the pixel.
In the present embodiment, dummy shutters are provided as many as the number of shutter rows in the frame.

The readout circuit 160 performs predetermined processing on the signal VSL output through the vertical signal line LSGN from each pixel circuit 110A in the readout row selected by driving of the row selection circuit 130, for example, a pixel signal after signal processing Hold temporarily.
For example, a circuit configuration including a sample hold circuit that samples and holds a signal output through the vertical signal line LSGN can be applied to the read circuit 160.
Alternatively, the readout circuit 160 includes a sample-and-hold circuit, and a circuit configuration including a function of removing fixed pattern noise unique to a pixel such as reset noise and threshold variation of an amplification transistor by CDS (correlated double sampling) processing is applicable. is there.
In addition, the reading circuit 160 can have a configuration in which an analog-digital (AD) conversion function is provided and a signal level is a digital signal.

FIG. 7 is a timing chart of the CMOS image sensor according to this embodiment having the above configuration.
FIG. 7 shows one horizontal readout period (1H period).

The read row RDR sets the control line SEL to H and outputs the signal VSL to the vertical signal line LSGN. Next, the control line RST is set to H and FD is reset to VRst.
Thereafter, the control line RST is set to a low level (L) to read the reset level.
Then, the control line TRG is set to H, and the electric charge photoelectrically converted by the photoelectric conversion element PD is transferred to the FD. After the transfer, the control line TRG is set to L to read the signal VSL.

In the shutter row STRR, the control line RST and the control line TRG are simultaneously set to H at any timing in the horizontal readout period, and the photoelectric conversion element PD is reset to VRst.
Further, the dummy shutter row DSTRR sets the dummy control line DUMMY_RST at the same timing as the control line RST of the shutter row STRR, and the dummy control line DUMMY_TRG at the same timing as the control line TRG.
Thereby, even when the number of shutter rows changes in the frame FRM, the power load is made constant and the occurrence of a shutter step is prevented.

FIG. 8 is an explanatory diagram of pixel signal reading (reading) and a shutter according to the present embodiment.
FIG. 8 shows the case of “two-pixel addition” in which two pixels are “added” and read out simultaneously.
Further, a case where a “1/2 thinning-out” operation for skipping half of the pixels is shown. In FIG. 8, the horizontal axis represents time, and the vertical axis represents the row address of the pixel array. The unit of time is the horizontal readout period (H).

  In the figure, the white circle indicates the lead row RDR, the black circle indicates the shutter NFSTR row of the next frame, and the hatched circle row indicates the readout shutter RFSTR row. The operation shown in FIG. 7 is performed.

At time t5, the row addresses “n + 9” and “n + 11” are simultaneously selected as the read row RDR, added and read.
In addition, the shutter operation is performed at the row addresses “n + 17”, “n + 19”, “n + 21”, “n + 23”, “n”, “n + 2”, “n + 4”, and “n + 6”.
Row addresses “n + 17” and “n + 19” are shutters for the frame being read, and row addresses “n” and “n + 2” are shutters for the next frame.
Row addresses “n + 21”, “n + 23”, “n + 4”, and “n + 6” are blooming prevention shutters for the skipped rows.

FIG. 9 is a diagram showing the shutter and lead operations in this embodiment for convenience.
In FIG. 9, the vertical axis represents row numbers and the horizontal axis represents time. The unit of time is a horizontal readout period.

The row number is obtained by assigning numbers to the shutter row and the lead row in the order of access within one frame period.
The row numbers will be described by taking as an example the case of performing “two-pixel addition” and “½ thinning” operations.
In FIG. 8, it is assumed that reading is performed from the row address n.
At this time, for the read row, row addresses “n” and “n + 2” are row number 0, “n + 1”, “n + 3” are row number 1, “n + 8”, and “n + 10” are row number 3.
For the shutter row, except for the blooming prevention shutter, the row number is determined so as to have the same row address as the lead row.
That is, when accessing the row address “n”, “n + 2”, “n + 4”, “n + 6”, it is assumed that the row number 0 is being accessed.
Similarly, row addresses “n + 1”, “n + 3”, “n + 5”, “n + 7” are row number 1, and “n + 8”, “n + 10”, “n + 12”, “n + 14” are row number 2.
As described above, the numbers assigned to the shutter row and the lead row in the order of reading are defined as row numbers.

In the CMOS image sensor 100 of the present embodiment, the number of shutter rows and the number of read rows are constant in any row number.
For example, in the “two-pixel addition” and “1/2 thinning-out” operations, the number of shutter rows in each row number is always 4 and the number of read rows is always 2.

In the example of FIG. 9, the accumulation time of the frame FRM1 is Tint1, the accumulation time of the frame FRM2 is Tint2, and the accumulation time of the frame FRM3 is Tint3.
In the present embodiment, when the accumulation time is changed between frames, the horizontal readout period for shuttering the dummy pixels is determined from the maximum number of shutter rows in the frame.
Specifically, when there is a horizontal readout period in which the shutter operation of the frame being read out and the next frame is simultaneously performed within a certain frame, the shutter of the dummy pixels is set so that the number of shutter rows is always 2 frames. Perform the action.
In a certain frame, when there is no horizontal readout period in which the shutter operation of the frame being read and the next frame is simultaneously performed, the shutter operation of the dummy pixels is performed so that the number of shutter rows is always one frame.
For example, in the period T2 of the frame FRM1, the shutter operation of the frame FRM1 that is the read frame and the frame FRM2 that is the next frame is performed simultaneously.

On the other hand, only the shutter operation of the frame FRM1 is performed in the period T1, and only the shutter operation of the frame FRM2 is performed in the period T3.
Therefore, in the frame FRM1, the shutter operation is performed with the largest number of rows in the period T2, and the number of rows corresponds to the number of shutter rows for two frames.
Therefore, in the frame FRM1, the shutter operation of the dummy pixels is performed so that the shutter operation for two frames is always performed.
Specifically, the shutter operation is performed on the number of dummy pixels corresponding to the number of shutter rows for one frame in the period T1 and the period tT.

On the other hand, in the frame FRM2, the shutter operation of the frame FRM2 that is the readout frame and the frame FRM3 that is the next frame is not performed at the same time.
Only the shutter operation of the frame FRM2 is performed in the period T4, only the shutter operation of the frame FRM3 is performed in the period T6, and no shutter operation is performed in the period T5.
Therefore, in the frame FRM2, the shutter operation is performed only with the number of shutter rows corresponding to one frame at the maximum. Therefore, in the frame FRM2, the shutter operation of the dummy pixels is performed so that the shutter for one frame is always performed.
Specifically, in the period T5, the dummy pixel shutter operation is performed on the number of dummy pixels corresponding to the number of shutter rows for one frame.

In the example of FIG. 9, the number of shutter rows is constant in the frame. However, it is only necessary that the number of shutter rows be constant in the same frame during the reading period.
If the read operation is not performed, even if the power supply voltage fluctuates due to the change in the number of shutter rows, the signal is not read out, so that there is no effect.

  Whether the maximum number of shutter rows in a frame is one frame or two frames can be determined by the following equation.

When Ln ≦ Tdint Number of shutter rows = 1 frame When Ln> Tdint Number of shutter rows = 2 frames Here, Ln indicates the number of readout / shutter rows, and Tdint indicates the interval between the readout frame and the shutter of the next frame. Yes.

Tdint can be calculated from the period of one frame and the accumulation time of the readout frame and the next frame.
For example, in the frame FRM1 of FIG. 9, Tdint is calculated by the following equation.

Tdint = Tfrm + Tint1-Tint2
Here, Tfrm is a period of one frame, Tint1 is an accumulation time of the frame FRM1, and Tint2 is a reading period of the next frame.

By driving as described above, the number of shutter rows in the frame is made constant, and the occurrence of a shutter step is prevented.
Furthermore, according to the driving method of the present embodiment, dummy pixels need only be provided for the number of shutter rows for one frame.

As described above, according to the present embodiment, the following effects can be obtained.
That is, according to the present embodiment, by providing dummy pixels as many as the number of shutter rows of one frame, the number of shutter rows during each read operation of the same frame can be made constant and a shutter step can be prevented.
Since the number of necessary dummy pixels is smaller than in the prior art, the chip size can be reduced, the power consumption can be reduced, and the chip unit price can be reduced. In particular, when “addition” or “thinning” operations are performed, the number of shutters per frame increases, so the effect is great.

  The CMOS image sensor according to each embodiment is not particularly limited, but may be configured as a CMOS image sensor equipped with, for example, a column parallel type analog-digital converter (hereinafter abbreviated as ADC (Analog Digital Converter)). Is possible.

  The solid-state imaging device having the above-described effects can be applied as an imaging device for a digital camera or a video camera.

<2. Second Embodiment>
FIG. 10 is a diagram illustrating an example of a configuration of a camera system to which the solid-state imaging device according to the second embodiment of the present invention is applied.

As shown in FIG. 10, the camera system 200 includes an imaging device 210 to which the CMOS image sensor (solid-state imaging device) 100 according to the present embodiment can be applied.
Furthermore, the camera system 200 includes an optical system that guides incident light (images a subject image) to the pixel area of the imaging device 210, for example, a lens 220 that forms incident light (image light) on the imaging surface.
The camera system 200 includes a drive circuit (DRV) 230 that drives the imaging device 210 and a signal processing circuit (PRC) 240 that processes an output signal of the imaging device 210.

  The drive circuit 230 includes a timing generator (not shown) that generates various timing signals including a start pulse and a clock pulse that drive a circuit in the imaging device 210, and drives the imaging device 210 with a predetermined timing signal. .

The signal processing circuit 240 performs predetermined signal processing on the output signal of the imaging device 210.
The image signal processed by the signal processing circuit 240 is recorded on a recording medium such as a memory. The image information recorded on the recording medium is hard copied by a printer or the like. Further, the image signal processed by the signal processing circuit 240 is displayed as a moving image on a monitor including a liquid crystal display or the like.

  As described above, by mounting the above-described imaging element 100 as the imaging device 210 in an imaging apparatus such as a digital still camera, a highly accurate camera with low power consumption can be realized.

  DESCRIPTION OF SYMBOLS 100 ... Solid-state image sensor, 110 ... Pixel array part, 110A ... Pixel circuit, 120 ... Dummy pixel array part, 120A ... Dummy pixel circuit, 130 ... Row selection circuit, 140. ..Dummy selection circuit, 150... Row selection control circuit, 160... Readout circuit, 170 .. power supply, PD .. photoelectric conversion element, TRG-Tr... Transfer transistor, RST-Tr. -Reset transistor, AMP-Tr ... Amplification transistor, SEL-Tr ... Selection transistor, DTRG-Tr ... Dummy transfer transistor, DRST-Tr ... Dummy reset transistor, DAMP-Tr ... Dummy amplification Transistor, DSEL-Tr ... dummy selection transistor, 200 ... camera system, 210 ... imaging device 220 ... driving circuit, 230 ... lens, 240 ... signal processing circuit.

Claims (7)

A pixel unit in which a plurality of pixels that convert an optical signal into an electrical signal and store the electrical signal according to an exposure time are arranged in a matrix;
A dummy pixel portion in which a plurality of dummy pixels are arranged in a matrix;
In accordance with a shutter mode switching signal, the electronic shutter operation of the pixel unit and the dummy pixel unit and the operation of the pixel to control reading are performed, and the electronic shutter is performed by a rolling shutter method in which the electronic shutter is performed in units of rows. If, having the maximum of the shutter number in the frame being read, the image element driving unit that determines whether to perform either a read period the shutter to the dummy pixels, and
The pixel of the pixel portion and the dummy pixel of the dummy pixel portion are
A photoelectric conversion element that generates signal charges from incident light; and
A transfer transistor for transferring the signal charge to the floating diffusion;
A reset transistor for connecting the floating diffusion to a predetermined potential , and
The pixel driving unit includes:
If there is a period in which the shutter of the frame during the readout period and the shutter of the next frame are performed in parallel,
In the first period during which frame of the shutter is performed in a simultaneous and parallel manner, the transfer transistor and the reset transistor of the pixel of the shutter row of pixels and the next frame of the shutter row to be read frames simultaneously turned ON, and the Turn off the transfer transistor and the reset transistor of the dummy pixel.
In the second period in which the shutters for the frames outside the first period are not performed simultaneously in parallel, the transfer transistors and the reset transistors of the pixels in the shutter row of the readout target frame or the pixels in the shutter row of the next frame are set. A solid-state imaging device which is turned on at the same time and simultaneously turns on the transfer transistor and the reset transistor of the dummy pixel . The second period includes a third period preceding the first period and a fourth period subsequent to the first period across the first period,
The pixel driving unit includes:
In the third period, the transfer transistor and the reset transistor of the pixels in the shutter row of the readout target frame are simultaneously turned on, and the transfer transistor and the reset transistor of the dummy pixel are simultaneously turned on,
2. The transfer transistor and the reset transistor of the dummy pixel are simultaneously turned on and the transfer transistor and the reset transistor of the dummy pixel are simultaneously turned on in the fourth period . Solid-state image sensor. The pixel driving unit includes:
If there is no period in which the shutter of the frame during the readout period and the shutter of the next frame are performed in parallel ,
In the fifth period in which the shutter of the frame is performed, the transfer transistor and the reset transistor of the pixels in the shutter row of the read target frame are simultaneously turned on, and the transfer transistor and the reset transistor of the dummy pixel are turned off.
In a sixth period in which no frame shutter is performed, the transfer transistor and the reset transistor of the pixels in the shutter row of the read target frame are turned off, and the transfer transistor and the reset transistor of the dummy pixel are turned on simultaneously. The solid-state imaging device according to claim 1 or 2. The solid-state imaging device according to any one of claims 1 to 3 , wherein a charge accumulation time can be changed for each frame. 5. The solid-state imaging device according to claim 1 , further comprising a power source that supplies power to the pixel unit, the dummy pixel unit, and the pixel driving unit . The pixel driving unit includes:
When the electronic shutter is performed by the rolling shutter method in which the electronic shutter is performed in units of rows, it is determined whether the shutter of the frame being read out and the shutter of the next frame are performed simultaneously in parallel, and in which horizontal readout period the dummy Decide whether you want to shutter the pixels,
When the shutter of the frame being read out in the frame and the shutter of the next frame are performed simultaneously in parallel, the shutter operation of the dummy pixel unit is performed so that the number of shutter rows in the readout period in the frame is two frames. ,
When the shutter of the frame being read out and the next frame in the frame are not simultaneously performed in parallel, the shutter operation of the dummy pixel unit so that the number of shutter rows in the read period in the frame is one frame. solid-state imaging device as claimed in any one of 5 to perform. A solid-state image sensor;
An optical system for forming a subject image on the solid-state image sensor;
A signal processing circuit for processing an output image signal of the solid-state imaging device,
The solid-state imaging device is
A pixel unit in which a plurality of pixels that convert an optical signal into an electrical signal and store the electrical signal according to an exposure time are arranged in a matrix;
A dummy pixel portion in which a plurality of dummy pixels are arranged in a matrix;
In accordance with a shutter mode switching signal, the electronic shutter operation of the pixel unit and the dummy pixel unit and the operation of the pixel to control reading are performed, and the electronic shutter is performed by a rolling shutter method in which the electronic shutter is performed in units of rows. If, having the maximum of the shutter number in the frame being read, the image element driving unit that determines whether to perform either a read period the shutter to the dummy pixels, and
The pixel of the pixel portion and the dummy pixel of the dummy pixel portion are
A photoelectric conversion element that generates signal charges from incident light; and
A transfer transistor for transferring the signal charge to the floating diffusion;
A reset transistor for connecting the floating diffusion to a predetermined potential , and
The pixel driving unit includes:
If there is a period in which the shutter of the frame during the readout period and the shutter of the next frame are performed in parallel,
In the first period in which the shutters of the frames are simultaneously performed in parallel, the transfer transistors and the reset transistors of the pixels in the shutter row of the readout target frame and the pixels in the shutter row of the next frame are simultaneously turned on, and the dummy Turn off the transfer transistor and the reset transistor of the pixel.
In the second period in which the shutters for the frames outside the first period are not performed simultaneously in parallel, the transfer transistors and the reset transistors of the pixels in the shutter row of the readout target frame or the pixels in the shutter row of the next frame are set. A camera system which is turned on at the same time and simultaneously turns on the transfer transistor and the reset transistor of the dummy pixel .

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