JP2005184358A - Solid state imaging apparatus and method for reading pixel signal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the bad effect of the pixel which is not read when segmenting a pixel region. <P>SOLUTION: When reading of pixel signal and resetting of a pixel with a part of an effective pixel region, only resetting of pixel is performed with a column containing no pixel for which pixel signal is read within the effective pixel region. Thus, all pixels in the effective pixel region are reset at prescribed respective timing, causing no pixel where electric charge is continuously accumulated with no resetting. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device having a pixel sensor using a solid-state imaging pixel such as a CMOS image sensor, and a pixel signal reading method thereof.

JP 2001-86391 A JP 2003-189184 A

For example, in a solid-state image pickup device (camera device) using a solid-state image pickup device such as a CMOS image sensor, the solid-state image pickup devices are arranged in an array in the row direction and the column direction, and each pixel forms one screen. A pixel sensor unit is formed.
In the field of solid-state imaging devices, for example, a plurality of video signal standards such as both the NTSC system (Standers Definition: SD standard) and the high-definition HDTV system (High Definition TV: HD standard) that are widely used in Japan and North America. In recent years, it has become important to deal with.
In this case, for example, mounting separate image sensors for the SD standard and the HD standard in a solid-state imaging device is disadvantageous in terms of cost and configuration, and therefore, using one image sensor array, the SD standard is used. It is appropriate to use imaging and HD standard imaging properly.
For example, when it is desired to make both the SD standard and the HD standard compatible in one image sensor array as a CMOS image sensor, an image sensor array is created in advance with a pixel array of one standard, and when using the other standard, the image sensor array A method may be considered in which a region is cut out and read out.

FIG. 22 shows a region structure of the image sensor array (pixel array).
FIG. 22A shows a state where a 4: 3 pixel array is formed in the row direction: column direction in accordance with the SD standard as an effective area of the image sensor array (an effective pixel area used for pixel signal readout). Is shown. In other words, this is the case of an image sensor array compliant with the SD standard aspect ratio 4: 3.
A pixel as an OPB (optical black) region is formed around the effective region.
The OPB area is an area in which the level of the output pixel signal is always a prescribed black level by making it impossible to receive light with a light-shielding mask or by preventing charges from being accumulated even if light is received by a manufacturing process. is there.
On the other hand, as a matter of course, the pixels in the effective region accumulate charges according to incident light and output pixel signals according to the charges.
When trying to obtain an HD-standard captured image signal with an aspect ratio of 16: 9 using the SD-standard-compliant image sensor array in FIG. 22A, for example, as shown as region A in FIG. A predetermined number of lines are cut out in the effective area. That is, a pixel signal is read from each pixel in the region A that is 16: 9, and a captured image signal that forms one screen is obtained. Pixel signals are not read out for the pixels in region B.

FIG. 22C shows a state in which the effective area of the image sensor array is formed as a 16: 9 pixel array in the row direction and the column direction in accordance with the HD standard. In other words, this is the case of an image sensor array that complies with the 16: 9 aspect ratio of the HD standard.
When trying to obtain an SD standard captured image signal with an aspect ratio of 4: 3 using the HD standard compliant image sensor array in FIG. 22C, for example, as shown as region A in FIG. A predetermined number of rows are cut out in the effective area. That is, a pixel signal is read from each pixel in the area A that is 4: 3, and a captured image signal that forms one screen is obtained. Also in this case, pixel signals are not read out for the pixels in the region B.

  Although not for sharing the SD / HD standard, a technique for reading out a part of pixels in the effective area is described in, for example, the above-mentioned Patent Documents 1 and 2 as reduced reading or thinning reading. .

An example of the configuration of the CMOS image sensor is shown in FIG. As shown in the figure, one pixel includes, for example, a photodiode PD that accumulates charges according to incident light, a selection transistor TR1, a reset transistor TR2, and an amplification transistor TR3.
Normally, the pixel shutter operation is performed during the H blanking period. In the H blanking period, a row of pixels to be read is selected, a pixel signal is read from each pixel in the selected row, and transferred to a column processing unit, for example, a CDS (correlated double sampling) circuit unit. Next, a reset operation for each pixel is performed. That is, the photodiode PD and the floating diffusion FD are reset and initialized.
The initialized photodiode PD receives incident light, starts accumulating charges, and continues accumulating until a row is selected at the next reading.

  In this case, in the pixels arranged in the row direction, the signal TG, the signal RST, and the signal SEL shown in FIG. As will be described in detail later with reference to FIG. 2, a signal RST is first applied to each pixel in a selected row, and reset level reading (P-phase reading) is performed from these pixels. Signal level is read (D-phase read) by applying signal TG. The difference between the signal level and the reset level is a pixel signal detected by the CDS circuit unit. Thereafter, the signal TG and the signal RST are simultaneously applied, so that all pixels in the row are reset (pixel reset) as the initialization.

Since such a reading operation is performed, each pixel in the row selected for reading is subjected to pixel reset as well as reading.
Considering this point, consider the case of performing HD standard reading as shown in FIG. In the case of FIG. 22B, the above read operation is executed for each row in the region A, while the read operation is not executed for each row in the region B. In other words, there is a row that is not selected at all when the pixel signal is read out even though it is within the effective region. As described above, the pixel is reset when the pixel signal is read out when the row is selected. However, since the row is not selected for each pixel in the region B, the pixel reset is performed during the HD standard reading. There will be no opportunity to be done.

As described above, since the pixel reset is not performed in each pixel in the region B, the following problem occurs.
FIG. 23B shows a cross-sectional configuration of the pixel. As shown in the figure, for example, an N-type diffusion layer in a P-type silicon substrate is arranged to form a photodiode PD, a selection transistor TR1, and a reset transistor TR2. If pixel reset is not performed on the pixels in the region B, the adverse effects occur in the operations shown as (1) to (5) in the figure.
(1) Since the pixels in the row of the region B are effective regions, light always strikes the photodiode PD of the pixel.
(2) Then, since the pixel is not reset, the photodiode PD in the pixel always performs photoelectric conversion, and the charge overflows.
(3) The potential of the floating diffusion (FD) changes due to the influence of charge overflow.
(4) The amplification transistor TR3 operates due to the fluctuation of the FD potential.
(5) The potential of the vertical signal line VL that is a signal line of the pixel signal is generated by the operation of the amplification transistor TR3.

Since the pixels in the same column in all rows are connected to the vertical signal line VL, the potential fluctuation of the vertical signal line due to the pixels in the region B is a pixel from the pixel in the row that is being read at that time. This will affect the signal.
As described above, since the pixels in the region B are not reset, the pixel signal from the region A is adversely affected, the signal quality is deteriorated, and the image quality is deteriorated.

  Further, the fact that the pixel reset is not performed and the light is always applied and the electric charge is generated also causes deterioration of the photodiode PD and the transfer gates (TR1 to TR3) in the pixel.

  To deal with such a problem, for example, even when HD standard readout is performed as shown in FIG. 22B, all pixels in the effective region are read (and pixel reset) and output as data. A method of not outputting a portion unrelated to (that is, a pixel signal from a pixel in the region B) is conceivable. With this method, the pixels in the region B are also reset, so that the above problem can be solved. However, in this case, since all the lines are read out, there is a disadvantage that the frame rate cannot be increased, which makes it difficult to perform a high frame rate operation for high-definition video required by the HD standard.

  Note that the above problem does not occur when the pixels in the region A are read out from the HD standard effective region for SD standard readout as shown in FIG. That is, in the case of FIG. 22D, the region A covers all rows of effective pixels, and the pixels in the region B are also reset when the pixels in the region A are read.

  In the present invention, when a row that is not selected for reading occurs, such as when an image sensor configured with an SD standard pixel array as described above is used as an HD standard, the pixels in that row are appropriately reset. The purpose is to prevent the adverse effects caused by the fact that the reset is not performed.

  For this reason, the solid-state imaging device of the present invention is a pixel in which the solid-state imaging devices are arranged in an array in the row direction and the column direction, and each of the solid-state imaging devices obtains a pixel signal based on the charge accumulated according to incident light. A sensor means, a vertical scanning means for selecting a row of the pixel sensor means, and reading out the pixel signal from the solid-state imaging device in each column of the selected row; and the pixel signal read by the vertical scanning means Output means for performing processing and outputting a captured image signal. The vertical scanning unit is a pixel from which the pixel signal is read out in the effective pixel region when the pixel signal is read out and the pixel reset is executed on a part of the effective pixel region of the pixel sensor unit. Only a pixel reset is executed for a row that does not contain.

In this case, the vertical scanning means includes a read address decoder for selecting a row for executing reading of the pixel signal and pixel reset, and a reset address decoder for sequentially selecting a row for executing only pixel reset.
Alternatively, the vertical scanning unit includes a read address decoder that selects a row on which the pixel signal is read and a pixel reset is performed, and a batch reset circuit that collectively selects a row that does not include a pixel on which the pixel signal is read. .

The pixel reset timing for the row not including the pixel from which the pixel signal is read is as follows.
That is, the control communication period is performed in a frame period unit composed of a control communication period and a frame readout period.
Alternatively, it is performed during a frame reading period in which normal reading is performed.
The line reading period for performing the reading operation of one row of the pixel sensor means includes a column reading period for reading out a pixel signal from a pixel in a selected row by vertical transfer, and a pixel signal read in the column reading period. Are sequentially transferred horizontally and output as a picked-up image signal for one row, pixel reset for a row not including a pixel from which a pixel signal is read is performed during the horizontal transfer period. To do.

  In the pixel sensor means, the effective pixel area is arranged in a 4: 3 pixel array in the row direction and the column direction, and the vertical scanning means is used for a 16: 9 area cut out from the effective pixel area. When the readout of the pixel signal and the pixel reset are executed, only the pixel reset is executed for the rows not included in the 16: 9 region in the effective pixel region.

  A pixel signal reading method according to the present invention is a pixel sensor in which solid-state image sensors are arranged in an array in the row direction and the column direction, and each solid-state image sensor obtains a pixel signal based on charges accumulated according to incident light. Means for reading out the pixel signal and resetting the pixel signal for a part of the effective pixel area of the pixel sensor means in the effective pixel area. Only a pixel reset is executed for a row that does not exist.

  According to the present invention described above, it is possible to execute pixel reset without reading pixel signals for a required row of the pixel sensor means. For example, in order to obtain an HD-standard captured image signal from pixel sensor means whose effective pixel area is an SD-standard pixel array, when reading out a pixel signal and resetting a pixel in a part of the effective pixel area In the effective pixel region, only pixel reset is performed on a row that does not include a pixel from which a pixel signal is read, so that a pixel that is not reset in the effective pixel region can be prevented from being generated.

According to the present invention, when pixel signal readout and pixel reset are executed for a part of the effective pixel region, the row in the effective pixel region that does not include the pixel from which the pixel signal is read out. Since only pixel reset is performed, pixel reset is performed at a predetermined timing for all the pixels in the effective pixel region. That is, since no pixel is generated in which charges are continuously accumulated without being reset, an adverse effect on the pixel signal is eliminated, and a high-quality captured image signal can be obtained. Further, since the deterioration of the pixel due to not being reset is prevented, the reliability is also improved.
Further, when a part of the pixel sensor unit is cut out, for example, when an HD standard captured image signal is obtained from a pixel sensor unit having an SD standard pixel array, the effective pixel region is reset for the purpose of resetting all pixels. Since it is not necessary to execute the read operation for all the rows, it is easy to increase the frame rate. In particular, it is also suitable for performing a high frame rate operation for HD standard high-definition video.

Hereinafter, as an embodiment of the present invention, a solid-state imaging device using a CMOS sensor array will be described in the following order.

1. 1. Configuration of main part of solid-state imaging device 2. Configuration of vertical scanning circuit 3. Pixel reset during communication period 4. Pixel reset during frame readout period 5. Pixel reset in horizontal transfer period Effects and modifications of the embodiment

1. Configuration of main parts of solid-state imaging device

FIG. 1 is a block diagram of a main part of the solid-state imaging device of the present embodiment.
Light from a subject is incident on the pixel array 1 in FIG. 1 by a lens system (not shown). The pixel array 1 is, for example, a CMOS sensor array, and is formed by arranging a large number of imaging pixels GS as solid-state imaging elements (CMOS sensors) in the row direction and the column direction. Here, the number of rows is n and the number of columns is m.
The pixel array 1 has an OPB area and an effective area as shown in FIG. As described above, the OPB region is a region where pixels for obtaining a black level signal are arranged, and is configured such that, for example, no light is incident thereon. On the other hand, the effective area is an area where pixels that output pixel signals corresponding to incident light are arranged. In the case of this example, the effective area has pixels arranged in a ratio of 4: 3 in the row direction: column direction, that is, the configuration conforms to the screen of the SD standard.

The vertical scanning circuit 3 of FIG. 1 selects a row in the pixel array 1 based on the address and control signal supplied from the timing generator 2 and performs scanning. As will be described in detail later, in this example, scanning for sequentially selecting each row is performed so that pixels in the effective area are read out in a column-parallel manner, and for example, the pixel arrays 1 to 16 in the 4: 3 effective area are selected. : When the HD imaged image signal is obtained by cutting out the area 9, pixel reset is executed at a predetermined timing for a row that is not read out.
For these operations, the vertical scanning circuit 3 drives the vertical scanning lines L1 to Ln. Signals (pulses) to be applied to the vertical scanning lines L1 to Ln are generated as a logic circuit level voltage in the vertical scanning circuit 3, and this is shifted to a scanning line driving level voltage by the voltage level shifter 4 to be applied to each vertical scanning line L1 to Ln. Will be given to.
When outputting a captured image signal of the SD standard, the first to nth rows of the effective pixels of the pixel array 1 are sequentially selected by the vertical scanning lines L1 to Ln (hereinafter also referred to as “SD standard readout”). .
In the case of outputting a captured image signal of the HD standard, a row in a range to be cut out from the first row to the n-th row of the effective pixels of the pixel array 1 is sequentially selected by the corresponding vertical scanning line (hereinafter referred to as the vertical scanning line). , Also referred to as “HD standard readout”).

The vertical scanning lines L1 to Ln shown in FIG. 1 each have three signal lines, and supply a signal SEL, a signal RST, and a signal TG to the pixel GS. FIG. 2 shows a relationship between the structure of the pixel GS and each signal.
For example, as shown in FIG. 2, the pixel GS includes a photodiode PD, a selection transistor TR1, a reset transistor TR2, and an amplification transistor TR3.
A signal line of the signal TG is connected to the gate of the selection transistor TR1. The signal line of the signal RST is connected to the gate of the reset transistor TR2. The signal SEL is connected to the source (or drain) of the reset transistor TR2 and the source (or drain) of the amplification transistor TR3.
By applying the signal SEL, the signal RST, and the signal TG to the pixel GS at predetermined timings, pixel signal reading and pixel reset are performed.

Incident light is photoelectrically converted by the photodiode, and charges are accumulated in the photodiode. When the selection transistor is turned on by the signal TG, the charge of the photodiode is read out. The amplification transistor TR3 amplifies the read level (FD) and transfers the signal to the vertical signal line VL. Further, the reset transistor TR2 is turned on by the signal RST, whereby the FD level is initialized (reset). The signal SEL is normally set to 0V, and the voltage of the signal SEL becomes the initial voltage.
The vertical signal line VL is connected to a constant current source, that is, the amplification transistor TR3 gives a current change of the vertical signal line VL in response to the FD level changing from the initial voltage level to the voltage level due to the read charge. become. This current change becomes the read pixel signal.

In this example, column-parallel pixel readout is performed. Therefore, the signal charges from the pixels G arranged in the row direction in the pixel array 1 are simultaneously read out and given to the vertical signal lines VL (VL1, VL2,...).
More specifically, the vertical scanning circuit 3 first applies a reset level signal (a signal when the FD level is initialized) from each pixel GS in the selected row to each vertical signal line VL (so-called P). Then, an operation (so-called D-phase reading) of applying a pixel signal corresponding to the electric charge accumulated in the photodiode PD to the vertical signal line VL is executed. The vertical scanning circuit 3 sequentially executes such reading operations.

Reading of pixel signals from the selected pixels GS in a certain row is performed in a horizontal blanking period within one horizontal period. That is, in the horizontal blanking period, pixel signals from the pixels GS in the row selected by the vertical signal driving circuit 2 are output in parallel to the vertical signal lines VL1, VL2,. .
In the horizontal blanking period, pixel reset is performed after P-phase reading and D-phase reading are performed as described above. Pixel reset is executed by simultaneously raising the signal RST and the signal TG.

Each pixel signal transferred from the pixel array 1 in FIG. 1 to each vertical signal line VL is processed by the column CDS unit 5.
In the column CDS section 5, for each vertical signal line VL (each column), a CDS (Correlated Double Sampling) circuit composed of, for example, a capacitive element and a switch element is formed, and sampling of the pixel signal is performed. Do. Specifically, the difference between the P-phase readout level and the D-phase readout level is sampled as a pixel signal.
As described above, the pixel signals of each column read out in parallel from the row selected in the horizontal blanking period within the horizontal cycle and sampled by the column CDS unit 5 are converted into the horizontal scanning circuit during the horizontal transfer period within the horizontal cycle. 6 are sequentially selected, transferred to the horizontal signal line HL, and supplied to the output circuit 7.
The output circuit 7 performs AGC processing, clamping processing, and the like, and outputs a captured image signal of one horizontal period as a serial signal. By performing the above operation in each horizontal cycle, one frame of the captured image signal is output in one frame period.
The “frame” here corresponds to a field in units of 1/60 second of the NTSC system, for example.

  The operation timing in the vertical scanning circuit 3, horizontal scanning circuit 6, column CDS unit 5, and output circuit 7 is controlled by the timing generator 2. The timing generator 2 controls the operation timing of each unit based on the vertical synchronization signal and the horizontal synchronization signal.

  The captured image signal output from the output circuit 7 is converted into a digital signal by an A / D converter (not shown), and further subjected to digital gain processing, white balance processing, and the like. Further, display signal processing is performed and image display is performed on the display unit, encoding processing such as formatting processing and compression processing is performed, and recording is performed on a recording medium, or transmission is output from the transmission unit.

The operation cycle for the above read operation is shown in FIG.
The frame period is defined by the V start pulse XVS, and one frame period corresponds to 1/60 seconds, for example.
In this frame cycle, operations as a communication period and a frame reading period are performed.
The communication period is a control communication period. For example, communication between the timing generator 2 and a control unit (control DSP or microcomputer) (not shown) is performed.
The frame reading period is a period during which one frame of the captured image signal is read. In this frame readout period, the captured image signal is read out one row (one horizontal line) for each horizontal period, and the captured image signal of one frame is output by reading out the captured image signals of n rows. Will be.
In the line readout period which is one horizontal period, operations as a column readout period and a horizontal transfer period are performed. The column readout period is a period in which pixel signals from each pixel GS in a selected row are read out and vertically transferred to the column CDS unit 5 in a column parallel manner. This period corresponds to a horizontal blanking period.
The horizontal transfer period is a period in which the pixel signals of each column held in the column CDS section 5 are sequentially selected by the horizontal scanning circuit 6, transferred to the output circuit 7 by the horizontal signal line HL, and output processed.

As described above, the effective pixels of the pixel array 1 have the 4: 3 pixel array shown in FIG. 4A. An example in which HD standard readout is performed from the pixel array 1 is shown in FIG. c) As shown in (d).
FIG. 4B shows a case where the 16: 9 range in the center of the effective pixels in the first row to the n-th row is cut out and an HD standard captured image signal is output.
FIG. 4C shows a case where a 16: 9 range is cut out below the effective pixels and an HD-standard captured image signal is output.
FIG. 4D shows a case where a 16: 9 range is cut out above the effective pixels and an HD standard captured image signal is output.
In any case, the vertical scanning circuit 3 sequentially selects each row in the region A to be cut out, and scans each pixel so that pixel signal reading and pixel reset are performed.
In any case, the row included in the region B is a row including only pixels that are not read out. In this example, pixel reset is performed at a predetermined timing for each row in the region B.

In the following description, in the case of HD standard reading, an example in which the central area A as shown in FIG. In this case, in the first row to the n-th row of the effective region, the q-th row to the r-th row are the regions A to be read as shown, and the first row to the p-th row and the s-th row to the n-th row are shown. Let the row be region B that is not to be read.

2. Configuration of vertical scanning circuit

A configuration example of the vertical scanning circuit 3 that performs pixel reset for each row in the region B in the case of SD standard readout, HD standard readout, and HD standard readout will be described.
As the vertical scanning circuit 3, a configuration in which pixel reset in the region B in the case of HD standard readout is performed in order of pixel reset sequentially for each row and a configuration in which all rows in the region B are collectively reset are considered. Each will be described with reference to FIGS. In addition, a variation of the configuration as the vertical scanning circuit 3 including them will be described with reference to FIG.

The vertical scanning circuit 3 causes the P-phase reading to be executed by raising the signal RST of the selected row, and causes the D-phase reading to be executed by raising the signal TG. Further, the pixel reset is executed by simultaneously raising the signal RST and the signal TG.
Therefore, hereinafter, a configuration for outputting the signal TG and the signal RST will be described as the configuration of the vertical scanning circuit 3 in particular.

First, FIG. 5 shows a configuration example of the vertical scanning circuit 3 that can select a row for pixel reset for each row.
In this case, the vertical scanning circuit 3 includes components as a reset address decoder 3a and a read address decoder 3b.

The read address decoder 3b is a decoder that selects a row from which pixel signals are read. A signal TG is selected so that a certain row is selected for reading by the read address decoder 3b, and reset reading (P-phase reading), pixel reading (D-phase reading), and pixel reset are performed for each pixel GS in the row. , A signal RST is generated.
The address of the row to be scanned (read address RD-Ad) is supplied from the timing generator 2 to the read address decoder 3b. The read address RD-Ad is input to the read row selection decoder 31. The read row selection decoder 31 has output terminals RD1 to RDn corresponding to the respective rows (respective vertical scanning lines L1 to Ln) of the pixel array 1, and the row designated by the read address RD-Ad, that is, the output terminals RD1 to RD1. An H level pulse as a read row selection signal is generated from a terminal selected from RDn.

Further, in the figure, only the output terminal RDn is shown, but AND gates 32 and 34 and OR gates 33 and 35 are provided corresponding to the output terminals RD1 to RDn of the read row selection decoder 31, respectively.
Explaining in correspondence with the output terminal RDn shown in the figure, a read row selection signal from the output terminal RDn is input to the AND gate 32. Further, the TG control signals TRTG and SHTG from the timing generator 2 are input to the AND gate 32 via the OR gate 38.
As shown in FIG. 6, the TG control signal TRTG is a pulse that defines the timing at which the signal TG rises for pixel signal reading (D-phase reading) within the horizontal blanking period in each horizontal period. The TG control signal SHTG is a pulse that defines the timing at which the signal TG is raised for pixel reset within the horizontal blanking period in each horizontal period.
The output of the AND gate 32 is supplied to the voltage level shifter 4 via the OR gate 33 and is voltage-shifted to become a signal TG of the nth row (vertical scanning line Ln).
Therefore, in the horizontal period in which the n-th row is selected as the read address RD-Ad and the output terminal RDn of the read row selection decoder 31 is at the H level, as shown in FIG. The pulse of the signal TG for pixel readout (D-phase readout) and the pulse of the signal TG at the time of pixel reset are given to each pixel GS in the nth row.

A read row selection signal from the output terminal RDn is input to the AND gate 34. The AND gate 34 has an RST control signal TRRST from the timing generator 2,
SHRST is input via the OR gate 39.
The RST control signal TRRST is a pulse that defines the timing at which the signal RST rises for reset reading (P-phase reading) within the horizontal blanking period of each horizontal cycle. The RST control signal SHRST is a pulse that defines the timing at which the signal RST rises for pixel reset within the horizontal blanking period in each horizontal period.
The output of the AND gate 34 is supplied to the voltage level shifter 4 via the OR gate 35 and is voltage-shifted to become a signal RST of the nth row (vertical scanning line Ln).
Therefore, in the horizontal period in which the nth row is selected as the read address RD-Ad and the output terminal RDn of the read row selection decoder 31 is at the H level, based on the H output of the AND gate 34, as shown in FIG. The pulse of the signal RST for reset reading (P-phase reading) and the pulse of the signal RST at the time of pixel reset are given to each pixel GS in the nth row.

  That is, when the n-th row is selected by the read address RD-Ad, the signal RST and the signal RST, as shown in FIG. 6 as “row selected by RD-Ad” by the vertical scanning line Ln for the n-th row. TG is given, and pixel signal readout and pixel reset are executed in each pixel GS in the n-th row.

On the other hand, the reset address decoder 3a is a decoder that selects a row in which only pixel reset is performed. Note that pixel reset is normally performed immediately after readout in a row where readout has been performed, but in this example, a row in which only reset is performed without readout is generated by the reset address decoder 3a.
The reset address decoder 3a is supplied with the address of the row to be reset (reset address RST-Ad) from the timing generator 2. The reset address RST-Ad is input to the reset row selection decoder 21. The reset row selection decoder 21 has output terminals RS1 to RSn corresponding to the respective rows (respective vertical scanning lines L1 to Ln) of the pixel array 1, and the row designated by the reset address RST-Ad, that is, the output terminals RS1 to RS1. An H level pulse is generated as a reset row selection signal from a terminal selected from RSn.

Also, in the figure, only the output terminals RSn are shown, but AND gates 22 and 23 are provided corresponding to the output terminals RS1 to RSn of the reset row selection decoder 21, respectively.
To explain in correspondence with the output terminal RSn shown in the figure, the AND row 22 receives a reset row selection signal from the output terminal RSn. The AND gate 22 receives a TG control signal SHTG that defines the pixel reset timing from the timing generator 2.
The output of the AND gate 22 is supplied to the OR gate 33.

The AND gate 23 receives a reset row selection signal from the output terminal RDn. The AND gate 23 receives an RST control signal SHRST that defines the pixel reset timing from the timing generator 2.
The output of the AND gate 23 is supplied to the OR gate 35.

Therefore, now, the nth row is selected by the reset address RST-Ad and the output terminal RSn is at the H level, while the nth row is not selected by the read address RD-Ad (the output terminal RDn is L), each pixel in the n-th row is not supplied with the pulse of the signal RST for reset reading and the pulse of the signal TG for pixel reading in FIG. A pulse of RST and signal TG will be given.
That is, when the nth row is selected by the reset address RST-Ad, the signal RST and the signal RST, as shown in FIG. 6 as “row selected by RST-Ad” by the vertical scanning line Ln with respect to the nth row. TG is given, and pixel reset without readout is executed in each pixel GS in the nth row.

As described above, depending on the vertical scanning circuit 3, a row where pixel signals are read and reset is selected by the read address decoder 3b, and a row where only pixel reset is performed is selected by the reset address decoder 3a.
Therefore, for example, when performing HD standard reading as shown in FIGS. 4B to 4D, the row address is sequentially given as the read address RD-Ad corresponding to each row of the region A, so that the pixels in the region A The signal readout is executed, and the row address is sequentially given as the reset address RST-Ad corresponding to each row in the region B, whereby the pixels GS in each row in the region B are reset.

By the way, as will be described later, the pixel reset timing of the pixels GS in each row of the region B is not limited to the column readout period as long as it is in the 1H period, and may be performed, for example, in the horizontal transfer period.
However, in the configuration of FIG. 5, the RST control signal SHRST and the TG control signal SHTG are commonly supplied to the reset address decoder 3a and the read address decoder 3b. In this case, the pixels GS in each row of the region B as shown in FIG. Will be reset at the same timing (within the column readout period) as the pixels in region A.
Here, if the RST control signal SHRST1 and TG control signal SHTG1 for the read address decoder 3 and the RST control signal SHRST2 and TG control signal SHTG2 for the reset address decoder 3a are supplied from the timing generator 2 independently, The reset timing of the pixel GS in the region B can be arbitrarily set. For example, FIG. 7 shows the RST control signal SHRST1, the TG control signal SHTG1, the RST control signal SHRST2, and the TG control signal SHTG2. For example, as shown in FIG. 7, the RST control signal SHRST2 and the TG control signal SHTG2 are given to the reset address decoder 3a. In this case, the pixel GS in the region B is reset during the horizontal transfer period. That is, the reset timing of the pixel GS in the region B can be arbitrarily set by the pulse timing of the RST control signal SHRST2 and the TG control signal SHTG2.

Next, FIG. 8 shows a configuration example of the vertical scanning circuit 3 in which all the rows in the region B are collectively reset.
In this case, the vertical scanning circuit 3 includes components as a read address decoder 3b and a collective reset circuit 3c.

The read address decoder 3b is a decoder for selecting a row from which a pixel signal is read in the same manner as in the case of FIG. 5 described above. A certain row is selected for reading by the read address decoder 3b, and each pixel in the row is selected. Signals TG and RST are generated so that GS reset readout (P-phase readout), pixel readout (D-phase readout), and pixel reset are performed.
The address (read address RD-Ad) of the row to be scanned is supplied from the timing generator 2 to the read address decoder 3b, and the output terminals RD1 to RDn of the read row selection decoder 31 correspond to the read address RD-Ad. An H level pulse as a read row selection signal is generated from a certain terminal.
In FIG. 8, among the output terminals RD1 to RDn, the output terminals RD1, RD2, RDn-1, and RDn correspond to the rows of the region B of the pixel array 1, and the output terminals RDx and RDX + 1 correspond to the region A. It is shown as corresponding to the line.

Corresponding to the output terminals RD1 to RDn of the read row selection decoder 31, AND gates 32 and 34 are provided, respectively.
To explain in correspondence with the output terminal RDn, the read row selection signal from the output terminal RDn is input to the AND gate 32. Further, the TG control signals TRTG and SHTG from the timing generator 2 are input to the AND gate 32 via the OR gate 38.
The output of the AND gate 32 is supplied to the voltage level shifter 4 via the OR gate 41 of the collective reset circuit 3c and is voltage-shifted to become the signal TG of the nth row (vertical scanning line Ln).
A read row selection signal from the output terminal RDn is input to the AND gate 34. The AND gate 34 has an RST control signal TRRST from the timing generator 2,
SHRST is input via the OR gate 39.
The output of the AND gate 34 is supplied to the voltage level shifter 4 via the OR gate 42 of the collective reset circuit 3c and is voltage-shifted to become a signal RST of the nth row (vertical scanning line Ln).
Therefore, in the horizontal period in which the n-th row is selected as the read address RD-Ad and the output terminal RDn of the read row selection decoder 31 is at the H level, as shown in FIG. A pulse of the signal TG for pixel readout (D-phase readout) and a pulse of the signal TG at the time of pixel reset are given to each pixel GS in the n-th row, and based on the H output of the AND gate 34, FIG. The pulse of the signal RST for reset readout (P-phase readout) shown in FIG. 9 and the pulse of the signal RST at the time of pixel reset are given to each pixel GS in the nth row.
That is, as in the configuration example of FIG. 5, when the nth row is selected by the read address RD-Ad, “RD-Ad is selected by the vertical scanning line Ln for the nth row in FIG. As shown in FIG. 5, a signal RST and a signal TG are given, and pixel signal readout and pixel reset are executed in each pixel GS in the n-th row.

On the other hand, the batch reset circuit 3c is configured such that OR gates 41 and 42 are provided in the vertical scanning line path for the row in the region B, and OR gates 43 and 44 are provided in the vertical scanning line route for the row in the region A. .
All the OR gates 41 and 43 receive the outputs of the AND gates 32 of the read address decoder 3b. That is, it is arranged on the path of the signal TG.
All the OR gates 42 and 44 receive the outputs of the AND gates 34 of the read address decoder 3b. That is, it is arranged on the path of the signal RST.

The all reset control signal ALRST is input from the timing generator 2 to all the OR gates 41, 42, 43, 44.
The all reset control signal ALRST is a control signal for resetting all the pixels in the effective area of the pixel array 1 as a so-called global shutter. That is, when the all reset control signal ALRST is set to the H level, the signals TG and RST rise at the same time in the vertical scanning lines L1 to Ln for all rows, and the shutter operation of all the pixels is performed.

In this example, in addition to such a configuration, the HD reset control signal HDRST is input from the timing generator 2 to the OR gates 41 and 42 corresponding to the row in the region B.
The HD reset control signal HDRST is a control signal for resetting all the pixels in the region B where reading is not performed when so-called HD standard reading is performed. That is, when the HD reset control signal HDRST is set to the H level, the signals TG and RST rise simultaneously in the vertical scanning lines L1 to Ln for all the rows in the region B, and the pixel reset of all the pixels in the region B is performed. Done.
For example, when the HD reset control signal HDRST is given as shown in FIG. 9, the signal RST and the signal TG shown in each row of the region B are given, as shown as “all the rows included in the region B”. Pixels GS are collectively reset.

As described above, depending on the vertical scanning circuit 3, the row where the pixel signal is read and reset is selected by the read address decoder 3b, and all pixels in the region B can be simultaneously reset by the batch reset circuit 3c. it can.
Therefore, for example, when performing HD standard reading as shown in FIGS. 4B to 4D, the row address is sequentially given as the read address RD-Ad corresponding to each row of the region A, so that the pixels in the region A When the signal reading is executed and the HD reset control signal HDRST is given at a certain timing, all the pixels GS in the region B are reset.
In this case, the batch reset timing of the region B can be arbitrarily set by setting the timing of the HD reset control signal HDRST. Although FIG. 9 shows an example in which collective reset is performed during the column readout period, the present invention is not limited to this, and collective reset is possible at any timing.
Although FIG. 8 shows the case where the global shutter function is provided, the signal line of the all reset control signal ALRST and the OR gates 43 and 44 are not necessary when this function is not provided.

Up to this point, examples of the configuration of the vertical scanning circuit 3 have been shown in FIGS. 5 and 8, respectively. As the configuration of the vertical scanning circuit 3 based on the examples of FIGS. 5 and 8, FIGS. c) can be assumed.
FIG. 10A shows a configuration including a reset address decoder 3a and a read address decoder 3b. In other words, the configuration shown in FIG. 5 is adopted. In this configuration, pixel reset (sequential reset) is executed for each row in the region B one row at a time.
FIG. 10B shows a configuration including a read address decoder 3b and a batch reset circuit 3c. In other words, the configuration shown in FIG. 8 is adopted. In this configuration, pixel reset is executed for all rows in the region B all at once.
FIG. 10C shows a configuration including a reset address decoder 3a, a read address decoder 3b, and a collective reset circuit 3c, that is, a configuration combining FIGS. Specifically, the components of the collective reset circuit 3c in FIG. 8 may be added to the configuration in FIG. 5 as they are (the outputs of the OR gates 33 and 35 in FIG. 5 are connected to the OR gate 41 (43) in FIG. 8). 42 (44)).
In this configuration, it is possible to select an operation for executing pixel reset for each row in the region B and an operation for performing batch reset.
For example, how to perform pixel reset for the region B needs to be set based on various factors such as an operation performance, a processing rate, and a reading operation in a model bell as a solid-state imaging device. For example, sequential resetting is good depending on the model, but batch resetting is good depending on the model. Also, depending on one model, there may be a case where it is desired to sequentially switch between reset / batch reset depending on the state of the operation mode or the like. Therefore, if the vertical scanning circuit 3 is designed as shown in FIG. 10C so that the reset mode can be selected by sequential resetting / batch resetting, various situations can be dealt with.

Incidentally, the number of read address decoders 3b and reset address decoders 3a should be changed according to the number of rows to be selected and operation settings. For example, if a plurality of reset address decoders 3a are provided, it is possible to select a reset row by a plurality of rows.
Of course, the configurations of the reset address decoder 3a, the read address decoder 3b, and the collective reset circuit 3c are not limited to the examples shown in FIGS. For example, there are various logic gate configurations.

3. Pixel reset during communication period

Hereinafter, various examples of the pixel B reset timing in the region B when performing HD standard reading will be described.
As described with reference to FIG. 3, a control communication period is provided within the frame period. Here, an example in which the pixel reset of the region B is performed within this communication period will be described.
FIG. 11 schematically shows pixel readout and reset operations for each row, with the vertical axis representing each row of the pixel array 1 and the horizontal axis representing time (frame period).
On the vertical axis, corresponding to FIG. 4B, the first to p-th rows, the s-th to n-th rows are the rows of the region B, and the q-th to r-th rows are the rows of the region A. It is going to be.

FIG. 11 shows a case where the vertical scanning circuit 3 is configured as shown in FIG. 10A or FIG.
During the frame reading period, reading of the area A cut out as HD standard reading is performed. In other words, in the frame readout period, in each horizontal period (one scale on the horizontal axis is one horizontal period), as indicated by the □ as a readout row, the rows from q-th row to r-th row are sequentially selected one by one. (P-phase readout / D-phase readout) and pixel reset are performed.
On the other hand, each row of the region B is sequentially selected from the first row to the p-th row and from the s-th row to the n-th row within the communication period, as indicated by the hatched squares in the figure as the reset row. The pixel is reset.
In this example, the first row to the p-th row and the s-th row to the n-th row are selected one by one (selected by the reset address RST-Ad for the reset address decoder 3a). May be set arbitrarily. For example, it may be selected and reset sequentially from the nth row side.

In this way, an example of sequentially resetting all the rows in the region B within the communication period can be considered. In this case, it is important to note the length of the communication period. If there is a sufficient margin in the communication period, there is no problem even if each row is selected in this way. However, if there is no margin in the communication period, it is possible that selection of all rows cannot be completed within the communication period. This is determined by the communication period, the number of lines, and the cycle time per line.
If there is a problem with the sequential reset within the communication period, the operation as a batch reset may be performed.

FIG. 12 shows a case where the vertical scanning circuit 3 is configured as shown in FIG. 10B or 10C, and the region B is collectively reset.
In the frame readout period, similarly to FIG. 11, in the horizontal periods, the q-th to r-th rows are sequentially selected one by one, and pixel readout (P-phase readout / D-phase readout) and pixel reset are performed. .
In each example of FIGS. 13 to 20 described later, the readout scanning timing from the q-th row to the r-th row of the region A is the same.

In the case of FIG. 12, in each row of the region B, pixel reset is collectively performed in all of the first to p-th rows and the s-th to n-th rows at the start of the communication period. That is, the HD reset control signal HDRST as shown in FIG. 9 is generated at the start of the communication period, and as a result, pulses as the signals TG and RST are output to each row in the region B by the collective reset circuit 3c. , All rows in region B are reset.
In this example, the batch reset is performed at the start of the communication period. However, the reset is not limited to the start time, but may be performed at any time within the communication period. That is, the pulse timing of the HD reset control signal HDRST is arbitrary.

4). Pixel reset during frame readout period

Next, an example in which the pixel reset of the region B is performed during the frame readout period will be described. That is, in the HD standard reading, the pixel reset of the region B is performed simultaneously with the scanning of each row of the region A to be read.

FIGS. 13 to 16 each show a case where the vertical scanning circuit 3 is configured as shown in FIG. 10A or 10C and the region B is sequentially reset.
In the example of FIG. 13, when the reading of the area A is sequentially performed from the q-th row to the r-th row for each horizontal period in the frame reading period, the first to p-th and s-th rows of the area B The pixel reset is performed by sequentially selecting the nth row one by one.
That is, the first row is reset in the horizontal period in which the reading of the qth row and the pixel reset is performed, the second row is reset in the horizontal period in which the reading and resetting of the (q + 1) th row is performed, and so on. In addition, pixel reset of each row in the region B is sequentially performed from the beginning of the frame period.

FIG. 14 is an example in which pixels in the region B are sequentially reset in the same manner in the frame readout period. This is because the first to p-th rows in the region B in each horizontal period on the end side of the frame readout period. This is an example in which pixel reset is performed by sequentially selecting s-th to n-th rows one by one.
FIG. 15 is also an example in which the pixels in the region B are sequentially reset in the frame readout period. In this example, the pixel resets in the first to p-th rows in the region B are sequentially performed at the beginning of the frame readout period. In addition, in this example, pixel resets of the s-th to n-th rows are sequentially performed in a predetermined period at the end of the frame reading period.
FIG. 16 also shows an example in which the pixels in the region B are sequentially reset in the frame readout period. This is because the first to p-th and s-th rows of the region B in the predetermined period at the center of the frame readout period. This is an example in which the pixel reset of the row to the n-th row is sequentially performed.
For example, as in the above example, each row of the region B can be sequentially reset in each horizontal period of the frame reading period. Of course, the order in which the rows in the region B are reset can be arbitrarily set according to the generation order of the reset address RST-Ad.

FIGS. 17 to 19 each show a case where the vertical scanning circuit 3 has the configuration shown in FIG. 10B or 10C and the region B is collectively reset.
In the example of FIG. 17, in the frame reading period in which the reading of the region A is sequentially performed row by row from the q-th row to the r-th row every horizontal period, for example, in the same horizontal period in which the q-th row reading is performed. In this example, the first row to p-th row and the s-th row to n-th row of the region B are collectively reset.
In FIG. 18, in the frame readout period, for example, the first row to the p-th row and the s-th row to the n-th row of the region B are collectively reset in the same horizontal period as the reading of the r-th row. This is an example.
Further, in FIG. 19, in the frame readout period, the first to p-th rows and the s-th to n-th rows of the region B are collectively in the same horizontal period in which a certain intermediate row of the region A is read. In this example, the pixel is reset.
By setting the pulse timing of the HD reset control signal HDRST, the collective pixel reset of the region B can be executed at an arbitrary timing within the frame readout period as in these examples.

5). Pixel reset during horizontal transfer period

Next, an example in which the pixel reset of the region B is performed at the timing of the horizontal transfer period within the horizontal period will be described.
For example, when the pixel reset of the region B is performed in the frame readout period as shown in FIGS. 13 to 19, for example, according to the RST control signal SHRST and the TG control signal SHTG in FIG. B is sequentially reset, and according to the HD reset control signal HDRST of FIG. 9, the region B is collectively reset during the column reading period.
On the other hand, for example, according to the RST control signal SHRST2 and the TG control signal SHTG2 in FIG. 7, the region B is sequentially reset during the horizontal transfer period of each horizontal period. If the reset control signal HDRST is activated during the horizontal transfer period, the region B is collectively reset during the horizontal transfer period.

FIG. 20A shows an example in which reset is sequentially performed in the horizontal transfer period within one horizontal cycle.
For example, in the first horizontal period in the frame readout period, pixel signal readout and pixel reset are performed in the column readout period, and in the subsequent horizontal transfer period, each pixel signal in the qth row is transmitted to the horizontal signal line HL. Is transferred horizontally. During the horizontal transfer period, the pixel in the first row of region B is reset.
In the next horizontal period, pixel signal readout and pixel reset are performed for the pixels in the q + 1th row in the column readout period, and each pixel signal in the q + 1th row is horizontally transferred through the horizontal signal line HL in the subsequent horizontal transfer period. The During the horizontal transfer period, the pixel in the second row of region B is reset.
For example, in this way, each row of the region B is sequentially reset for each horizontal transfer period in each horizontal period.

FIG. 20B shows an example in which batch reset is performed during a horizontal transfer period in a certain horizontal period.
For example, in the first horizontal period in the frame readout period, pixel signal readout and pixel reset are performed in the column readout period, and in the subsequent horizontal transfer period, each pixel signal in the qth row is transmitted to the horizontal signal line HL. In this horizontal transfer period, all pixels in the first row to the p-th row and the s-th row to the n-th row of the region B are reset.

For example, as described above, after the column reading period (horizontal blanking period) ends, the data held in the column CDS unit 5 is transferred to the output circuit 7 and output. It is also possible to perform a pixel reset of a row.

6). Effects and modifications of the embodiment

According to the above embodiment, when the pixel signal reading and the pixel reset are executed for the area A which is a part of the effective area for the HD standard reading, the pixel signal is read in the effective area. Since only the pixel reset is performed on the row that does not include the pixel (the row in the region B), all the pixels in the effective pixel region are reset at a predetermined timing.
For this reason, no pixel in which charges are continuously accumulated without being reset does not occur, so that adverse effects on the pixel signal are eliminated, and a high-quality captured image signal can be obtained. Further, since the deterioration of the pixel due to not being reset is prevented, the reliability is also improved.

  Furthermore, since it is not necessary to perform the read operation for all the rows in the effective pixel area for the purpose of resetting all the pixels at the time of HD standard reading, it becomes easy to increase the frame rate. In particular, it is also suitable for performing a high frame rate operation for HD standard high-definition video.

Further, both sequential reset and batch reset can be applied as suitable reset operations, and if configured as shown in FIG. 10 (c), batch reset / sequential reset can be selected according to the model or operation mode. Is expensive.
Further, for example, as shown in FIG. 8, if a configuration of all row reset as a so-called global shutter is applied, there is an advantage that the batch reset circuit 3c can be easily realized.

Also, the reset operation timing can be various examples such as a communication period, a frame reading period, or a column reading period and a horizontal transfer period within the horizontal period, and can be selected according to the convenience of processing. It will be good and the degree of freedom of design will be high.
In addition, the optimum reset mode and reset timing can be set by performing batch reset / sequential reset and setting the reset timing in consideration of the noise level and the like.

By the way, the present invention can be applied not only to HD standard readout but also to readout in which there is a row that does not include a pixel from which a pixel signal is read out in an effective region.
For example, an operation mode in which a part of the effective area is read as in the area A1 in FIG. 21 is known as window reading.
In this case, the captured image signal is output only from the pixels in the area A1. The pixels in the region A2 are scanned at the same time when the pixels in the region A1 are read out, so that they are reset periodically. On the other hand, if the pixels in the region B are not scanned, there is no opportunity for reset.
For this reason, conventionally, when such window reading is performed, a method has been used in which all rows are accessed and only necessary portions are read due to the problem of resetting rows in the region B that is not read.
However, in this method, the time required for one frame is not different from the time for reading all the pixels, and the frame rate in window reading cannot be increased.
However, even in the case of such window reading, such a problem can be solved if the pixel reset of the region B is executed in the same manner as in the above embodiment. In other words, the reset function for rows that are not read is effective in increasing the frame rate at the time of window reading, and can be said to be an appropriate method for providing high-speed imaging and high-speed AF functions.

It is a block diagram of the principal part of the solid-state imaging device of an embodiment of the invention. It is explanatory drawing of the pixel of embodiment. It is explanatory drawing of the read-out operation | movement period of embodiment. It is explanatory drawing of extraction of the pixel area | region of embodiment. It is a block diagram of the vertical scanning circuit provided with the reset address decoder of an embodiment. It is explanatory drawing of the scanning waveform by the vertical scanning circuit of embodiment. It is explanatory drawing of the example of the other scanning waveform by the vertical scanning circuit of embodiment. It is a block diagram of the vertical scanning circuit provided with the collective reset circuit of embodiment. It is explanatory drawing of the scanning waveform by the vertical scanning circuit of embodiment. It is explanatory drawing of the structural example of the vertical scanning circuit of embodiment. It is explanatory drawing of the sequential reset operation | movement in the communication period of embodiment. It is explanatory drawing of the batch reset operation | movement in the communication period of embodiment. It is explanatory drawing of the sequential reset operation | movement in the frame read-out period of embodiment. It is explanatory drawing of the sequential reset operation | movement in the frame read-out period of embodiment. It is explanatory drawing of the sequential reset operation | movement in the frame read-out period of embodiment. It is explanatory drawing of the sequential reset operation | movement in the frame read-out period of embodiment. It is explanatory drawing of the batch reset operation | movement in the flame | frame read-out period of embodiment. It is explanatory drawing of the batch reset operation | movement in the flame | frame read-out period of embodiment. It is explanatory drawing of the batch reset operation | movement in the flame | frame read-out period of embodiment. It is explanatory drawing of the sequential / batch reset operation | movement in the horizontal transfer period of embodiment. It is explanatory drawing of extraction of the pixel area | region of the modification of embodiment. It is explanatory drawing of extraction of a pixel area. It is explanatory drawing of the influence by pixel structure and electric charge accumulation continuation.

Explanation of symbols

1 pixel array, 2 timing generator, 3 vertical scanning circuit, 3a reset address decoder, 3b readout address decoder, 3c collective reset circuit, 4 voltage level shifter, 5 column CDS section, 6 horizontal scanning circuit, 7 output circuit

Claims (8)

Pixel sensor means comprising a solid-state imaging device arranged in an array in the row direction and the column direction, and each of the solid-state imaging devices obtains a pixel signal based on charges accumulated according to incident light; and
Vertical scanning means for selecting a row of the pixel sensor means and executing reading of the pixel signal from the solid-state imaging device in each column of the selected row;
An output unit that performs processing on the pixel signal read by the vertical scanning unit and outputs a captured image signal;
When the vertical scanning unit performs reading of the pixel signal and resetting a pixel in a part of the effective pixel region of the pixel sensor unit, the vertical scanning unit selects a pixel from which the pixel signal is read in the effective pixel region. A solid-state imaging device, wherein only a pixel reset is executed for a row not included. The vertical scanning means includes
A read address decoder for selecting a row on which the pixel signal is read and the pixel is reset;
A reset address decoder that sequentially selects rows that only perform pixel reset;
The solid-state imaging device according to claim 1, further comprising: The vertical scanning means includes
A read address decoder for selecting a row on which the pixel signal is read and the pixel is reset;
A batch reset circuit that batch-selects rows that do not include pixels from which pixel signals are read; and
The solid-state imaging device according to claim 1, further comprising: In a frame cycle unit consisting of a control communication period and a frame readout period,
Output of the captured image signal by the pixel sensor means, the vertical operation means, and the output means is performed during the frame readout period,
2. The solid-state imaging device according to claim 1, wherein pixel reset for a row not including a pixel from which a pixel signal is read by the vertical operation unit is performed during the control communication period. In a frame cycle unit consisting of a control communication period and a frame readout period,
Output of the captured image signal by the pixel sensor means, the vertical operation means, and the output means is performed during the frame readout period,
2. The solid-state imaging device according to claim 1, wherein pixel reset for a row not including a pixel from which a pixel signal is read by the vertical operation unit is also performed during the frame reading period. The line readout period for performing the readout operation for one row of the pixel sensor means is such that a column readout period for reading out a pixel signal from a pixel in a selected row by vertical transfer, and a pixel signal read out during the column readout period in order. It consists of a horizontal transfer period that is horizontally transferred and output as a captured image signal for one row,
2. The solid-state imaging device according to claim 1, wherein pixel reset for a row not including a pixel from which a pixel signal is read by the vertical operation unit is performed during the horizontal transfer period. In the pixel sensor means, the effective pixel region has a 4: 3 pixel array in the row direction and the column direction,
The vertical scanning means is included in the 16: 9 area in the effective pixel area when the pixel signal is read out and reset in the 16: 9 area cut out from the effective pixel area. The solid-state imaging device according to claim 1, wherein only a pixel reset is executed for a row that does not exist. With respect to the pixel sensor means that the solid-state imaging devices are arranged in an array in the row direction and the column direction, and each solid-state imaging device obtains a pixel signal based on charges accumulated according to incident light,
When the pixel signal readout and pixel reset are executed for a part of the effective pixel area of the pixel sensor means, the row in the effective pixel area does not include the pixel from which the pixel signal is read out. A pixel signal reading method, wherein only pixel reset is executed.

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