JP2009225021A - Solid-state imaging apparatus and electronic information apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a CMOS image sensor wherein a noise superposed on a power source voltage is avoided from affecting the signal level of an output signal line which is read with a horizontal scanning circuit, resulting in improved resistance against the noise superposed on the power source voltage, thereby suppressing degradation in picture quality such as appearance of horizontal streaks on an imaged screen under the effect of the noise. <P>SOLUTION: Relating to a vertical scanning circuit 110 in a solid-state imaging apparatus 100 which selects a pixel row in a pixel array after a specified pixel row is selected, supplying a power source voltage to a selective signal line Ls of the specified pixel row is cut off at a level reading timing for reading the signal level of an output signal line Lr by a horizontal scanning circuit. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and an electronic information device, and more particularly to a solid-state imaging device such as a CMOS image sensor used in an electronic imaging device such as a video camera or a digital camera, and an electronic information device equipped with the solid-state imaging device. It is about.

  Conventionally, in solid-state imaging devices, there are cases where noise is superimposed on the power supply, which causes a reduction in operating margin and problems. One technique for suppressing this power supply noise is disclosed in Patent Document 1 below.

  In Patent Document 1, in a solid-state imaging device including a photoelectric conversion element and a differential amplifier circuit provided in a subsequent stage, a pixel from the photoelectric conversion element which is one input signal of the differential amplifier circuit Similarly to the signal, it is described that noise components at the output of the differential amplifier circuit can be removed by superimposing noise or the like on a reference signal which is another input of the differential amplifier circuit.

  However, in order to remove noise at the subsequent stage of the photoelectric conversion element, a complicated circuit such as a differential amplifier circuit is required, and such a circuit occupies the chip area. In addition, when processing is performed at the subsequent stage of the photoelectric conversion element, various disturbance noises are also mixed in, causing problems such as difficulty in noise removal.

  FIG. 5 is a block diagram showing an overall configuration of a conventional CMOS image sensor. FIG. 6 shows a circuit configuration of one pixel in a pixel array constituting the CMOS image sensor and a vertical scanning circuit corresponding to one pixel row. The circuit configuration of (DECV circuit) is shown.

  The CMOS image sensor 200 shown in FIG. 5 is provided with a pixel array 200a in which a plurality of pixels Px are two-dimensionally arranged, and for each pixel column in the pixel array 200a, and signals obtained from the pixels in the pixel column. An output signal line Lr for outputting a level and a selection signal line Ls provided for each pixel row in the pixel array and for selecting the pixel row are provided. This output signal line Lr is connected to a constant current source Pw.

  In addition, the CMOS image sensor 200 is a vertical scanning circuit that drives a selection signal line Ls of a specific pixel row with a power supply voltage so that the specific pixel row is selected based on the selection control signals SELn,. 210, and a horizontal scanning circuit 220 that reads a signal level output to the output signal line Ls and outputs a pixel signal.

  Note that the pixel array 200a, the vertical scanning circuit 210, and the horizontal scanning circuit 220 are configured by circuit elements, wirings, and the like formed on a semiconductor substrate.

  The pixel Px includes a photoelectric conversion unit PD (photodiode) that generates a signal charge corresponding to the amount of received light by photoelectric conversion of incident light, a charge storage unit FD (floating diffusion) that stores the signal charge, and the signal charge. A transfer transistor Ttr for transferring from the photoelectric conversion unit PD to the charge storage unit FD, a reset transistor Rtr for resetting signal charges stored in the charge storage unit FD, and a signal level of the charge storage unit FD are amplified. It has an amplification transistor Atr that outputs to the output signal line Lr, and a selection transistor Str that is controlled by the selection signal line Ls to supply a power supply voltage to the amplification transistor.

  Here, the transfer transistor Ttr is connected between the photodiode PD and the charge storage unit FD, and its gate is connected to the transfer signal line Lt. The reset transistor Rtr is connected between the AVDD power supply and the charge storage unit FD, and its gate is connected to the reset signal line Lrs. The selection transistor Str and the amplification transistor Atr are connected in series between the AVDD power source and the output signal line Lr. The drain of the selection transistor Str is connected to the AVDD power source, the source of the amplification transistor Atr is connected to the output signal line Lr, the gate of the selection transistor Str is connected to the selection signal line Ls, and the gate of the amplification transistor Atr is the charge storage. Connected to the unit FD. Here, the serial connection selection transistor Str and amplification transistor Atr connected between the AVDD power supply and the output signal line Lr are connected to the amplification transistor Str on the power supply side, and the selection transistor on the output signal line Lt side. What connected Atr may be used. That is, the drain of the amplification transistor Atr is connected to the AVDD power source, the source of the selection transistor Str is connected to the output signal line Lr, the gate of the selection transistor Str is connected to the selection signal line Ls, and the gate of the amplification transistor Atr is It may be connected to the charge storage unit FD.

  The capacitor Csf is a parasitic capacitor between the selection signal line Ls and the charge storage unit FD, the capacitor Caf is a parasitic capacitor between the AVDD power supply and the charge storage unit FD, and the capacitor Cfg is This is a parasitic capacitance (grounding capacitance) between the ground and the charge storage unit FD.

  Here, the pixel array 200a is configured by arranging pixels of a 4Tr configuration having the transfer transistor Ttr in the X direction and the Y direction. However, the pixel array does not have the transfer transistor Ttr. There is also a thing.

  Further, the vertical scanning circuit (DECV circuit) 210 includes a SEL signal SELn,..., SELm that controls the selection transistor Str of each pixel Px, and an RST signal RSTn,..., RSTm that controls the reset transistor Rtr. , TXm for controlling the transfer gate (transfer transistor), and a drive control circuit for driving and controlling these transistors.

  The column circuit (horizontal scanning circuit) 220 reads the signal level output to each output signal line Lr and outputs a digital pixel signal. The column circuit (horizontal scanning circuit) 220 outputs the charge storage unit FD when the charge storage unit FD is reset. CDS (correlation) that reads the potential (reset potential) and the potential (signal potential) of the charge storage unit FD when the signal charge is stored in the charge storage unit FD from the output signal line Lr and outputs the difference potential A double sampling) circuit 221, an AGC circuit 222 that amplifies the differential potential, and an AD conversion circuit (ADC circuit) 223 that AD-converts the output of the AGC circuit 222. The column circuit 220 removes noise such as reset noise and FPN noise (fixed pattern noise) from the analog signal output from the pixel array 200a, converts the analog pixel signal into a digital pixel signal, and outputs the digital pixel signal. .

  The DECV circuit converts the signal level of the inversion selection signal XSEL and outputs the selection signal SEL to the selection signal line Lr. The DECV circuit converts the signal level of the inversion reset signal XRST and outputs the reset signal SEL to the reset signal line Lrs. And an inverter circuit Tv that converts the signal level of the inverted transfer signal XTX and outputs the transfer signal TX to the transfer signal line Lt. Note that the capacitance Cs is a parasitic capacitance between the selection signal line Ls and the ground, the capacitance Cr is a parasitic capacitance between the reset line Lrs and the ground, and further, the capacitance Ct is the transfer signal line Lt and the ground. Is the parasitic capacitance between.

  Next, the operation of the conventional CMOS image sensor will be described.

  FIG. 7 is a waveform diagram for explaining the operation of this CMOS image sensor.

  In such a CMOS image sensor 200, photoelectric conversion of incident light is performed in each pixel of the pixel array 200a, and a photoelectric conversion signal obtained in each pixel is read out as a pixel signal by the DECV circuit 210 and the column circuit 220.

  For example, in the pixel Px shown in FIG. 6, when the reset signal RST becomes a high level, the reset transistor Rtr is turned on, the voltage of the pixel power supply AVDD is applied to the charge storage unit FD, and the potential of the charge storage unit FD is the reset potential. It becomes. Next, after the reset signal RST changes from the high level to the low level, when the selection signal SEL changes to the high level, the selection transistor Atr becomes conductive and the pixel Px is selected. In this selected state, the potential of the charge storage unit FD (the gate of the amplification transistor Atr) is amplified by the amplification transistor Atr and output to the output signal line Lr. At this timing, the reset potential is amplified and output. It is output to the signal line Lr. The CDS circuit 221 of the column circuit 220 samples the amplified reset potential at the timing Tra and holds the sampling value. Thereafter, when the transfer signal TX becomes high level, the signal charge obtained by photoelectric conversion in the photoelectric conversion unit PD is transferred from the photoelectric conversion unit PD to the charge accumulation unit FD. At this time, the signal potential of the charge storage portion FD is amplified by the amplification transistor Atr and output to the output signal line Lr. The CDS circuit 221 of the column circuit 220 samples the amplified signal potential at the timing Tsa and holds the sampling value.

  When the CDS circuit 221 outputs the differential voltage between the sampled reset potential and the sampled signal potential to the AGC circuit 222, the AGC circuit 222 amplifies the differential voltage and outputs it to the ADC circuit 223. The ADC circuit 223 converts this analog differential voltage into a digital signal and outputs it as a digital pixel signal.

  Next, resistance to power supply noise of such a solid-state imaging device will be described.

  When the sine wave noise Npw is mixed into the pixel power supply AVDD of the solid-state imaging device, a potential fluctuation Nfd is generated in the charge storage unit FD due to the coupling capacitance Caf between the pixel power supply and the charge storage unit (floating diffusion) FD, which is the source follower. (Amplification transistor) Atr is output as the potential fluctuation Nrs to the vertical signal line Lr. Further, the control signal lines Lt, Lts, and Ls of the transfer signal TX, the selection signal SEL, and the reset signal RST are supplied with power from the DECV circuit 210 instead of the pixel power supply AVDD, and the power of the DECV circuit 210 is also supplied. In many cases, the pixel power supply AVDD is basically common. Therefore, when the sine wave noise Npw is mixed into the pixel power supply AVDD, not only the pixel is directly affected but also noise is mixed into the power supply of the DECV circuit 210, and the control signal itself becomes a signal including the noise Nd. . For example, the selection signal SEL, the reset signal RST, and the transfer signal TX include noises Nd1, Nd2, and Nd3, respectively.

  Among these, when the noise Nd1 is mixed in the selection signal SEL, the sine wave noise Nfd is superimposed on the charge storage unit FD by the parasitic coupling capacitance Csf between the selection signal SEL and the charge storage unit FD. As a result, since the sine wave noise Nfd is superimposed on the vertical signal line Lr by the source follower circuit including the amplification transistor Atr, it is superimposed on the vertical signal line Lr by the horizontal line period, that is, for each pixel row. Since the sampling location of the sine wave Nrs by the CDS circuit 22 is different, it appears as a horizontal stripe on the imaging screen.

  FIG. 8 shows a simulation result in which sine wave noise Npw (see FIG. 6) is superimposed on the pixel power supply AVDD, which affects the selection signal SEL, and the signal Nfd of the charge storage unit FD fluctuates.

  In order to clarify the effect in the simulation, the sine wave noise was evaluated under the condition that the sine wave noise amplitude 100 mV (± 50 mV) was superimposed only on the DECV power source and the sine wave noise was not superimposed on the pixel power source. .

  Referring to FIG. 8, the selection signal SEL fluctuates due to the sine wave noise amplitude of 100 mV (± 50 mV) superimposed on the DECV power source (see the portion A indicated by the dotted line in FIG. 8C), and then the selection signal line Ls Due to the parasitic coupling capacitance Csf with the charge storage unit FD, sine wave noise (amplitude 33.7 mV) is superimposed on the charge storage unit FD, and the potential of the charge storage unit FD fluctuates (see FIG. 8A). ). The superimposed sine wave noise (amplitude 33.7 mV) is superimposed on the vertical signal line Lr by the source follower circuit including the amplification transistor Atr. That is, in this example, about 1/3 of the noise Npw input to the power supply is superimposed on the potential level of the charge storage unit FD. FIG. 8B shows the waveform of the reset signal RST, and FIG. 8D shows the waveform of the transfer signal TX.

  In the pixel Px shown in FIG. 6, a coupling capacitor Caf exists between the pixel power supply AVDD and the charge storage unit FD. Therefore, both the noise directly affecting the vertical signal line Lr from the pixel power supply through the coupling capacitance and the noise affecting the selection signal line from the power supply of the DECV inverter Sv are dominant, and noise resistance is improved. It gets worse.

Therefore, there is a method for preventing the mixing of power supply noise by generating an internal voltage from the power supply of the solid-state imaging device by a regulator and using this as the pixel power supply AVDD. However, an increase in the layout area caused by the regulator, the regulator itself It is not a good idea to generate noise components due to, and to reduce the dynamic range of pixels.
JP 2003-198949 A

  As described above, the selection signal SEL for selecting a pixel fluctuates due to noise superimposed on the power supply, and then charges are charged by capacitive coupling due to the parasitic capacitance Caf between the selection signal line Ls and the charge storage unit FD. Noise is superimposed on the potential of the storage unit FD. This superimposed noise is superimposed on the potential of the vertical signal line Lr by the source follower circuit including the amplification transistor Atr, which causes image quality degradation.

  The present invention has been made in order to solve the above-described conventional problems, and can improve resistance to noise superimposed on the power supply voltage. As a result, the horizontal lines of the imaging screen and the like are affected by such noise. An object of the present invention is to obtain a solid-state imaging device capable of improving the deterioration of image quality such as the appearance of an electronic information device equipped with such a solid-state imaging device.

  A solid-state imaging device according to the present invention includes a pixel array in which a plurality of pixels are arranged, and an output signal line that is provided for each pixel column in the pixel array and that outputs a signal level obtained from the pixels in the pixel column A solid-state imaging device provided for each pixel row in the pixel array, and a selection signal line for selecting the pixel row, so that a specific pixel row is selected based on a selection control signal A vertical scanning circuit that drives a selection signal line of the specific pixel row by a power supply voltage, and a horizontal scanning circuit that reads a signal level output to the output signal line and outputs a pixel signal, and the vertical scanning circuit In the level reading timing in which the signal level of the output signal line is read by the horizontal scanning circuit after the specific pixel row is selected, the supply of the power supply voltage to the selection signal line of the specific pixel row Shut off Cormorant is configured, the object is achieved.

  According to the present invention, in the solid-state imaging device, the vertical scanning circuit is supplied with the power supply voltage and drives the selection signal line based on the selection control signal, the signal line driving circuit, and the signal line driving circuit And a switch circuit provided between a power supply for supplying a power supply voltage, and after the specific pixel row is selected, the selection signal line of the specific pixel row is in a floating state at the level reading timing. It is preferable to control the switch circuit.

  According to the present invention, in the solid-state imaging device, the vertical scanning circuit preferably includes a delay circuit that delays the selection control signal, and the switch circuit is controlled by an output of the delay circuit.

  In the solid-state imaging device according to the aspect of the invention, it is preferable that the delay circuit includes a multistage-connected inverter circuit, and the number of stages of the inverter circuit is set by an external setting signal.

  In the solid-state imaging device according to the present invention, the switch circuit is a P-channel transistor connected between the power source and the signal line driver circuit, and the gate of the P-channel transistor has the delay circuit The output is preferably connected.

  In the solid-state imaging device according to the present invention, it is preferable that the signal line driving circuit is an inverter circuit having a CMOS configuration.

  According to the present invention, in the solid-state imaging device, the pixel includes a photoelectric conversion unit that generates a signal charge according to a received light amount by photoelectric conversion of incident light, a charge storage unit that stores the signal charge, and the signal charge. A transfer transistor that transfers from the photoelectric conversion unit to the charge storage unit, a reset transistor that resets signal charges stored in the charge storage unit, and amplifies the signal level of the charge storage unit and outputs the amplified signal level to the output signal line It is preferable to include an amplifying transistor to be controlled and a selection transistor controlled to supply the power supply voltage to the amplifying transistor by the selection signal line.

  According to the present invention, in the solid-state imaging device, the pixel includes a photoelectric conversion unit that generates a signal charge according to a received light amount by photoelectric conversion of incident light, a charge storage unit that stores the signal charge, and the signal charge. A transfer transistor that transfers from the photoelectric conversion unit to the charge storage unit, a reset transistor that resets signal charges stored in the charge storage unit, and the power supply voltage are supplied to amplify the signal level of the charge storage unit And a selection transistor connected between the amplification transistor and the output signal line, and controlled to output the signal level amplified by the amplification transistor to the output signal line by the selection signal line It is preferable to include a transistor.

  According to the present invention, in the solid-state imaging device, the horizontal scanning circuit reads a reset level of the charge storage unit when the signal charge stored in the charge storage unit is reset, and the signal charge is A differential circuit that reads a signal charge level of the charge storage unit when transferred from the photoelectric conversion unit to the charge storage unit, and outputs a difference between the reset level and the signal charge level as a pixel signal; The vertical scanning circuit includes a reset level reading timing at which the reset level of the output signal line is read by the horizontal scanning circuit after the specific pixel row is selected, and a signal of the output signal line by the horizontal scanning circuit. In a period including a signal charge level reading timing at which the charge level is read, supply of the power supply voltage to the selection signal line of the specific pixel row is cut off. Which is preferably earthenware pots configuration.

  According to the present invention, in the solid-state imaging device, the pixel includes a photoelectric conversion unit that generates a signal charge according to a received light amount by photoelectric conversion of incident light, a charge storage unit that stores the signal charge, and the charge storage unit. A reset transistor that resets the signal charge accumulated in the signal, an amplification transistor that amplifies the signal level of the charge accumulation unit and outputs the amplified signal level to the output signal line, and supplies the power supply voltage to the amplification transistor through the selection signal line It is preferable to have a selection transistor controlled to do so.

  According to the present invention, in the solid-state imaging device, the pixel includes a photoelectric conversion unit that generates a signal charge according to a received light amount by photoelectric conversion of incident light, a charge storage unit that stores the signal charge, and the charge storage unit. A reset transistor that resets the signal charge stored in the power supply, an amplification transistor that is supplied with the power supply voltage and amplifies and outputs the signal level of the charge storage unit, and is connected between the amplification transistor and the output signal line And a selection transistor controlled by the selection signal line to output the signal level amplified by the amplification transistor to the output signal line.

  According to the present invention, in the solid-state imaging device, the horizontal scanning circuit includes a reset level of the charge storage unit when the signal charge stored in the charge storage unit is reset, and the photoelectric conversion unit before the reset. And a differential circuit that reads the signal charge level of the charge storage unit in a state where the signal charge from the charge storage unit is stored in the charge storage unit and outputs the difference between the reset level and the signal charge level as a pixel signal. The vertical scanning circuit includes a signal charge level reading timing at which a signal charge level of the output signal line is read by the horizontal scanning circuit after the specific pixel row is selected, and the horizontal scanning circuit The power supply voltage supply to the selection signal line is cut off during a period including the reset level reading timing at which the reset level of the output signal line is read. It is preferred that the.

  According to the present invention, in the solid-state imaging device, the vertical scanning circuit is supplied with the power supply voltage and drives the selection signal line based on the selection control signal, the signal line driving circuit, and the signal line driving circuit And a switch circuit provided between the selection signal line and the switch circuit so that the selection signal line of the specific pixel row is in a floating state at the level reading timing after the specific pixel row is selected. Is preferably controlled.

  According to the present invention, in the solid-state imaging device, the vertical scanning circuit preferably includes a delay circuit that delays the selection control signal, and the switch circuit is controlled by an output of the delay circuit.

  In the solid-state imaging device according to the aspect of the invention, it is preferable that the delay circuit includes a multistage-connected inverter circuit, and the number of stages of the inverter circuit is set by an external setting signal.

  In the solid-state imaging device according to the present invention, the switch circuit is a transfer gate that is connected between the signal line driving circuit and the selection signal line and includes a P-channel transistor and an N-channel transistor connected in parallel. It is preferable that the output of the delay circuit is connected to the gates of both transistors.

  In the solid-state imaging device according to the present invention, it is preferable that the signal line driving circuit is an inverter circuit having a CMOS configuration.

  According to the present invention, in the solid-state imaging device, the pixel includes a photoelectric conversion unit that generates a signal charge according to a received light amount by photoelectric conversion of incident light, a charge storage unit that stores the signal charge, and the signal charge. A transfer transistor that transfers from the photoelectric conversion unit to the charge storage unit, a reset transistor that resets signal charges stored in the charge storage unit, and amplifies the signal level of the charge storage unit and outputs the amplified signal level to the output signal line It is preferable to include an amplifying transistor to be controlled and a selection transistor controlled to supply the power supply voltage to the amplifying transistor by the selection signal line.

  According to the present invention, in the solid-state imaging device, the pixel includes a photoelectric conversion unit that generates a signal charge according to a received light amount by photoelectric conversion of incident light, a charge storage unit that stores the signal charge, and the signal charge. A transfer transistor that transfers from the photoelectric conversion unit to the charge storage unit, a reset transistor that resets signal charges stored in the charge storage unit, and the power supply voltage are supplied to amplify the signal level of the charge storage unit And a selection transistor connected between the amplification transistor and the output signal line, and controlled to output the signal level amplified by the amplification transistor to the output signal line by the selection signal line It is preferable to include a transistor.

  According to the present invention, in the solid-state imaging device, the horizontal scanning circuit reads a reset level of the charge storage unit when the signal charge stored in the charge storage unit is reset, and the signal charge is A differential circuit that reads a signal charge level of the charge storage unit when transferred from the photoelectric conversion unit to the charge storage unit, and outputs a difference between the reset level and the signal charge level as a pixel signal; The vertical scanning circuit includes a reset level reading timing at which the reset level of the output signal line is read by the horizontal scanning circuit after the specific pixel row is selected, and a signal of the output signal line by the horizontal scanning circuit. In a period including a signal charge level reading timing at which the charge level is read, supply of the power supply voltage to the selection signal line of the specific pixel row is cut off. Which is preferably earthenware pots configuration.

  According to the present invention, in the solid-state imaging device, the pixel includes a photoelectric conversion unit that generates a signal charge according to a received light amount by photoelectric conversion of incident light, a charge storage unit that stores the signal charge, and the charge storage unit. A reset transistor that resets the signal charge accumulated in the signal, an amplification transistor that amplifies the signal level of the charge accumulation unit and outputs the amplified signal level to the output signal line, and supplies the power supply voltage to the amplification transistor through the selection signal line It is preferable to have a selection transistor controlled to do so.

  According to the present invention, in the solid-state imaging device, the pixel includes a photoelectric conversion unit that generates a signal charge according to a received light amount by photoelectric conversion of incident light, a charge storage unit that stores the signal charge, and the charge storage unit. A reset transistor that resets the signal charge stored in the power supply, an amplification transistor that is supplied with the power supply voltage and amplifies and outputs the signal level of the charge storage unit, and is connected between the amplification transistor and the output signal line And a selection transistor controlled by the selection signal line to output the signal level amplified by the amplification transistor to the output signal line.

  According to the present invention, in the solid-state imaging device, the horizontal scanning circuit includes a reset level of the charge storage unit when the signal charge stored in the charge storage unit is reset, and the photoelectric conversion unit before the reset. And a differential circuit that reads the signal charge level of the charge storage unit in a state where the signal charge from the charge storage unit is stored in the charge storage unit and outputs the difference between the reset level and the signal charge level as a pixel signal. The vertical scanning circuit includes a signal charge level reading timing at which a signal charge level of the output signal line is read by the horizontal scanning circuit after the specific pixel row is selected, and the horizontal scanning circuit The power supply voltage supply to the selection signal line is cut off during a period including the reset level reading timing at which the reset level of the output signal line is read. It is preferred that the.

  An electronic information device according to the present invention is an electronic information device provided with an image pickup unit that picks up an image of a subject, and the image pickup unit is the solid-state image pickup device, thereby achieving the object.

  The operation of the present invention will be described below.

  In the present invention, in the solid-state imaging device, the vertical scanning circuit that selects the pixel row in the pixel array is the level reading in which the signal level of the output signal line is read by the horizontal scanning circuit after the specific pixel row is selected. At the timing, supply of the power supply voltage to the selection signal line of a specific pixel row is cut off, so that the selection signal line is in a floating state when the signal level of the output signal line is read by the horizontal scanning circuit. For this reason, it is possible to avoid the influence of noise superimposed on the power supply voltage from reaching the signal level of the output signal line read by the horizontal scanning circuit. As a result, it is possible to increase resistance to noise superimposed on the power supply voltage, and to improve image quality degradation such as horizontal stripes appearing on the imaging screen due to such noise.

  As described above, according to the present invention, a pixel array in which a plurality of pixels are arranged, and an output that is provided for each pixel column in the pixel array and that outputs a signal level obtained from the pixels in the pixel column In a solid-state imaging device including a signal line and a selection signal line provided for each pixel row in the pixel array for selecting the pixel row, a specific pixel row is selected based on a selection control signal. A vertical scanning circuit that drives a selection signal line of the specific pixel row by a power supply voltage, and a horizontal scanning circuit that reads a signal level output to the output signal line and outputs a pixel signal, and the vertical scanning circuit At the level reading timing when the signal level of the output signal line is read by the horizontal scanning circuit after the specific pixel row is selected, supply of the power supply voltage to the selection signal line of the specific pixel row Shut off With this configuration, it is possible to increase resistance to noise superimposed on the power supply voltage, and thereby, it is possible to improve image quality deterioration such as horizontal stripes appearing on the imaging screen due to such noise. is there.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a diagram illustrating a solid-state imaging device according to Embodiment 1 of the present invention. A circuit configuration of one pixel in a pixel array constituting the solid-state imaging device and a vertical scanning circuit (DECV) corresponding to one pixel row. Circuit).

  The solid-state imaging device 100 according to the first embodiment is a CMOS image sensor, and a pixel array in which a plurality of pixels Px are two-dimensionally arranged as in the conventional solid-state imaging device (CMOS image sensor) 200 (see FIG. 5). An output signal line (hereinafter also referred to as a vertical signal line) Lr provided for each pixel column in the pixel array and outputting a signal level obtained by the pixel Px of the pixel column, and a pixel row in the pixel array And a selection signal line Ls for selecting a pixel row. This output signal line Lr is connected to a constant current source Pw. Here, each pixel has a 4-transistor configuration (4TR configuration) as in the conventional case.

  Further, the solid-state imaging device 100 is a vertical scanning circuit that drives a selection signal line Ls of a specific pixel row with a power supply voltage so that a specific pixel row is selected based on the selection control signals SELn,. 110, and a horizontal scanning circuit (see FIG. 5) that reads a signal level output to the output signal line Lr and outputs a pixel signal.

  In the solid-state imaging device 100 according to the first embodiment, the vertical scanning circuit 110 that selects the pixel row in the pixel array is used to read the signal level of the output signal line by the horizontal scanning circuit after the specific pixel row is selected. At the level reading timing to be performed, the supply of the power supply voltage to the selection signal line of a specific pixel row is cut off, so that at the time when the signal level of the output signal line is read by the horizontal scanning circuit. The selection signal line is in a floating state, so that the influence of noise superimposed on the power supply voltage can be prevented from reaching the signal level of the output signal line read by the horizontal scanning circuit. It is.

  Since the pixel array and the horizontal scanning circuit in the first embodiment are the same as the conventional one, the vertical scanning circuit 110 will be mainly described in detail below.

  The vertical scanning circuit (DECV circuit) 110 according to the first embodiment includes a SEL signal SELn,..., SELm that controls the selection transistor Str of each pixel Px, and an RST signal RSTn,... That controls the reset transistor Rtr. , RSTm and TX signals TXn,..., TXm for controlling the transfer gates (transfer transistors), and driving control of these transistors.

  Here, the DECV circuit 110 inverts the signal level of the inverted selection signal XSEL and outputs the selection signal SEL to the selection signal line Lr, and inverts the signal level of the inverted reset signal XRST to reset the signal line Lrs. The inverter circuit Rv for outputting the reset signal SEL and the inverter circuit Tv for inverting the signal level of the inverted transfer signal XTX and outputting the transfer signal TX to the transfer signal line Lt. The DECV circuit 110 includes a switch circuit 120 provided between the inverter circuit (signal line drive circuit) Sv and a pixel power supply AVDD that supplies the power supply voltage. After the specific pixel row is selected, At the level reading timing, the switch circuit 120 is controlled so that the selection signal line of the specific pixel row is in a floating state. Specifically, the vertical scanning circuit 110 includes a delay circuit 111 that delays the selection control signal, and the switch circuit 120 is controlled by the output of the delay circuit 111.

  The delay circuit 111 has a multi-stage inverter circuit, and the number of stages of the inverter circuit is set by an external setting signal. The switch circuit 120 includes a power supply voltage AVDD and an inverter circuit Sv. The P-channel transistor is connected between them, and the output of the delay circuit 111 is connected to the gate of the P-channel transistor. Here, in the inverter circuit, a P-channel transistor and an N-channel transistor are connected in series between the power source and the ground, and the gates of the two transistors are connected in common to serve as an input node of the inverter circuit. The connection point of the transistor is the output node.

  Note that the capacitance Cs is a parasitic capacitance between the selection signal line Ls and the ground, the capacitance Cr is a parasitic capacitance between the reset line Lrs and the ground, and further, the capacitance Ct is the transfer signal line Lt and the ground. Is the parasitic capacitance between.

  Next, the operation of the solid-state imaging device according to the first embodiment will be described.

  FIG. 2 is a waveform diagram for explaining the operation of the CMOS image sensor (solid-state imaging device) 100 according to the first embodiment.

  In such a CMOS image sensor 100, photoelectric conversion of incident light is performed in each pixel of the pixel array (see FIG. 5), and the photoelectric conversion signal obtained in each pixel is the DECV circuit 110 and the column circuit (see FIG. 5). ) Is read out as a pixel signal.

  For example, in the pixel Px having the 4Tr configuration shown in FIG. 1, when the reset signal RST becomes high level, the reset transistor Rtr is turned on, and the voltage of the pixel power supply AVDD is applied to the charge storage unit FD, and the potential of the charge storage unit FD. Becomes a reset potential. Next, after the reset signal RST changes from the high level to the low level, when the selection signal SEL changes to the high level, the selection transistor Atr becomes conductive and the pixel Px is selected. In this selected state, the potential of the charge storage unit FD (the gate of the amplification transistor Atr) is amplified by the amplification transistor Atr and output to the output signal line Lr. At this timing, the reset potential is amplified and output. It is output to the signal line Lr.

  Then, after the selection signal SEL becomes high level, the switch circuit 120 is turned off as indicated by the waveform SW with a delay of the set delay time in the delay circuit 111, and the selection signal line SEL enters a floating state. Thereafter, at the timing Tra immediately before the transfer signal TX rises, the CDS circuit (see FIG. 5) of the column circuit samples the amplified reset potential and holds the sampling value. Thereafter, when the transfer signal TX becomes high level, the signal charge obtained by photoelectric conversion in the photoelectric conversion unit PD is transferred from the photoelectric conversion unit PD to the charge accumulation unit FD. At this time, the signal potential of the charge storage portion FD is amplified by the amplification transistor Atr and output to the output signal line Lr.

  Next, at the timing Tsa immediately after the transfer signal TX becomes low level and immediately before the selection signal SEL becomes low level, the CDS circuit of the column circuit samples and samples the amplified signal potential of the charge storage unit FD. Holds the value. Thereafter, when the selection signal SEL becomes a low level, the switch circuit 120 is turned on as shown by the waveform SW with a delay of the set delay time in the delay circuit 111.

  On the other hand, the CDS circuit of the horizontal scanning circuit outputs a differential voltage between the sampled reset potential and the sampled signal potential to the AGC circuit, and the AGC circuit 222 amplifies the differential voltage and outputs it to the ADC circuit 223. The ADC circuit 223 converts the analog differential voltage into a digital signal and outputs it as a digital pixel signal.

  Hereinafter, the operation of the solid-state imaging device according to the first embodiment will be described in detail in comparison with the conventional one.

  In the conventional example, as described with reference to FIG. 6, the sine wave noise Npw superimposed on the pixel power supply AVDD enters the DECV circuit 210 and is superimposed on the selection signal SEL, the reset signal RST, and the pixel charge transfer signal TX. The noise superimposed on the selection signal SEL is superimposed on the potential of the charge storage unit FD as noise Nfd by the parasitic coupling capacitance Csf between the selection signal line Ls and the charge storage unit FD. This superimposed noise Nfd is superimposed on the potential of the vertical signal line Lr by the source follower circuit of each pixel, resulting in image quality degradation.

  FIG. 7 shows the control signal timing of the DECV circuit for accessing the pixel circuit.

  Even when noise is superimposed on the RST signal for resetting the pixel, the reset level is read from the pixel after the reset signal RST changes from the H level to the L level. Therefore, the reset level sampling timing (RA timing) Tra It will not be affected by the noise level. Similarly, even when noise is superimposed on the pixel charge transfer signal TX, the signal level is read from the pixel after the transfer signal TX changes from the H level to the L level. Therefore, at the signal level sampling timing (SA timing) Tsa. Similarly, it is not affected by the noise level on the power supply.

  Next, when noise is superimposed on the pixel selection signal SEL, as described in the conventional example, the potential of the charge storage unit FD fluctuates due to the coupling capacitor Csf between the charge storage unit FD and the selection signal line Ls, This is superimposed as noise on the vertical signal line Lr. In the conventional solid-state imaging device, since the reset level and the signal level are read from the pixel in a state where the selection signal SEL is at the H level, the digital pixel signal whose noise is applied to the power supply is the output of the horizontal scanning circuit. Will be affected.

  On the other hand, in the first embodiment of the present invention, in order to solve such a problem, a switch 120 is provided between the pixel power supply AVDD and the inverter circuit (SEL power supply) Sv of the DECV circuit, and the reset level and signal are set. At the timing when the level is read from the pixel, this switch is turned off.

  FIG. 2 shows the control signal timing of the DECV circuit 110 of the first embodiment.

  The difference from the operation in the conventional DECV circuit 210 is that when a predetermined time (delay time in the delay circuit 111) elapses (timing) after the pixel selection signal SEL becomes H level, The switch 120 between the inverter circuit (SEL power supply) Sv is turned off. By turning off the switch 120 at this timing, the selection signal SEL maintains the H level and enters a floating state. In FIG. 2, this floating state is indicated by a broken line. Thus, by turning off the switch 120 between the pixel power supply AVDD and the inverter circuit (SELV SEL power supply) Sv, noise superimposed on the pixel power supply AVDD affects the signal level read by the horizontal scanning circuit. Can be completely blocked.

  FIG. 3 shows the result of a simulation similar to that shown in FIG. 8 performed in the solid-state imaging device of the first embodiment. In the simulation shown in FIG. 3, the noise tolerance improvement effect in the present embodiment is shown. Similar to the conventional example (FIG. 8), in order to clarify the effect, sine wave noise (amplitude 100 mV (± 50 mV)) is superimposed only on the power supply voltage supplied to the DECV circuit 110, and the pixel The power supply voltage was evaluated under the condition that sine wave noise was not superimposed.

  In FIG. 3, it is not confirmed that the pixel selection signal SEL fluctuates due to sine wave noise (amplitude 100 mV (± 50 mV)) superimposed on the power supply voltage to DECV (dotted line portion B in FIG. 3C). Next, a sine wave noise (amplitude 0.17 mV) is superimposed on the potential of the charge storage unit FD, though slightly, due to the parasitic coupling capacitance Csf between the selection signal line Ls and the charge storage unit FD. The upper flat portion of the waveform shown in FIG. This superimposed sine wave noise (amplitude 0.17 mV) Nfd is superimposed on the potential of the vertical signal line by the source follower circuit including the amplification transistor Atr, but is about 1/1000 of the noise Npw input to the power supply. It is a slight noise level and does not matter.

  That is, in the first embodiment, the noise (100 mV (± 50 mV)) superimposed on the power source is reduced from 33.7 mV to 0.17 mV on the charge storage unit FD of the pixel. Thus, this Embodiment 1 has a big effect with respect to the noise superimposed on the power supply voltage to DECV. In other words, an improvement in PSRR (POWER SUPPLY REJECTION RATIO), which indicates how much the noise output to the vertical signal line is affected when noise such as a sine wave is applied to the power supply, is improved. The purpose of preventing deterioration of image quality has been achieved.

  Finally, noise Npw superimposed on the pixel power source AVDD is coupled to the charge storage unit FD and output as it is by the source follower by the parasitic capacitance Caf existing between the pixel power source AVDD and the charge storage unit FD shown in FIG. Therefore, although it is a parasitic capacitance, it is a very important element. At the time of pixel layout, it is necessary to suppress the influence of power supply noise as much as possible by striving to make this capacity as small as possible. 3B shows the waveform of the reset signal RST, and FIG. 3D shows the waveform of the transfer signal TX.

  As described above, in the first embodiment, in the solid-state imaging device 100, the vertical scanning circuit 110 that selects the pixel row in the pixel array is changed to the signal level of the output signal line by the horizontal scanning circuit after the specific pixel row is selected. At the level reading timings Tra and Tsa at which reading is performed, the supply of the power supply voltage to the selection signal line of a specific pixel row is cut off. Therefore, when the signal level of the output signal line is read by the horizontal scanning circuit. Since the selection signal line is in a floating state, the influence of noise superimposed on the power supply voltage can be prevented from reaching the signal level of the output signal line read by the horizontal scanning circuit. As a result, it is possible to increase resistance to noise superimposed on the power supply voltage, and to improve image quality degradation such as horizontal stripes appearing on the imaging screen due to such noise.

In this embodiment, since the vertical scanning circuit 110 includes a simple switch 120 and a delay circuit 111, the layout area of the solid-state imaging device hardly increases.
(Embodiment 2)
FIG. 4 is a diagram for explaining a solid-state imaging device according to Embodiment 2 of the present invention. A circuit configuration of one pixel in a pixel array constituting the solid-state imaging device and a vertical scanning circuit (DECV) corresponding to one pixel row. Circuit).

  The solid-state imaging device 100a according to the second embodiment includes a DECV circuit 110a having a circuit configuration different from that of the DECV circuit 110 of the solid-state imaging device 100 according to the first embodiment. The DECV circuit 110a is a DECV circuit according to the first embodiment. Instead of the switch circuit 111 in the circuit 110, a switch circuit 120a is connected between the inverter circuit Sv and the selection signal line Ls in the first embodiment.

  The switch circuit 120a is a transfer gate composed of a pair of P-channel type transistor 121 and N-channel type transistor 122 connected in parallel, and the output of the delay circuit 111 is connected to the gates of both transistors.

  The remaining configuration of the solid-state imaging device 100a according to the second embodiment is the same as that of the solid-state imaging device according to the first embodiment.

  Also in the solid-state imaging device 100a of the second embodiment having such a configuration, a specific pixel row is selected in the vertical scanning circuit 110a that selects a pixel row in the pixel array in the solid-state imaging device 100a as in the first embodiment. Thereafter, at the level reading timings Tra and Tsa where the signal level of the output signal line is read by the horizontal scanning circuit, the supply of the power supply voltage to the selection signal line of the specific pixel row is cut off. Thus, when the signal level of the output signal line is read, the selection signal line is in a floating state. Therefore, the influence of noise superimposed on the power supply voltage is output by the horizontal scanning circuit. Can be avoided. As a result, it is possible to increase resistance to noise superimposed on the power supply voltage, and to improve image quality degradation such as horizontal stripes appearing on the imaging screen due to such noise.

  In the present embodiment, the vertical scanning circuit 110a has a simple switch 120a and a delay circuit 111 added thereto, so that the layout area of the solid-state imaging device hardly increases.

  In the first and second embodiments, the pixel has a four-transistor configuration. However, the pixel may have a three-transistor configuration that does not include a transfer transistor.

In this case, the timing for reading the signal level of the charge storage unit FD is the timing immediately before the rise of the reset signal RST, and the timing for reading the reset level of the charge storage unit FD is the timing immediately after the fall of the reset signal. . Accordingly, in this case, the switch circuit 120 or 120a has an off period that includes at least a signal level read timing immediately before the reset signal RST rising and a reset level read timing immediately after the reset signal RST falling. Must be set. Also in such a three-transistor pixel, the serially connected selection transistor and amplification transistor connected between the AVDD power supply and the output signal line may be any transistor connected to the power supply side. That is, the selection transistor may be connected to the power supply side and the amplification transistor may be connected to the output signal line side, or the amplification transistor may be connected to the power supply side and the selection transistor connected to the output signal line side.
(Embodiment 3)
Although not particularly described in the first and second embodiments, a digital camera such as a digital video camera or a digital still camera using at least one of the solid-state imaging devices of the first and second embodiments as an imaging unit, An electronic information device having an image input device such as an image input camera, a scanner, a facsimile, a camera-equipped mobile phone device, and the like will be described. The electronic information device of the present invention performs data recording after performing predetermined signal processing for recording high-quality image data obtained by using at least one of the solid-state imaging devices of the first and second embodiments of the present invention as an imaging unit. A memory unit such as a recording medium, a display unit such as a liquid crystal display device that displays the image data on a display screen such as a liquid crystal display screen after performing predetermined signal processing for display, and the image data for communication At least one of communication means such as a transmission / reception device that performs communication processing after the signal processing and image output means for printing (printing) and outputting (printing out) the image data.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range from the description of specific preferred embodiments of the present invention based on the description of the present invention and common general technical knowledge. It is understood that the patent documents cited in the present specification should be incorporated by reference into the present specification in the same manner as the content itself is specifically described in the present specification.

  The present invention can improve the adverse effect of noise applied to the power supply of a solid-state image pickup device on an output signal in the field of solid-state image pickup devices and electronic information devices, and is equipped with a solid-state image pickup device such as a CMOS image sensor. The present invention can be applied to electronic information devices such as electronic imaging devices such as video cameras and digital cameras.

FIG. 1 is a diagram illustrating a solid-state imaging device according to Embodiment 1 of the present invention. A circuit configuration of one pixel in a pixel array constituting the solid-state imaging device and a vertical scanning circuit (DECV) corresponding to one pixel row. Circuit). FIG. 2 is a waveform diagram for explaining the operation of the CMOS image sensor (solid-state imaging device) 100 according to the first embodiment. FIG. 3 illustrates a simulation result in which a sine wave noise is superimposed on the pixel power supply AVDD, which affects the selection signal SEL, and the signal Nfd of the charge storage unit FD fluctuates as an effect of the solid-state imaging device according to the first embodiment. FIG. 6 is a diagram illustrating a potential change of the charge storage unit FD (FIG. (A)), a waveform of the reset signal RST (FIG. (B)), a waveform of the selection signal SEL (FIG. (C)), and a waveform of the transfer signal TX (FIG. (D)) is shown. FIG. 4 is a diagram for explaining a solid-state imaging device according to Embodiment 2 of the present invention. A circuit configuration of one pixel in a pixel array constituting the solid-state imaging device and a vertical scanning circuit (DECV) corresponding to one pixel row. Circuit). FIG. 5 is a block diagram showing the overall configuration of a conventional CMOS image sensor. FIG. 6 is a diagram showing a circuit configuration of one pixel in a pixel array constituting this conventional CMOS image sensor and a circuit configuration of a vertical scanning circuit (DECV circuit) corresponding to one pixel row. FIG. 7 is a waveform diagram for explaining the operation of this CMOS image sensor. FIG. 8 is a diagram illustrating a simulation result in which a sine wave noise is superimposed on the pixel power supply AVDD in the conventional CMOS image sensor, which affects the selection signal SEL, and the signal Nfd of the charge storage unit FD fluctuates. The potential change of the storage unit FD (FIG. (A)), the waveform of the reset signal RST (FIG. (B)), the waveform of the selection signal SEL (FIG. (C)), and the waveform of the transfer signal TX (FIG. (D)). Show.

Explanation of symbols

100, 100a Solid-state imaging device 110, 110a Vertical scanning circuit (DECV circuit)
111 Delay circuit 120, 120a Switch circuit 220 Horizontal scanning circuit
Atr Amplifying transistor Rtr Reset transistor Str Select transistor Ttr Transfer transistor

Claims (24)

A pixel array in which a plurality of pixels are arranged, an output signal line provided for each pixel column in the pixel array, and outputting a signal level obtained from the pixels in the pixel column, and for each pixel row in the pixel array A solid-state imaging device provided with a selection signal line for selecting the pixel row,
A vertical scanning circuit for driving a selection signal line of the specific pixel row by a power supply voltage so that the specific pixel row is selected based on the selection control signal;
A horizontal scanning circuit that reads a signal level output to the output signal line and outputs a pixel signal;
The vertical scanning circuit outputs the signal level of the specific pixel row to the selection signal line at a level reading timing when the signal level of the output signal line is read by the horizontal scanning circuit after the specific pixel row is selected. A solid-state imaging device configured to cut off the supply of power supply voltage. The vertical scanning circuit includes:
A signal line driving circuit which is supplied with the power supply voltage and drives the selection signal line based on the selection control signal;
A switch circuit provided between the signal line driving circuit and a power supply for supplying the power supply voltage;
2. The solid-state imaging device according to claim 1, wherein after the specific pixel row is selected, the switch circuit is controlled so that a selection signal line of the specific pixel row is in a floating state at the level reading timing. The vertical scanning circuit includes:
A delay circuit for delaying the selection control signal;
The solid-state imaging device according to claim 2, wherein the switch circuit is controlled by an output of the delay circuit.   The solid-state imaging device according to claim 3, wherein the delay circuit includes a multistage-connected inverter circuit, and the number of stages of the inverter circuit is set by an external setting signal. The switch circuit is a P-channel transistor connected between the power source and the signal line driver circuit,
The solid-state imaging device according to claim 3, wherein an output of the delay circuit is connected to a gate of the P-channel transistor.   The solid-state imaging device according to claim 3, wherein the signal line drive circuit is an inverter circuit having a CMOS configuration. The pixel is
A photoelectric conversion unit that generates a signal charge according to the amount of received light by photoelectric conversion of incident light; and
A charge storage section for storing the signal charge;
A transfer transistor for transferring the signal charge from the photoelectric conversion unit to the charge storage unit;
A reset transistor for resetting signal charges accumulated in the charge accumulation unit;
An amplification transistor that amplifies the signal level of the charge storage unit and outputs the amplified signal level to the output signal line;
The solid-state imaging device according to claim 2, further comprising: a selection transistor controlled to supply the power supply voltage to the amplification transistor by the selection signal line. The pixel is
A photoelectric conversion unit that generates a signal charge according to the amount of received light by photoelectric conversion of incident light; and
A charge storage section for storing the signal charge;
A transfer transistor for transferring the signal charge from the photoelectric conversion unit to the charge storage unit;
A reset transistor for resetting signal charges accumulated in the charge accumulation unit;
An amplification transistor that is supplied with the power supply voltage and amplifies and outputs the signal level of the charge storage unit;
3. A selection transistor connected between the amplification transistor and the output signal line, and controlled by the selection signal line to output a signal level amplified by the amplification transistor to the output signal line. The solid-state imaging device described in 1. The horizontal scanning circuit reads a reset level of the charge storage unit when the signal charge stored in the charge storage unit is reset, and transfers the signal charge from the photoelectric conversion unit to the charge storage unit after the reset. And a difference circuit that reads out the signal charge level of the charge storage unit when output, and outputs a difference between the reset level and the signal charge level as a pixel signal,
The vertical scanning circuit includes a reset level reading timing at which the reset level of the output signal line is read by the horizontal scanning circuit after the specific pixel row is selected, and the output signal line of the horizontal scanning circuit. 9. The power supply voltage supply to a selection signal line of the specific pixel row is cut off during a period including a signal charge level reading timing at which a signal charge level is read. Solid-state imaging device. The pixel is
A photoelectric conversion unit that generates a signal charge according to the amount of received light by photoelectric conversion of incident light; and
A charge storage section for storing the signal charge;
A reset transistor for resetting signal charges accumulated in the charge accumulation unit;
An amplification transistor that amplifies the signal level of the charge storage unit and outputs the amplified signal level to the output signal line;
The solid-state imaging device according to claim 2, further comprising: a selection transistor controlled to supply the power supply voltage to the amplification transistor by the selection signal line. The pixel is
A photoelectric conversion unit that generates a signal charge according to the amount of received light by photoelectric conversion of incident light; and
A charge storage section for storing the signal charge;
A reset transistor for resetting signal charges accumulated in the charge accumulation unit;
An amplification transistor that is supplied with the power supply voltage and amplifies and outputs the signal level of the charge storage unit;
3. A selection transistor connected between the amplification transistor and the output signal line, and controlled by the selection signal line to output a signal level amplified by the amplification transistor to the output signal line. The solid-state imaging device described in 1. The horizontal scanning circuit includes a reset level of the charge storage unit when the signal charge stored in the charge storage unit is reset, and a signal charge from the photoelectric conversion unit before the reset is input to the charge storage unit. It has a difference circuit that reads out the signal charge level of the charge storage unit in the accumulated state and outputs the difference between the reset level and the signal charge level as a pixel signal,
The vertical scanning circuit includes a signal charge level reading timing at which a signal charge level of the output signal line is read by the horizontal scanning circuit after the specific pixel row is selected, and the output signal by the horizontal scanning circuit. 12. The solid-state imaging device according to claim 10, wherein supply of a power supply voltage to the selection signal line is cut off during a period including a reset level reading timing at which a line reset level is read. The vertical scanning circuit includes:
A signal line driving circuit which is supplied with the power supply voltage and drives the selection signal line based on the selection control signal;
A switch circuit provided between the signal line drive circuit and the selection signal line,
2. The solid-state imaging device according to claim 1, wherein after the specific pixel row is selected, the switch circuit is controlled so that a selection signal line of the specific pixel row is in a floating state at the level reading timing. The vertical scanning circuit includes:
A delay circuit for delaying the selection control signal;
The solid-state imaging device according to claim 13, wherein the switch circuit is controlled by an output of the delay circuit.   The solid-state imaging device according to claim 14, wherein the delay circuit includes a multistage-connected inverter circuit, and the number of stages of the inverter circuit is set by an external setting signal. The switch circuit is a transfer gate that is connected between the signal line drive circuit and the selection signal line and includes a P-channel transistor and an N-channel transistor connected in parallel.
The solid-state imaging device according to claim 14, wherein an output of the delay circuit is connected to gates of the two transistors.   The solid-state imaging device according to claim 14, wherein the signal line drive circuit is an inverter circuit having a CMOS configuration. The pixel is
A photoelectric conversion unit that generates a signal charge according to the amount of received light by photoelectric conversion of incident light; and
A charge storage section for storing the signal charge;
A transfer transistor for transferring the signal charge from the photoelectric conversion unit to the charge storage unit;
A reset transistor for resetting signal charges accumulated in the charge accumulation unit;
An amplification transistor that amplifies the signal level of the charge storage unit and outputs the amplified signal level to the output signal line;
The solid-state imaging device according to claim 13, further comprising: a selection transistor controlled to supply the power supply voltage to the amplification transistor by the selection signal line. The pixel is
A photoelectric conversion unit that generates a signal charge according to the amount of received light by photoelectric conversion of incident light; and
A charge storage section for storing the signal charge;
A transfer transistor for transferring the signal charge from the photoelectric conversion unit to the charge storage unit;
A reset transistor for resetting signal charges accumulated in the charge accumulation unit;
An amplification transistor that is supplied with the power supply voltage and amplifies and outputs the signal level of the charge storage unit;
14. A selection transistor connected between the amplification transistor and the output signal line and controlled by the selection signal line to output a signal level amplified by the amplification transistor to the output signal line. The solid-state imaging device described in 1. The horizontal scanning circuit reads a reset level of the charge storage unit when the signal charge stored in the charge storage unit is reset, and transfers the signal charge from the photoelectric conversion unit to the charge storage unit after the reset. And a difference circuit that reads out the signal charge level of the charge storage unit when output, and outputs a difference between the reset level and the signal charge level as a pixel signal,
The vertical scanning circuit includes a reset level reading timing at which the reset level of the output signal line is read by the horizontal scanning circuit after the specific pixel row is selected, and the output signal line of the horizontal scanning circuit. 20. The power supply voltage supply to the selection signal line of the specific pixel row is cut off during a period including a signal charge level reading timing at which a signal charge level is read. Solid-state imaging device. The pixel is
A photoelectric conversion unit that generates a signal charge according to the amount of received light by photoelectric conversion of incident light; and
A charge storage section for storing the signal charge;
A reset transistor for resetting signal charges accumulated in the charge accumulation unit;
An amplification transistor that amplifies the signal level of the charge storage unit and outputs the amplified signal level to the output signal line;
The solid-state imaging device according to claim 13, further comprising: a selection transistor controlled to supply the power supply voltage to the amplification transistor by the selection signal line. The pixel is
A photoelectric conversion unit that generates a signal charge according to the amount of received light by photoelectric conversion of incident light; and
A charge storage section for storing the signal charge;
A reset transistor for resetting signal charges accumulated in the charge accumulation unit;
An amplification transistor that is supplied with the power supply voltage and amplifies and outputs the signal level of the charge storage unit;
14. A selection transistor connected between the amplification transistor and the output signal line and controlled by the selection signal line to output a signal level amplified by the amplification transistor to the output signal line. The solid-state imaging device described in 1. The horizontal scanning circuit includes a reset level of the charge storage unit when the signal charge stored in the charge storage unit is reset, and a signal charge from the photoelectric conversion unit before the reset is input to the charge storage unit. It has a difference circuit that reads out the signal charge level of the charge storage unit in the accumulated state and outputs the difference between the reset level and the signal charge level as a pixel signal,
The vertical scanning circuit includes a signal charge level reading timing at which a signal charge level of the output signal line is read by the horizontal scanning circuit after the specific pixel row is selected, and the output signal by the horizontal scanning circuit. 24. The solid-state imaging device according to claim 22, wherein the supply of the power supply voltage to the selection signal line is cut off during a period including a reset level reading timing at which a reset level of the line is read. An electronic information device having an imaging unit for imaging a subject,
The electronic information device which is the solid-state imaging device according to any one of claims 1 to 23.

Images