JP6731731B2 - Solid-state imaging device, driving method thereof, and electronic device - Google Patents

Description

The present invention relates to a solid-state imaging device, a driving method thereof, and electronic equipment.

A CMOS (Complementary Metal Oxide Semiconductor) image sensor has been put to practical use as a solid-state imaging device (image sensor) using a photoelectric conversion element that detects light and generates electric charges.
The CMOS image sensor is widely applied as a part of various electronic devices such as a digital camera, a video camera, a surveillance camera, a medical endoscope, a personal computer (PC), and a mobile terminal device (mobile device) such as a mobile phone. There is.

The CMOS image sensor has a FD amplifier having a photodiode (photoelectric conversion element) and a floating diffusion layer (FD: Floating Diffusion) for each pixel, and for reading the FD amplifier, one row in the pixel array is selected. However, a column parallel output type is the mainstream in which they are simultaneously read out in the column direction.

By the way, as a pixel configuration of a solid-state imaging device (CMOS image sensor), for example, for one photodiode (photoelectric conversion element), a transfer transistor as a transfer element, a reset transistor as a reset element, and a source follower element are provided. A pixel having a four-transistor (4Tr) configuration having one source follower transistor and one selection transistor as a selection element can be exemplified.

The transfer transistor is selected in a predetermined transfer period to be in a conductive state, and transfers charges (electrons) photoelectrically converted and accumulated by the photodiode to the floating diffusion FD.
The reset transistor is selected in a predetermined reset period to be in a conductive state, and resets the floating diffusion FD to the potential of the power supply line.
The selection transistor is selected and becomes conductive during the read scan. As a result, the source follower transistor outputs a column output read signal obtained by converting the charge of the floating diffusion FD into a voltage signal with a gain according to the charge amount (potential) to the vertical signal line.

For example, in the read scan period, after the floating diffusion FD is reset to, for example, the potential of the power supply line (reference potential) in the reset period, the charge of the floating diffusion FD is converted to a voltage with a gain according to the amount of charge (potential) by the source follower transistor. It is converted into a signal and output to the vertical signal line as a read reset voltage (reference level signal) Vrst of the reference level.
Subsequently, during a predetermined transfer period, the charges (electrons) photoelectrically converted and accumulated by the photodiode are transferred to the floating diffusion FD. Then, the charge of the floating diffusion FD is converted into a voltage signal by the source follower transistor with a gain corresponding to the charge amount (potential), and is output to the vertical signal line as a read signal voltage (signal level signal) Vsig of the signal level. ..
The output signal of the pixel is processed as a difference signal (Vsig-Vrst).

As described above, the normal pixel read signal (hereinafter, also referred to as a pixel signal) PS is formed by the read reset voltage Vrst having one reference level and the read signal voltage Vsig having one signal level.

In order to improve the characteristics, various methods have been proposed for realizing a high image quality solid-state imaging device (CMOS image sensor) having a high dynamic range (HDR).

As a method of increasing (enlarging) the dynamic range in a solid-state imaging device, for example, two kinds of signals having different storage times are read out from the same pixel of the image sensor, and the two kinds of signals are combined (combined). , A method of expanding the dynamic range, a method of combining (combining) the signals of the low illuminance area obtained by the high sensitivity pixel and the signals of the high illuminance area obtained by the low sensitivity pixel to expand the dynamic range, etc. It has been known.

For example, Patent Document 1 discloses a high dynamic range technology that divides into two or more different exposure times, one for high illuminance due to short exposure time and the other for low illuminance due to long exposure time. ..

Pixel read signals (pixel signals) PSD in the case of adopting this high dynamic range technology are read reset voltages (reference level signals) Vrst of a plurality of M (for example, M=2) and M (M=2). ) Signal level read signal voltage (signal level signal) Vsig.
The pixel read signal (pixel signal) PSD in this case is processed as a so-called uninterrupted read signal.

1A and 1B show a normal pixel read signal (pixel signal) of a solid-state image pickup device (CMOS image sensor) and a pixel read signal without interruption (adjacent pixel) when a high dynamic range technology is adopted. It is a figure which shows an example of a (pixel signal).
FIG. 1A shows an example of a normal pixel readout signal (pixel signal) PS, and FIG. 1B shows an example of an uninterrupted pixel readout signal (uninterrupted pixel signal) PSD.

As shown in FIG. 1A, the normal pixel signal PS[N] includes one reference level signal (hereinafter, also simply referred to as reference level) Vrst[N] and one signal level signal ( Hereinafter, it may be simply referred to as a signal level) Vsig[N].
That is, one pixel signal PS[N] includes one reference level Vrst[N] and one signal level Vsig[N].
The output data OD[N] in this case becomes the reference level Vrst[N]-signal level Vsig[N].
Similarly, one pixel signal PS[N+1] includes one reference level Vrst[N+1] and one signal level Vsig[N+1].
The output data OD[N+1] in this case becomes the reference level Vrst[N+1]−signal level Vsig[N+1].

As shown in FIG. 1B, the uninterrupted pixel signal PSD[N] has M (M=2 in this example) reference levels Vrst[N, 1] in one pixel signal PSD[N]. , Vrst[N, 2] and M signal levels Vsig[N, 1] and Vsig[N, 2].
That is, in one uninterrupted pixel signal PSD[N], M reference levels Vrst[N,1] and Vrst[N,2] and M signal levels Vsig[N,1] and Vsig[N]. , 2] are included.
In this case, the output data OD[N,1] becomes the reference level Vrst[N,1]-signal level Vsig[N,1], and the output data OD[N,2] is the reference level Vrst[N,2]. The signal level is Vsig[N,2].
Similarly, in one uninterrupted pixel signal PSD[N+1], M reference levels Vrst[N+1,1], Vrst[N+1,2] and M signal levels Vsig[N+1,1], Vsig[ N+1, 2] are included.
In this case, the output data OD[N+1,1] becomes the reference level Vrst[N+1,1]-signal level Vsig[N+1,1], and the output data OD[N+1,2] becomes the reference level Vrst[N+1,2]. -The signal level becomes Vsig [N+1, 2].

Thus, the pixel signal PSD without interruption includes M reference levels Vrst and M signal levels Vsig in one pixel signal PSD, and the arrangement order thereof is one output data OD[N. , M], the reference levels Vrst[N, M] are always input first, and then the signal levels Vsig[N, M] are input.
FIG. 1(B) shows M=2 and one of the possible arrangements.

FIG. 2 illustrates a method of increasing (expanding) the dynamic range in a solid-state imaging device, and a method of combining pixel signals without interruption when the number M of read signals to be combined is 2 (M=2). FIG.

The uninterrupted pixel signal PSD may have M signals having different amplification factors K for the same light amount.
FIG. 2 is an example in which M=2 and the amplification factor ratio K(M=1)/K(M=2)=4.

The output data OD[*,1] and OD[*,2] obtained from the uninterrupted pixel signal PSD shown in FIG. 1(B) are signals having different inclinations as shown in FIG. 2(A). ..
In the combining process, the output data OD[*,2] is amplified according to the ratio, and one combined final output data ODA is obtained as shown in FIG. 2(B).

As the synthesizing method, the first method by switching shown in FIG. 2C or the second method by averaging shown in FIG. 2D is adopted, and the final output data ODA is obtained.

For this reason, conventionally, the first method emphasizes the boundary (coupling position (point)) [X] at which the error is noticeable, and the second method for alleviating the error always requires two output data OD[* , 1] and OD[*, 2] are required, further complicating the signal processing.

Hereinafter, a configuration for reducing (eliminating) individual variations and the like in a circuit system that processes pixel readout signals (pixel signals) will be described.
Here, description will be made in relation to a configuration for generating output data for a normal pixel signal.

FIG. 3 is a diagram showing an example of a read circuit including a new reference level setting function in a normal pixel read signal (pixel signal) processing system.
In FIG. 3, pixels PXL(N) and PXL(N+1) in the same column are connected to a common read signal line LS. A clamp circuit 1 for setting a new reference level is arranged at an input stage between the signal line LS and an input node [Y] of an analog digital converter (ADC) not shown.
The clamp circuit 1 includes an amplifier AMP1, capacitors C1 and C2, and a switch SW1.

For example, in the processing of the normal pixel read signal (pixel signal) PS shown in FIG. 1A, the reference level Vrst[N] and the reference level Vrst[N+1] may have different levels due to individual variation of the pixel PXL.
Therefore, in the example of FIG. 3, the individual variation of the pixel is eliminated by using the new reference level [V1] by the clamp circuit 1 inside the readout circuit.

FIG. 4 is a diagram showing an example of a normal pixel read signal (pixel signal) when a new reference level Vrst[V1] by the clamp circuit 1 is applied.
FIG. 4A shows the clamp circuit of FIG. 3 in a simplified manner with a capacitor C and a switch SW1, and FIG. 4B shows an example of a normal pixel read signal (pixel signal).

As shown in FIG. 4, by turning on the switch SW1 by the clamp signal CLP in the clamp circuit 1, the reference level Vrst appearing at the node [Y] is changed using the new reference level [V1].
At this time, the signal level Vsig[N] becomes a new signal level Vsig[N′] based on the new reference level [V1].
Even in this case, the difference between the reference level [V1] and the signal level Vsig[N'] is constant.

FIG. 5 is a diagram for explaining a configuration for deleting individual variations occurring in the ADC.
5A shows an example of a state of AD conversion and output processing of a normal pixel read signal (pixel signal), and FIG. 5B shows a configuration example of a column parallel processing unit including an ADC. ..

In the readout circuit of the column parallel output type solid-state imaging device, as shown in FIG. 5B, ADCs 2 are arranged in each column corresponding to the column output of the pixel portion, and a switch is provided on the output side of each ADC 2. A holding unit 3-1 that holds the reference level Vrst and a holding unit 3-2 that holds the signal level Vsig are arranged via the SW3-1 and the SW3-2, and further, an operation for obtaining the difference between the signal level Vsig and the reference level Vrst The container 4 is arranged.

In column parallel reading, individual variations also occur in the ADC.
Therefore, the reference level [V1] and the signal level Vsig[N'] generated at the input node [Y] of FIG. 4A are AD-converted by the ADC2, respectively, and one output data OD[N] is obtained by digital operation processing. ] Is generated.
As a result, individual variations of ADC2 are deleted.

FIG. 6 is a diagram showing an example of a column reading system having a configuration for eliminating individual variation corresponding to a pixel reading signal without interruption (pixel signal without interruption).
FIG. 7 is a diagram showing an example of a state of AD conversion processing of a pixel readout signal without interruption (pixel signal without interruption).

In the readout circuit of FIG. 6, ADC 2A is arranged in each column corresponding to the column output of the pixel portion, and the reference level Vrst and the signal level Vsig are provided on the output side of the ADC 2A via the switches SW3-1 to SW3-2M. The holding units 3-1 to 3-2M for holding are arranged, and the combining processing unit 5 for combining the signals held in the holding units 3-1 to 3-2M is arranged.

The ADC 2A is configured to include the clamp circuit 1A having the same configuration as that of FIG. 4A and the conversion unit 2-1 connected to the input node [Y].

Patent No. 3984814

However, the above-mentioned read system of FIG. 6 has the following three main disadvantages.

First, as can be seen from FIG. 6, the reading system in FIG. 6 requires 2M holding units for M unbroken pixel signals. Further, this requires the AD conversion operation 2M times, which disadvantageously increases the circuit area and the processing time.

As the second disadvantage, M=2 will be described as an example in association with FIG. 7.
The clamp operation is desired to be performed twice within the same pixel signal, but if the clamp operation is performed at the reference level Vrst[N,2], the state at the first reference level Vrst[N,1] is lost. That is, the clamping operation can be performed only once.
Therefore, the reading system of FIG. 6 deteriorates AD conversion accuracy.

The third disadvantage lies in the composition process.
As described above, as the synthesizing method, the first method by switching shown in FIG. 2C or the second method by averaging processing shown in FIG. 2D is adopted. In the signal processing for combining, the second method is superior to the first method, but the second method is complicated in processing, and thus the processing time increases.

INDUSTRIAL APPLICABILITY The present invention can prevent deterioration of AD conversion accuracy while suppressing an increase in circuit area and processing time, and can realize a wide dynamic range, which in turn can realize high image quality. Another object of the present invention is to provide a solid-state imaging device, a driving method thereof, and an electronic device.

A first aspect of the present invention is a solid-state imaging device capable of expanding a dynamic range by combining a plurality of read signals, the pixel unit having pixels arranged therein, and the solid-state imaging device arranged corresponding to a column output of the pixel unit. And a read-out section including a column signal processing section, wherein the column signal processing section converts the plurality of read signals read from the pixels and input to the input node into analog signals from analog signals to digital signals. An analog-to-digital converter (ADC) for (AD) conversion is compared with a level of the input node to which the read signal read from the pixel is input and a preset reference voltage, and the reference voltage is set according to a comparison result. A comparison and selection unit that selects an input state of the read signal read from the pixel to the input node.

A second aspect of the present invention includes a pixel section in which pixels are arranged, and a reading section including a column signal processing section arranged corresponding to a column output of the pixel section, and the column signal processing section. is the plurality of read signals input to the input node read from the pixels includes an analog-to-digital converter (ADC) for analog-digital (AD) converted from an analog signal to a digital signal, synthesizing a plurality of read signals And a method of driving a solid-state imaging device capable of expanding a dynamic range, wherein a level of the input node to which the read signal read from the pixel is input is preset in AD conversion of the ADC. The reference voltage is compared, and the input state of the read signal read from the pixel to the input node is selected according to the comparison result.

An electronic apparatus according to a third aspect of the present invention includes a solid-state imaging device capable of expanding a dynamic range by combining a plurality of read signals, and an optical system for forming a subject image on the solid-state imaging device. The solid-state imaging device includes a pixel section in which pixels are arranged, and a reading section including a column signal processing section arranged corresponding to a column output of the pixel section, wherein the column signal processing section is the An analog-digital converter (ADC) that converts the plurality of read signals read from the pixels and input to the input node into an analog-digital (AD) signal from an analog signal, and the read signal read from the pixels A comparison and selection unit that compares the level of the input node that is input with a preset reference voltage, and selects the input state of the read signal read from the pixel to the input node according to the comparison result; ,including.

According to the present invention, it is possible to prevent the deterioration of the AD conversion accuracy while suppressing the increase of the circuit area and the processing time, and also to realize the wide dynamic range and the high image quality. You can

It is a figure which shows an example of a normal pixel read-out signal (pixel signal) of a solid-state imaging device (CMOS image sensor), and an uninterrupted pixel read-out signal (uninterrupted pixel signal) in the case of adopting the high dynamic range technology. FIG. 3 is a diagram for explaining a method of increasing (enlarging) a dynamic range in a solid-state imaging device, which is a method for combining pixel signals without interruption when the number M of read signals to be combined is 2 (M=2). Is. It is a figure which shows an example of the read-out circuit containing the setting function of the new reference level in the normal pixel read-out signal (pixel signal) processing system. It is a figure which shows an example of the normal pixel read-out signal (pixel signal) at the time of applying a new reference level by a clamp circuit. It is a figure for explaining the composition which deletes the individual variation which occurs in ADC. It is a figure showing an example of a column read-out system which has a composition which removes individual variation corresponding to a pixel read-out signal without a break (pixel signal without a break). It is a figure which shows an example of a mode of AD conversion processing of a pixel read signal without a discontinuity (pixel signal without a discontinuity). It is a block diagram which shows the structural example of the solid-state imaging device which concerns on the 1st Embodiment of this invention. It is a circuit diagram which shows an example of the pixel which concerns on the 1st Embodiment of this invention. It is a figure for explaining an example of composition of a read-out system of column output of a pixel part of a solid-state image sensing device concerning an embodiment of the present invention. Configuration example of an ADC forming a column output readout system of the pixel unit of the solid-state imaging device according to the first embodiment of the present invention, a comparison selection unit, and a holding unit arranged on the output side of the ADC and a synthesis processing unit FIG. FIG. 12 is a diagram for explaining the operation of the circuit of FIG. 11 when the number M of read signals to be combined is 2 (M=2). FIG. 6 is a diagram for explaining a method of increasing (enlarging) a dynamic range in a solid-state imaging device, which is a method for combining pixel signals without interruption when the number M of read signals to be combined is 4 (M=4). Is. FIG. 12 is a diagram for explaining the operation of the circuit of FIG. 11 when the number M of read signals to be combined is 4 (M=4). It is a figure which shows the structural example of the clamp circuit arrange|positioned at the input part of ADC which forms the read-out system of the column output of the pixel part of the solid-state imaging device concerning the 2nd Embodiment of this invention. 16 is a diagram showing an operation example of the circuit of FIG. 15. FIG. It is a figure which shows the structural example of the clamp circuit and comparison selection part arrange|positioned at the input part of ADC which form the read-out system of the column output of the pixel part of the solid-state imaging device concerning the 3rd Embodiment of this invention. FIG. 18 is a diagram showing an operation example of the circuit of FIG. 17. Configuration example of an ADC forming a readout system of a column output of a pixel unit of a solid-state imaging device according to a fourth embodiment of the present invention, a comparison selection unit, and a holding unit arranged on the output side of the ADC and a synthesis processing unit FIG. It is a figure which shows an example of a structure of the electronic device to which the solid-state imaging device which concerns on embodiment of this invention is applied.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 8 is a block diagram showing a configuration example of the solid-state imaging device according to the first embodiment of the present invention.
In the present embodiment, the solid-state imaging device 10 is composed of, for example, a CMOS image sensor.

As shown in FIG. 8, the solid-state imaging device 10 includes a pixel unit 20 as an imaging unit, a vertical scanning circuit (row scanning circuit) 30, a readout circuit (column readout circuit) 40, and a horizontal scanning circuit (column scanning circuit) 50. , A timing control circuit 60, and a digital signal processor (DSP) unit 70 having a function as a signal synthesis processing unit, for example, as main components.
Of these components, for example, the vertical scanning circuit 30, the readout circuit 40, and the timing control circuit 60 constitute a pixel signal readout unit 80.

In the present embodiment, the solid-state imaging device 10 is configured to combine a plurality of (M) read signals (pixel signals) read from the pixel unit 20 to expand the dynamic range, as described later in detail. There is.

As a method of increasing (enhancing) the dynamic range, the reading unit 80 reads, for example, a plurality of M (for example, M=2) types of signals having different storage times from the same pixel of the image sensor, and outputs the M types of signals. A method of combining (combining) and expanding the dynamic range is applied.
Further, the reading unit 80 applies a method of expanding (combining) the dynamic range by combining (combining) the signal in the low illuminance region obtained by the high sensitivity pixel and the signal in the high illuminance region obtained by the low sensitivity pixel It is possible.

In the present embodiment, the pixel read signal (pixel signal) PSD when this high dynamic range technology is adopted is a read reset voltage (reference level of the reference level) of a plurality M (M=2, 4,... ). Signal) Vrst and a plurality of M read signal voltages (signal level signals) Vsig having signal levels.
The pixel read signal (pixel signal) PSD in this case is processed as a so-called uninterrupted read signal.

As described above, in the present embodiment, the pixel signal PSD without interruption includes M reference levels (reference level signals) Vrst and M signal levels (signal level signals) Vsig in one pixel signal PSD. include.
In the present embodiment, the arrangement order of the uninterrupted pixel signals PSD is, for example, the signal level Vsig[ after the reference level Vrst[N,M] forming one output data OD[N,M] is always input first. N, M] exist and there are a plurality of them, with the constraint that they are input.

The readout unit 80 includes a plurality of column signal processing units arranged corresponding to the column output of the pixel unit 20, and each column signal processing unit outputs a plurality of readout signals read from pixels from analog signals. It includes an ADC (analog-digital converter) for AD (analog-digital) conversion into a digital signal.
The readout unit 80 compares the input node [Y] to which each readout signal read out from the pixel is input, the level of the input node [Y], and a preset reference voltage [V20], and obtains the comparison result. And a comparison/selection unit that selects the input state of the read signal read from the pixel to the input node [Y].
To the ADC, for example, the reference level signal Vrst is input first, and then the signal level signal Vsig is input.
Then, the comparison/selection unit compares the signal level of the input node [Y] with the preset reference voltage V[20] when the signal of the signal level appears at the input node [Y], and compares The input state of the read signal read from the pixel to the input node [Y] is selected according to the result.

In the present embodiment, as will be specifically described later, when the level of the input node [Y] is higher (or lower) than the reference voltage [V20], the comparison/selection unit reads out the read signal of the current comparison target. Then, the state in which the subsequent read signal is continuously input to the input node [Y] is selected, and the subsequent read signal is controlled to be the AD conversion target to be held.
When the level of the input node [Y] is lower (or higher) than the reference voltage V20, the comparison/selection unit selects a state in which no subsequent read signal is input to the current read signal to be compared, The read signal to be compared is configured to be controlled to be an AD conversion target to be held.

Further, as will be described later, the ADC includes a clamp unit that fixes at least a reference level signal first input to the input node [Y] to a clamp level [V10] preset according to the clamp signal CLP. It has a clamp circuit.

Hereinafter, the outline of the configuration and function of each unit of the solid-state imaging device 10 will be described, and then the configuration of the ADC including the clamp circuit and the reading process related thereto will be described in detail.

(Structure of Pixel Unit 20 and Pixel PXL)
In the pixel portion 20, a plurality of pixels including a photodiode (photoelectric conversion element) and an in-pixel amplifier are arranged in a two-dimensional matrix of n rows and m columns.

FIG. 9 is a circuit diagram showing an example of the pixel according to the present embodiment.

This pixel PXL has, for example, a photodiode (PD) which is a photoelectric conversion element.
For this photodiode PD, a transfer transistor TG-Tr as a transfer element, a reset transistor RST-Tr as a reset element, a source follower transistor SF-Tr as a source follower element, and a selection transistor SEL-Tr as a selection element. Have one each.

The photodiode PD generates and accumulates a signal charge (here, an electron) in an amount according to the amount of incident light.
Hereinafter, the case where the signal charge is an electron and each transistor is an n-type transistor will be described, but the signal charge may be a hole or each transistor may be a p-type transistor.
Further, the present embodiment is also effective when a plurality of photodiodes share each transistor or when a three-transistor (3Tr) pixel having no selection transistor is adopted.

The transfer transistor TG-Tr is connected between the photodiode PD and a floating diffusion FD (Floating Diffusion) and is controlled through a control line TG.
The transfer transistor TG-Tr is selected when the control line TG is at a high level (H) and is in a conductive state, and transfers the charges (electrons) photoelectrically converted and accumulated in the photodiode PD to the floating diffusion FD.

The reset transistor RST-Tr is connected between the power supply line VRst and the floating diffusion FD and controlled through the control line RST.
The reset transistor RST-Tr may be connected between the power supply line VDD and the floating diffusion FD and controlled via the control line RST.
The reset transistor RST-Tr is selected and rendered conductive when the control line RST is at the H level, and resets the floating diffusion FD to the potential of the power supply line VRst (or VDD).

The source follower transistor SF-Tr and the selection transistor SEL-Tr are connected in series between the power supply line VDD and the vertical signal line LSGN.
A floating diffusion FD is connected to the gate of the source follower transistor SF-Tr, and the selection transistor SEL-Tr is controlled through the control line SEL.
The select transistor SEL-Tr is selected to be in the conductive state while the control line SEL is at the H level. As a result, the source follower transistor SF-Tr is a signal path for transmitting a pixel output signal (pixel signal) VSL (PSD) of a column output obtained by converting the charge of the floating diffusion FD into a voltage signal with a gain according to the charge amount (potential). Output to the vertical signal line LSGN.
In the present embodiment, the pixel read signal (pixel signal) PSD in this case is processed as a so-called uninterrupted read signal.
These operations are performed simultaneously in parallel for each pixel for one row because, for example, the gates of the transfer transistor TG-Tr, the reset transistor RST-Tr, and the selection transistor SEL-Tr are connected in row units. Be seen.

Since the pixels PXL are arranged in n rows×m columns in the pixel section 20, there are n control lines SEL, RST, and TG, and m vertical signal lines LSGN.
In FIG. 1, each control line SEL, RST, TG is shown as one row scanning control line.

The vertical scanning circuit 30 drives pixels through the row scanning control lines in the shutter row and the reading row under the control of the timing control circuit 60.
Further, the vertical scanning circuit 30 outputs a row selection signal of a row address of a read row for reading a signal and a row address of a shutter row for resetting charges accumulated in the photodiode PD according to the address signal.

Normally, in the pixel reading operation, shutter scanning is performed by driving the vertical scanning circuit 30 of the reading unit 80, and then reading scanning is performed.

The readout circuit 40 includes a plurality of column signal processing units (not shown) arranged corresponding to each column output of the pixel unit 20, and the plurality of column signal processing units are configured to perform column parallel processing.
The read circuit 40 can be configured to include, for example, an ADC and a memory.

As described above, the column signal processing unit 400 of the readout circuit 40 is configured to include the ADC 410 that converts the readout signal VSL of each column output of the pixel unit 20 into a digital signal, as shown in FIG. 10, for example.

The horizontal scanning circuit 50 scans the signals processed by the plurality of column signal processing units such as the ADC of the reading circuit 40, transfers the signals in the horizontal direction, and outputs the signals to the DSP unit 70.

The timing control circuit 60 generates timing signals necessary for signal processing of the pixel unit 20, the vertical scanning circuit 30, the reading circuit 40, the horizontal scanning circuit 50, and the like.

The outline of the configuration and function of each unit of the solid-state imaging device 10 has been described above.
Next, the ADC 410 including the clamp circuit according to the first embodiment, the configurations of the holding unit and the synthesis processing unit arranged on the output side of the ADC 410, and the reading process related thereto will be described in detail.

FIG. 11 illustrates an ADC forming a column output read system of the pixel unit of the solid-state imaging device according to the first embodiment of the present invention, a comparison/selection unit, a holding unit arranged on the output side of the ADC, and a combining process. It is a figure which shows the structural example of a part.

In FIG. 11, one reading system including a column signal processing unit 400 corresponding to one column output of the pixel unit 20 is shown for simplification of the drawing and easy understanding. The readout system including the column signal processing unit 400 corresponding to the other column output of the pixel unit 20 also has the same configuration.

In the reading system of FIG. 11, ADCs 410 are arranged in each column with respect to a vertical signal line LSGN which is a column output line of a pixel portion and which is a signal path, and an AD conversion state of the ADC 410 is selected in parallel with the ADC 410. A comparator 420, which constitutes a part of the comparison/selection unit 430 to be controlled, is arranged.
On the output side of the ADC 410, holding units 440-1 and 440-2 that hold the reference level Vrst and the signal level Vsig via the switches SW440-1 and SW440-2 are arranged, and further holding units 440-1 and 440-. A synthesis processing unit 450 that synthesizes the signals held in No. 2 is arranged.
The synthesis processing unit 450 is arranged in the DSP unit 70, for example.

The ADC 410 has an input node [Y], an input switch (S) 411, a clamp circuit 412, and a conversion unit 413 as main constituent elements.

The ADC 410 AD-converts a plurality of read signals read from the pixels PXL and input to the input node [Y] from analog signals to digital signals.

As described above, each of the plurality of read signals is formed of the reference level signal and the signal level signal, and the ADC 410 is input with the reference level signal Vrst first and then with the signal level signal Vsig. It

The input switch 411 has a connection state (on state) and a non-connection state (off state) of the signal path to the input node [Y] of the read signal read from the pixel PXL according to the signal S420 indicating the comparison result of the comparator 420. State).
The input switch 411 and the comparator 420 form a comparison/selection unit 430.

The clamp circuit 412 includes a clamp unit 412A that fixes at least the reference level signal Vrst that is first input to the input node [Y] to a clamp level [V10] preset according to the clamp signal CLP.
As shown in FIG. 3, the clamp circuit 412 includes an amplifier AMP1, capacitors C1 and C2, and a switch SW1.
The clamp circuit 412 of FIG. 11 shows the clamp circuit of FIG. 3 in a simplified manner with the capacitor C11 and the switch SW11, and the clamp unit 412A is composed of the capacitor C11 and the switch SW11.

In the ADC 410, the clamp circuit 412 turns on the switch SW11 by the clamp signal CLP to change the reference level Vrst appearing at the node [Y] using the new reference level [V10].
At this time, the signal level Vsig[N] becomes a new signal level Vsig[N′] based on the new reference level [V10].
In this case, the difference between the reference level [V10] and the signal level Vsig[N'] is constant.

The conversion unit 413 AD-converts a plurality of read signals read from the pixels PXL and input to the input node [Y] from analog signals to digital signals.

The comparator 420 constitutes the comparison/selection unit 430 together with the input switch 411.
When the signal Vsig of the signal level appears at the force node [Y], the comparator 420 constituting the comparison/selection unit 430 outputs the signal level of the input node [Y] and the preset reference voltage [V20]. And the signal S420 corresponding to the comparison result is used to control ON/OFF switching of the input switch 411 so that the input state of the read signal read from the pixel to the input node is selected.

In the present embodiment, the reference voltage [V20] is a level (for example, the coupling position X in FIG. 2B) corresponding to the coupling position of the plurality of read signals to be combined.

For example, when the level of the input node [Y] is higher than the reference voltage [V20], the comparison and selection unit 430 continuously inputs the subsequent read signal to the read signal of the current comparison target to the input node [Y]. Is selected and controlled so that the subsequent read signal becomes an AD conversion target to be held.
In this case, the output signal S420 of the comparator 420 becomes "1", for example, and the input switch 411 is controlled to be in the ON state (connection state).

For example, when the level of the input node [Y] is lower than the reference voltage V20, the comparison/selection unit 430 selects a state in which no subsequent read signal is input to the input node [Y] to the read signal of the current comparison target, The read signal of the current comparison target is controlled to be the AD conversion target to be held.
In this case, the output signal S420 of the comparator 420 becomes "0", for example, and the input switch 411 is controlled to the off state (non-connection state).

The holding units 440-1 and 440-2 are connected in parallel to the output of the ADC 410 via the switches SW440-1 and SW440-2, and select the reference level signal or the signal level signal AD-converted by the ADC 410. Retained,
At least one of the holding units 440-1 and 440-2 is configured to be overwritable during ADC conversion processing by the ADC 410.
The number of holding units is set to a number smaller than 2M, which is twice the number of read signals to be combined with two or more. In the present embodiment, the minimum two holding units 440-1 and 440-2 are arranged.

The synthesis processing unit 450 synthesizes the digital signals held in the plurality of holding units 440-1 and 440-2 to generate output data OD.

FIG. 12 is a diagram for explaining the operation of the circuit of FIG. 11 when the number M of read signals to be combined is 2 (M=2).
Here, the operation of the circuit of FIG. 11 when the number M of read signals to be combined is 2 (M=2) will be described with reference to FIG.

In this case, as shown in FIG. 12, the pixel readout signal (pixel signal) PSD[N] without interruption has M (M=2 in this example) reference levels Vrst in one pixel signal PSD[N]. [N,1], Vrst[N,2] and M signal levels Vsig[N,1], Vsig[N,2].
That is, in one uninterrupted pixel signal PSD[N], M reference levels Vrst[N,1] and Vrst[N,2] and M signal levels Vsig[N,1] and Vsig[N]. , 2] are included.
Similarly, in one uninterrupted pixel signal PSD[N+1], M reference levels Vrst[N+1,1], Vrst[N+1,2] and M signal levels Vsig[N+1,1], Vsig[ N+1, 2] are included.

Thus, the pixel signal PSD without interruption includes M reference levels Vrst and M signal levels Vsig in one pixel signal PSD, and the arrangement order thereof is one output data OD[N. , M], the reference levels Vrst[N, M] are always input first, and then the signal levels Vsig[N, M] are input.

In the example of FIG. 12, in the continuous pixel signal PSD[N], two reference levels Vrst[N,1] and Vrst[N,2] are input, and then two signal levels Vsig[N, 1] and Vsig[N, 2] are input.
Similarly, in one continuous pixel signal PSD[N+1], two signal levels Vsig[N+1,1] are input after two reference levels Vrst[N+1,1] and Vrst[N+1,2] are input. ], Vsig[N+1, 2] are input.

As described above, in the continuous pixel signal PSD[N], the reference levels Vrst[N,1] and Vrst[N,2] are input first. The comparator 420 is in the reset state without performing the comparison process, and its output is “1”.
As a result, the input switch 411 of the ADC 410 is held in the ON state (connection state).

In such a state, in the ADC 410, the reference level Vrst[N,1] that is input first is transmitted to the input node [Y] via the input switch 411. Then, in the ADC 410, the clamp circuit 412 turns on the switch SW11 by the clamp signal CLP to change the reference level Vrst appearing at the node [Y] using the new reference level [V10].
At this time, the signal level Vsig[N] becomes a new signal level Vsig[N′] based on the new reference level [V10].
In this case, the difference between the reference level [V10] and the signal level Vsig is constant.

In the ADC 410, the reference level Vrst[N] of the level V10 appearing at the input node [Y] is converted from an analog signal to a digital signal by the conversion unit 413 (first AD conversion-1).
Then, this digital signal is written and held in the holding unit 440-1 via the switch SW440-1, for example.

Next, in the ADC 410, the input switch 411 is held in the ON state, and the reference level Vrst[N,2] is input to the input node [Y].
In the ADC 410, the reference level Vrst[N,2] continuously appearing at the input node [Y] is converted from an analog signal to a digital signal by the conversion unit 413 (second AD conversion-2).
Then, this digital signal, for example, written in the storage unit 440-2 via the switch SW440-2 held.

Next, in the ADC 410, the signal level Vsig[N,1] is input to the input node [Y] while the input switch 411 is held in the ON state.
Here, since the signal level Vsig appears at the input node [Y] of the ADC 410, the signal level Vsig[N] that appears at the input node [Y] and the reference voltage [in the comparator 420 of the comparison and selection unit 430. V20] is compared, and ON/OFF of the input switch 411 is controlled by a signal S420 indicating the result.

When the input switch 411 is held in the ON state, the signal level Vsig of the pixel signal PSD continues to appear at the input node [[Y], and when the input switch 411 is selected in the OFF state, the input node [Y]. Holds the state of the input node [Y] as it is.

The above processing is similarly performed on the pixel signal [N+1] following the pixel signal PSD[N]. Therefore, detailed description thereof will be omitted.

In the pixel signal PSD[N] in the example of FIG. 12, since the signal level Vsig[N,1] input to the input node [Y] is higher than the reference voltage [V20], AD of the signal level Vsig[N,1] is obtained. The conversion result is unnecessary.
That is, in the example of the pixel signal PSD[N] in FIG. 12, the input switch 411 remains in the ON state, the signal level Vsig[N,1] is input subsequently to the signal level Vsig[N,2], and the subsequent The signal level Vsig[N,2] of is the target of the third AD conversion-3.

In this case, since the AD conversion result of the signal level Vsig[N,1] is unnecessary, the reference level Vrst[N,1] paired therewith is unnecessary. As a result, the digital reference level Vrst[N,1] already held in the holding unit 440-1 becomes unnecessary.
Therefore, in the circuit of FIG. 11, the signal level Vsig[N, 2] converted into a digital signal by the conversion unit 413 is overwritten and held in the holding unit 440-1 via the switch SW440-1, for example.

In the pixel signal PSD[N+1] in the example of FIG. 12, the signal level Vsig[N+1,1] input to the input node [Y] is lower than the reference voltage [V20], so the output signal S420 of the comparator 420 is It becomes "0", and the input switch 411 is controlled to be in the off state. As a result, the AD conversion result of the signal level Vsig[N+1,1] subsequent to the signal level Vsig[N+1,1] is unnecessary.
That is, in the example of the pixel signal PSD[N+1] of FIG. 12, the input switch 411 is turned off, the signal level Vsig[N+1, 1] is continuously held at the input node [Y], and the signal level Vsig[N+1, 1] is the target of the third AD conversion-3.

In this case, since the AD conversion result of the signal level Vsig[N+1, 2] is unnecessary, the reference level Vrst[N+1, 2] paired therewith is unnecessary. As a result, the digital reference level Vrst[N+1,2] already held in the holding unit 440-2 becomes unnecessary.
Therefore, in the circuit of FIG. 11, the signal level Vsig[N+1, 1] converted into the digital signal by the conversion unit 413 is overwritten and held in the holding unit 440-2 via the switch SW440-2, for example.

As described above, according to the circuit of FIG. 11 according to the present embodiment, the AD conversion operation, which is conventionally required four times, is performed three times, and the number of the holding units 440 is basically changed from four to three.
Further, at this time, since only the reference level paired with the signal level selected for the third AD conversion-3 is unnecessary, when the holding unit capable of overwriting is provided as in this example, the holding unit 440-1 is provided. Alternatively, by overwriting 440-2, the number of holding units becomes two.
That is, according to the circuit of FIG. 11 according to the present embodiment, the number of holding units does not increase, and the number of holding units can be reduced to a minimum of two.

The operation of the circuit of FIG. 11 when the number M of read signals to be combined is 2 (M=2) has been described above with reference to FIG.
The present invention can be applied not only when the number M of read signals to be combined is 2 (M=2) but also when a larger number of read signals, for example, 4 (M=4) are combined. ..

FIG. 13 illustrates a method of increasing (expanding) the dynamic range in a solid-state imaging device, and a method of combining pixel signals without interruption when the number M of read signals to be combined is 4 (M=4). FIG.

In the pixel signal PSD without interruption, M (=4) signals can have different amplification factors K for the same light amount.
In FIG. 13, M=4, the amplification factor ratio K(1)/K(2)=2, the ratio K(1)/K(3)=3, and the ratio K(1)/K(4)= 4 is an example.

Similar to the example of FIG. 2, the output data OD[*,1], OD[*,2], OD[*,3], OS[*,4] obtained by the uninterrupted pixel signal PSD are as shown in FIG. The signal has characteristics with different inclinations as shown in (A).
In the synthesizing process, the output data OD[*,2], OD[*,3], OS[*,4] are amplified in accordance with the ratio, and as shown in FIG. The final output data ODA is obtained.

At this time, as shown in FIG. 13B, the bonding positions (points) [X] are three points [X1], [X2], and [X3].
[X1] indicates the connecting point between the output data OD[*,1] and OD[*,2], [X2] indicates the connecting point between the output data OD[*,2] and OD[*,3], [X3] indicates a connection point between the output data OD[*,3] and OD[*,4].
Accordingly, the reference voltage [V20] becomes [V20 1], [V20 2], [V20 3].

FIG. 14 is a diagram for explaining the operation of the circuit of FIG. 11 when the number M of read signals to be combined is 4 (M=4).
FIG. 14A shows the case where the signal level Vsig[N, 2] is selected as the target of the third AD conversion-3. FIG. 14B shows the case where the signal level Vsig[N,3] is selected as the target of the third AD conversion-3.

Here, the operation of the circuit of FIG. 11 when the number M of read signals to be combined is 4 (M=4) will be described with reference to FIG.
However, since the processing for the reference level Vrst is basically the same as that in the case of FIG. 12, the processing for the signal level Vsig will be mainly described.

In the example of FIG. 14, the arrangement order is such that the arrangement of M=2 is repeated twice, and the pixel signal PSD[N] with no interruption of M=4 is formed.
In the example of FIG. 14, the comparator operation in the comparator 420 of the comparison/selection unit 430 is performed at the signal levels Vsig[N,1], Vsig[N,2], and Vsig[N,3].

The example of FIG. 14A is the case where the signal level Vsig[N, 2] is selected as the target of the third AD conversion-3, as described above.
In this case, in the comparator 420, the first comparison operation is performed with the signal level Vsig[N,1] and the reference voltage [V20_1].
In the example of FIG. 14A, since the signal level Vsig[N,1] is higher than the reference voltage [V20_1], the AD conversion result of the signal level Vsig[N,1] is unnecessary.
That is, in the example of the pixel signal PSD[N] in FIG. 14A, the input switch 411 remains in the ON state and the signal level Vsig[N, 2] is input subsequently to the signal level Vsig[N, 1]. It

In the comparator 420, the second comparison operation is performed with the signal level Vsig[N,2] and the reference voltage [V20_2].
In the example of FIG. 14A, since the signal level Vsig[N,2] is lower than the reference voltage [V20_2], all subsequent signal processing becomes unnecessary.
That is, the input switch 411 is held in the OFF state, the signal level Vsig[N, 2] is held at the input node [Y] up to the third AD conversion -3, and the conversion operation is performed by the conversion unit 413.

Hereinafter, this operation will be considered in association with the holding unit.
As described in the example of FIG. 12, the holding unit 440-1 temporarily holds the reference level Vrst[N,1] and the holding unit 440-2 holds the reference level Vrst[N,2]).
However, since the signal level Vsig[N,2] is selected as the target of the third AD conversion-3 by the second comparison operation, the reference level Vrst[N,1] held in the holding unit 440-1 is unnecessary. become.
As a result, the holding unit 440-1 is overwritten with the signal level Vsig[N, 2] by the third AD conversion-3.

In the example of FIG. 14B, as described above, the signal level Vsig[N,3] is selected as the target of the third AD conversion-3.
In this case, in the comparator 420, since the signal level Vsig is higher than the reference voltages [V20_1] and [V20_2] in the first and second comparison operations, the input switch 411 is held in the ON state.
In the comparator 420, the third comparison operation is performed with the signal level Vsig[N,3] and the reference voltage [V20_3].
In the example of FIG. 14B, since the signal level Vsig[N,3] is lower than the reference voltage [V20_3], all subsequent signal processing becomes unnecessary.
That is, the input switch 411 is held in the OFF state, the signal level Vsig[N, 3] is held at the input node [Y] until the third AD conversion-3, and the conversion operation is performed by the conversion unit 413.

Hereinafter, this operation will be considered in association with the holding unit.
When the switch 411″ remains in the ON state by the first and second comparison operations, the reference levels Vrst[N,1] and Vrst[N,2 temporarily held in the holding units 440-1 and 440-2 are held. ] Becomes unnecessary.
That is, the holding unit 440-1 is overwritten with the reference level Vrst[N,3] and the holding unit 440-2 is overwritten with the reference level Vrst[N,4].
Since the signal level Vsig[N,3] is selected as the target of the third AD conversion-3 by the third comparison operation, the reference level Vrst[N,4] held and stored in the holding unit 440-2 becomes unnecessary. Become.
That is, the holding unit 440-2 is overwritten with the signal level Vsig[N, 3] by the third AD conversion-3.
As a result, even when the number of continuous pixel signals formed by the extension in which the array of M=2 is repeated is M, the number of holding units remains two. That is, the number of holding parts does not increase.

As described above, according to the first embodiment, the reading unit 80 has the ADC 420 and the comparator 420 configuring the comparison/selection unit 430.
The comparison and selection unit 430 compares the signal level of the input node [Y] with a preset reference voltage [V20] when the signal Vsig of the signal level appears at the force node [Y], and the comparison result In response to the signal S420, the input switch 411 is switched on/off so as to select the input state of the read signal read from the pixel to the input node.
Specifically, when the level of the input node [Y] is higher than the reference voltage [V20], the comparison/selection unit 430 continuously outputs the read signal of the current comparison target and the subsequent read signal of the input node [Y]. The state to be input to is selected and controlled so that the subsequent read signal becomes an AD conversion target to be held.
When the level of the input node [Y] is lower than the reference voltage [V20], the comparison/selection unit 430 selects a state in which the subsequent read signal of the current comparison target read signal is not input to the input node [Y]. , So that the read signal of the current comparison target is the AD conversion target to be held.

Therefore, according to the first embodiment, it is possible to deal with M uninterrupted pixel signals by 2 or more and less than 2M holding units, and perform AD conversion operations less than 2M times. It is possible to suppress an increase in circuit area and an increase in processing time.
Further, the comparison operation using the reference voltage [V20] makes it possible to prevent the boundary from being emphasized due to its own analog noise, and prevents deterioration of AD conversion accuracy while suppressing an increase in circuit area and processing time. It becomes possible.

That is, according to the first embodiment, it is possible to prevent the deterioration of the AD conversion accuracy while suppressing the increase of the circuit area and the processing time, and it is possible to realize the wide dynamic range, which in turn increases the high range. It is possible to realize image quality improvement.

(Second embodiment)
FIG. 15 is a diagram showing a configuration example of a clamp circuit arranged in an input section of an ADC forming a column output readout system of a pixel section of a solid-state imaging device according to the second embodiment of the present invention.
FIG. 15 shows an example in which the input stage of the clamp circuit is extracted, and the clamp circuit 412B is not simplified and is shown as an example including the amplifier AMP11, the capacitors C11 and C12, and the switch SW11. ..
FIG. 16 is a diagram showing an operation example of the circuit of FIG.

The read system of the second embodiment differs from the read system of the first embodiment in the following points.
The read system of the second embodiment basically has two clamp circuits.
Further, in the second embodiment, an example in which the comparison/selection unit is not provided is shown. However, it is possible to provide the comparison/selection unit 430 as in the third embodiment described later.

In the clamp circuit 412B, the clamp unit 412A is formed by sharing the amplifier AMP11, the capacitor C12, and the switch SW11, and only the path selection switches 462-1 and 462-2 and the capacitors C11-1 and C11-2 are added. Are provided.
This suppresses an increase in circuit area.

In the circuit of FIG. 15, the route selection unit 460 is arranged on the input side of the clamp unit 412A of the clamp circuit 412B.
The path selection unit 460 sets a plurality of signal paths 461-1[A] and 461-2[B] through which each of a plurality of (two in this example) read signals to be combined read out from the pixel PXL is individually transmitted. A read signal including the signal and transmitted through one of the signal paths 461-1 and 461-2 according to the path selection signal is supplied to the clamp unit 412A.
The route selection unit 460 is arranged on each of the signal routes 461-1[A] and 461-2[B], and establishes the connection state of the signal routes 461-1 and 461-2 according to the corresponding route selection signals WA and WB. A plurality of route selection switches 462-1 and 462-2 for switching the non-connection state are included.
The capacitor C11-1 is arranged on the signal path 461-1 and the capacitor C11-2 is arranged on the signal path 461-2.

The clamp circuit 412B of FIG. 15 is connected to the input node [Y] through the signal path 461-1[A] or 461-2[B] by the path selection signals WA and WB.
As a result, the two reference levels are held through the signal paths 461-1[A] or 461-2[B], respectively, so that AD conversion can be performed with high accuracy even on a pixel signal without interruption.

(Third Embodiment)
FIG. 17 is a diagram showing a configuration example of a clamp circuit and a comparison/selection unit arranged in an input unit of an ADC forming a column output read system of a pixel unit of a solid-state imaging device according to a third embodiment of the present invention. is there.
FIG. 17 shows an example in which the input stage of the clamp circuit is extracted, and the clamp circuit 412C shows the clamp section 412A in a simplified manner as in FIG.
FIG. 18 is a diagram showing an operation example of the circuit of FIG.

The read system of the third embodiment differs from the read system of the second embodiment in the following points.
In the read system of the third embodiment, the comparison/selection unit 430 described in the first embodiment is arranged, and outputs the output signal S420 of the comparator 420 of the comparison/selection unit 430 and the path selection signals WA and WB. The route selection switches 462-1 and 462-2 are switched on and off (connected state and non-connected state) in association with each other.

Then, in the third embodiment, the path selection switch and the input switch are shared, and the common switches 462-1 and 462-2 are set to the state of the comparison result of the comparator and the corresponding path selection signals WA and WB. The connection state and the non-connection state can be switched in association with each other.

In the example of FIG. 17, the path selection signals WA and WB required for path selection are logically ANDed with the output of the comparator 420 in AND gates 470-1 and 470-2, and AND gates 470-1 and 470-2. Is output to control the path selection switches 462-1 and 462-2 which also have the function of the input switch.

In the circuit of FIG. 17, as shown in FIG. 18, when the output signal S420 of the comparator 420 is “1”, the path selection signals WA and WB are valid, and the state of the input node [Y] is obtained.
However, since the output signal S420 of the comparator 420 becomes "0" at the signal level Vsig [N+1, 2], the immediately following path selection signal WB becomes invalid.
That is, the signal level Vsig[N+1, 1] is held at the input node [Y].

According to the third embodiment, it is possible to obtain the same effects as those of the above-described first and second embodiments.

(Fourth Embodiment)
FIG. 19 illustrates an ADC forming a column output read system of a pixel unit of a solid-state imaging device according to the fourth embodiment of the present invention, a comparison/selection unit, a holding unit arranged on the output side of the ADC, and a combining process. It is a figure which shows the structural example of a part.

The read system of the fourth embodiment differs from the read system of the first embodiment in that the level of the reference voltage [V20] can be changed with time.

The simplest method for synthesizing a plurality of read signals is the first method shown in FIG.
However, when the configuration according to FIG. 11 is used, the coupling point [X] of the plurality of read signals is determined by the reference voltage [V20].
That is, the state in which the reference voltage [V20] changes with time is equivalent to changing the coupling point [X], and it becomes possible to ease the emphasis of the boundary.

FIG. 19 shows a configuration example for changing the reference voltage [V20] with time.
In the example of FIG. 19, as the reference voltage [V20], voltage waveforms [V20_A], [V20_B], and [V20_C] can be selected through the switches 480-1, 480-2, and 480-3.
[V20_A] is a sine wave, [V20_B] is a square wave having multiple levels, and [V20_C] is a noise waveform.
Each waveform is centered on the level of the reference voltage [V20] originally required.

According to the fourth embodiment, it is possible to obtain the same effect as that of the first embodiment described above, and it is possible to prevent the boundary due to analog noise from being emphasized. As a result, the boundary is not emphasized. Complicated signal processing becomes unnecessary, and it becomes possible to suppress an increase in circuit area and an increase in processing time.

The solid-state imaging device 10 described above can be applied as an imaging device to an electronic device such as a digital camera, a video camera, a mobile terminal, a surveillance camera, or a medical endoscope camera.

FIG. 20 is a diagram showing an example of the configuration of an electronic device equipped with a camera system to which the solid-state imaging device according to the embodiment of the present invention is applied.

The electronic device 100 has a CMOS image sensor 110 to which the solid-state imaging device 10 according to the present embodiment can be applied, as shown in FIG.
Further, the electronic device 100 has an optical system (lens or the like) 120 that guides incident light (forms a subject image) to the pixel region of the CMOS image sensor 110.
The electronic device 100 has a signal processing circuit (PRC) 130 that processes the output signal of the CMOS image sensor 110.

The signal processing circuit 130 performs predetermined signal processing on the output signal of the CMOS image sensor 110.
The image signal processed by the signal processing circuit 130 can be displayed as a moving image on a monitor such as a liquid crystal display or can be output to a printer, or can be directly recorded on a recording medium such as a memory card. Is possible.

As described above, by mounting the above-described solid-state imaging device 10 as the CMOS image sensor 110, it is possible to provide a high-performance, small-sized, low-cost camera system.
And electronic devices such as surveillance cameras and medical endoscope cameras used in applications where there are restrictions such as mounting size, number of connectable cables, cable length, installation height, etc. in camera installation requirements. Can be realized.

10... Solid-state imaging device, 20... Pixel part, 30... Vertical scanning circuit, 40... Readout circuit, 410... ADC, 411... Input switch, 412, 412B, 412C... -Clamp circuit, 412A... Clamp section, 413... Conversion section, 420... Comparator, 430... Comparison selection section, 440-1, 440-2... Holding section, 450... Synthesis processing unit, 460... Route selection unit, 461-1, 461-2... Signal route, 462-1, 462-2... Route selection switch, 470-1, 470-2... AND Gate, 480-1, 480-2, 480-3... Switch, 50... Horizontal scanning circuit, 60... Timing control circuit, 70... DSP section, 80... Read section, 100... ..Electronic equipment, 110... CMOS image sensor, 120... Optical system, 130... Signal processing circuit (PRC)

Claims (13)

A solid-state imaging device capable of expanding a dynamic range by combining a plurality of read signals,
A pixel portion in which pixels are arranged,
A reading section including a column signal processing section arranged corresponding to the column output of the pixel section,
Each of the plurality of read signals is formed of a reference level signal and a signal level signal,
The column signal processing unit,
An analog-digital converter (ADC) that converts the plurality of read signals read from the pixels and input to an input node, from analog signals to digital signals (AD);
The level of the input node to which the read signal read from the pixel is input is compared with a preset reference voltage, and the input node of the read signal read from the pixel according to a comparison result. A comparison/selection unit for selecting the input state to
It is connected in parallel to the output of the ADC, and the reference level signal or the signal level signal AD-converted by the ADC is selectively held. and a plurality of holding portions of the small number, only including,
The comparison and selection unit,
When the level of the input node is higher or lower than the reference voltage, a state in which the subsequent read signal is continuously input to the input node to the read signal of the current comparison target is selected, and the subsequent read signal is Control to be the AD conversion target to be held,
When the level of the input node is lower or higher than the reference voltage, the current comparison target read signal is selected so that no subsequent read signal is input to the input node, and the current comparison target read signal is held. A solid-state imaging device that is controlled to be an AD conversion target . Before Symbol ADC is,
The signal of the reference level is input first, then the signal of the signal level is input,
The comparison and selection unit,
When the signal of the signal level appears at the input node, the signal level of the input node is compared with a preset reference voltage, and the read signal read from the pixel according to the comparison result. The solid-state imaging device according to claim 1, wherein an input state of the input signal to the input node is selected. The solid-state imaging device according to claim 1 or 2, wherein including the synthesis processing unit for generating a combined output data stored digital signals before Symbol plurality of holders. At least one of the holding parts is
The solid-state imaging device according to any one of claims 1 to 3, wherein the ADC is capable of overwriting during AD conversion processing. The ADC is
At least a first reference level of the signal input, according to any one of claims 2 4 having a clamping circuit including a clamp portion for fixing the clamp level set in advance according to the clamping signal to the input node Solid-state imaging device. The clamp circuit, on the input side of the clamp unit,
Each of the plurality of read signals to be combined read out from the pixel includes a plurality of signal paths individually transmitted, and the read signal transmitted through any one of the signal paths is clamped according to a path selection signal. The solid-state imaging device according to claim 5 , further comprising a route selection unit that supplies the image to the unit. The route selection unit,
The solid-state imaging device according to claim 6 , further comprising a plurality of route selection switches that are arranged in each of the signal routes and that switch a connection state and a non-connection state of the signal route according to a corresponding route selection signal. The comparison and selection unit,
A comparator for comparing the level of the input node with a preset reference voltage;
Any one of claims 1 to 7, comprising an input switch for switching the connection state and the disconnection state of the signal path to the input node of the read signal read from the pixel according to the comparison result of said comparator The solid-state imaging device according to 1. The route selection unit,
A plurality of route selection switches disposed on each of the signal routes and switching between a connection state and a non-connection state of the signal route according to a corresponding route selection signal,
The comparison and selection unit,
A comparator for comparing the level of the input node with a preset reference voltage;
An input switch for switching a connection state and a non-connection state of a signal path of the read signal read from the pixel to the input node according to a comparison result of the comparator,
The path selection switches and the input switch is shared, the switch of the sharing, the comparator of the comparison results and the corresponding claim 6 wherein said route status connected state and disconnected state dipped associated with the selection signal is switched Solid-state imaging device. The reference voltage is
A level corresponding to binding positions of a plurality of read signals to be synthesized solid-state imaging device according to any one of claims 1-9. The solid-state imaging device according to claim 10 , wherein the reference voltage can change the level with time. A pixel portion in which pixels are arranged,
A reading section including a column signal processing section arranged corresponding to the column output of the pixel section,
The column signal processing unit,
Said plurality of read signals input to the input node read from the pixels includes an analog-to-digital converter (ADC) for analog-digital (AD) converted from an analog signal to a digital signal,
A method for driving a solid-state imaging device capable of expanding a dynamic range by combining a plurality of read signals,
Each of the plurality of read signals is formed of a reference level signal and a signal level signal,
In the AD conversion of the ADC,
The level of the input node to which the read signal read from the pixel is input is compared with a preset reference voltage, and the input node of the read signal read from the pixel according to a comparison result. Comparison selection step to select the input state to
A plurality of holding units, which are connected in parallel to the output of the ADC and have a number smaller than twice the number of read signals to be combined by two or more, are stored in a plurality of holding units, and signals of the reference level AD-converted by the ADC or A holding step of selectively holding the signal,
In the comparison and selection step,
When the level of the input node is higher or lower than the reference voltage, a state in which the subsequent read signal is continuously input to the input node to the read signal of the current comparison target is selected, and the subsequent read signal is Control to be the AD conversion target to be held,
When the level of the input node is lower or higher than the reference voltage, the current comparison target read signal is selected so that no subsequent read signal is input to the input node, and the current comparison target read signal is held. A method for driving a solid-state imaging device, which is controlled to be an AD conversion target . A solid-state imaging device capable of expanding a dynamic range by combining a plurality of read signals,
An optical system for forming a subject image on the solid-state imaging device,
The solid-state imaging device,
A pixel portion in which pixels are arranged,
A reading section including a column signal processing section arranged corresponding to the column output of the pixel section,
Each of the plurality of read signals is formed of a reference level signal and a signal level signal,
The column signal processing unit,
An analog-digital converter (ADC) that converts the plurality of read signals read from the pixels and input to an input node, from analog signals to digital signals (AD);
The level of the input node to which the read signal read from the pixel is input is compared with a preset reference voltage, and the input node of the read signal read from the pixel according to a comparison result. A comparison/selection unit for selecting the input state to
It is connected in parallel to the output of the ADC, and the reference level signal or the signal level signal AD-converted by the ADC is selectively held. and a plurality of holding portions of the small number, only including,
The comparison and selection unit,
When the level of the input node is higher or lower than the reference voltage, a state in which the subsequent read signal is continuously input to the input node to the read signal of the current comparison target is selected, and the subsequent read signal is Control to be the AD conversion target to be held,
When the level of the input node is lower or higher than the reference voltage, the current comparison target read signal is selected so that no subsequent read signal is input to the input node, and the current comparison target read signal is held. An electronic device that is controlled to be an AD conversion target .

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