JP2008067301A - Imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an imaging apparatus capable of obtaining a high-quality image from which noise that is caused during a shift from a motion picture mode to a still picture mode is completely removed, by performing smooth photographing without stress by shortening a shifting period from the motion picture mode to the still picture mode. <P>SOLUTION: When a still picture imaging instruction is input during the motion picture mode, two start pulses are continuously input to a shift register for the electronic shutter of a solid-state imaging apparatus. After lines are reset by scanning with the first pulse, the still picture mode is started by scanning with the second pulse. Thus, according to the present invention, the imaging apparatus can be attained in which the time required for switching the motion picture mode and the still picture mode is shortened and a high-quality still image with no afterimage difference between lines can be photographed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an imaging device including a solid-state imaging device in which unit cells for photoelectrically converting incident light on a semiconductor substrate are arranged in a one-dimensional or two-dimensional manner, and more specifically, a charge remaining in a unit cell. The present invention relates to a technique for reducing noise caused by noise.

  In recent years, imaging devices such as mobile phones with digital cameras have been widely used. In order to achieve both weight reduction by downsizing of the battery and extension of continuous use time, these imaging devices are required to suppress power consumption. Therefore, in many cases, a MOS type image pickup device that consumes much less power than a CCD type image pickup device is employed for these image pickup devices.

  In addition, since various MOS circuits can be easily configured on the same substrate as the pixel in the MOS type solid-state image pickup device, the MOS type solid-state image pickup device has more various functions than the CCD type solid-state image pickup device. Can be implemented. As an example, in a MOS type solid-state imaging device that reads a signal for each line, a function of freely changing a readout line is known. Hereinafter, for convenience of explanation, this function is referred to as “read line changing function”.

  A certain type of imaging device includes a moving image mode for acquiring a moving image and a still image mode for acquiring a still image as a driving method of the solid-state imaging device. An image pickup apparatus having a moving image mode and a still image mode is normally only driven when an imaging instruction is input while the power is on, usually by driving the solid-state image pickup device in the moving image mode and displaying a moving image on a monitor in real time. Only when the shutter button is operated by the user), the solid-state imaging device is driven in the still image mode to capture a still image.

  When a digital camera or a mobile phone camera operates in a moving image mode, a high-speed readout process is required for a built-in solid-state imaging device in order to suppress image distortion. Therefore, in the above-described solid-state imaging device having the read line changing function, the reading operation is speeded up by reading out the pixel signal from only a specific line instead of reading out the pixel signal from all the lines.

A driving method of a solid-state imaging device that can read a specific line is described in Patent Document 1, for example.
JP-A 63-185284

  However, when the driving method of the solid-state imaging device described in Patent Document 1 is applied to the moving image mode, a state difference of the photoelectric conversion unit occurs between lines when moving from the moving image mode to the still image mode. Causes the occurrence. More specifically, when the driving method is switched from the moving image mode to the still image mode, the photoelectric conversion unit of the line where the pixel signal is not read out in the moving image mode reads out the pixel signal in the moving image mode. More charge is accumulated than the photoelectric conversion part of the line. As a result, a difference occurs in the residual electrons (hereinafter referred to as “afterimage”) of the photoelectric conversion unit when acquiring an image in the still image mode, which leads to generation of line noise.

  Therefore, a driving method of a solid-state imaging device that can eliminate such a problem is known. Hereinafter, this method will be briefly described.

  FIG. 20 is a timing diagram illustrating a method for driving a conventional solid-state imaging device.

  In the driving method shown in FIG. 20, when a still image capturing instruction is input during the moving image mode, the reset pulse is skipped for one frame period without immediately shifting from the moving image mode to the still image mode. Is called. As a result, since all lines are once reset before the still image is captured, the generation of noise based on the afterimage difference between the lines is prevented.

  However, in the driving method shown in FIG. 20, at least one frame period is required to shift from the moving image mode to the still image mode. As the number of pixels increases, one frame period becomes longer. Therefore, it becomes more difficult to capture a smooth still image as the number of pixels increases.

  Therefore, the present invention is an image pickup apparatus that reads a signal from a specific line at the time of moving image shooting, the afterimage difference between the line read at the time of moving image shooting and the line that is not read out is completely removed, and still image shooting is performed. An object of the present invention is to provide an imaging apparatus that takes a short time from an instruction to reading a still image.

  In order to solve the above problems, an imaging apparatus according to the present invention stores a signal charge according to the intensity of incident light, and includes a pixel array having a plurality of unit cells arranged in a row direction and a column direction, and a unit A vertical scanning unit that reads out a signal corresponding to the electric charge accumulated in the cell in units of rows and resets the unit cell in units of rows, a receiving unit that receives an input of a still image capturing instruction, and the receiving unit receives the imaging instruction Before, when the vertical scanning means is driven so as to read out the signal charges accumulated in the unit cell at predetermined row intervals, and when the accepting means accepts the imaging instruction, resetting all the rows of the unit cell; Driving means for driving the vertical scanning means so as to read out signals from all the rows of the unit cells within one frame period;

  According to such a configuration, in response to an input of an instruction to capture a still image, all rows of the pixel array are reset and signals are read from all rows within one frame period. Therefore, it is possible to realize a solid-state imaging device that captures a high-quality still image with no afterimage difference between rows within one frame period after the imaging instruction is input.

  The vertical scanning means responds to the supply of the first start pulse from the outside in response to the supply of the electronic shutter vertical shift register for resetting the unit cell for each row and the supply of the second start pulse from the outside. A multiplexer circuit that selects one of a read vertical shift register that reads out a signal from the unit cell for each row, an output of the electronic shutter vertical shift register, and an output of the read vertical shift register and supplies the pixel array to the pixel array; May be included. In this case, the driving means outputs the two first start pulses to the electronic shutter vertical shift register at a time interval smaller than one frame period in response to the input of the imaging instruction to the accepting means, and then for reading. A second start pulse is supplied to the vertical shift register.

  According to such a configuration, after all the pixel rows are reset in accordance with the first start pulse supplied earlier, each pixel row in accordance with the first start pulse and the second start pulse supplied later. The signal from is read out. Since the time difference between the two first start pulses is within one frame period, it is possible to make the period required from when the still image capturing instruction is input until the still image is read out shorter than one frame period. .

  Alternatively, the imaging apparatus according to the present invention further includes an all reset unit that outputs an all reset pulse for resetting all the pixel rows to the vertical scanning unit in response to an input of an imaging instruction to the receiving unit. In response to the supply of the first start pulse from the outside, the scanning means is responsive to the vertical shift register for electronic shutter that resets the unit cell for each row and the supply of the second start pulse from the outside. A readout vertical shift register that reads out a signal from the unit cell for each row, an output of the electronic shutter vertical shift register, an output of the readout vertical shift register, or an all reset pulse is selected and supplied to the pixel array. And a multiplexer circuit. In this case, the driving means outputs the first start pulse to the electronic shutter vertical shift register until one frame period elapses after the all reset pulse is output from the all reset unit, and then the second start pulse. Is output to the vertical shift register for reading.

  According to such a configuration, after all the pixel rows are simultaneously reset by the reset pulse supplied in response to the input of the imaging instruction, each pixel row is changed according to the first start pulse and the second start pulse. Are read out. Since the time difference between the all-reset pulse and the first start pulse is within one frame period, it is possible to make the period required for reading a still picture after inputting a still picture imaging instruction shorter than one frame period. It becomes.

  According to the present invention, the time required for switching from the moving image mode for capturing a moving image to the still image mode for capturing a still image is shorter than one frame period, and a high-quality still image with no afterimage difference between pixel rows is captured. An imaging device that performs

(Embodiment 1)
<Overview>
The imaging apparatus according to Embodiment 1 is characterized in that two electronic shutter start pulses are input to the solid-state imaging apparatus within the same frame period, and line scanning is performed twice using each of the two pulses. Have. An afterimage difference between pixel rows is eliminated by the first pulse, and a still image mode is started by the second pulse. As a result, the time required for switching from the moving image mode to the still image mode can be shortened.

<Configuration of imaging device>
FIG. 1 is a functional block diagram showing a schematic configuration of the imaging apparatus according to Embodiment 1 of the present invention.

  The imaging device 100a according to the present embodiment includes a monitor unit 101, a reception unit 102a, a drive control device 103a, and a solid-state imaging device 105a.

  The receiving unit 102a receives an imaging instruction, and instructs the drive control apparatus 103a to capture a still image in response to the imaging instruction. The imaging instruction is, for example, a signal generated when the user presses the shutter button or a signal generated according to a timer. Note that the reception unit 102a may instruct the monitor unit 101 to stop displaying the moving image in response to the imaging instruction.

  The drive control device 103a generates and generates a start pulse, a reset pulse (RSCELL / ERSCELL), and a readout pulse (TRANS / ETRANS) for driving the solid-state imaging device 105a in accordance with an instruction from the reception unit 102a. The pulse is output to the solid-state imaging device 105a. Further, the drive control device 103a outputs the image data (still image and moving image) output from the solid-state imaging device 105a to the monitor unit 101. The details of the method for driving the solid-state imaging device 105a by the drive control device 103a will be described later.

  The solid-state imaging device 105a includes a pixel array in which a plurality of pixels for photoelectrically converting incident light are arranged, a vertical scanning unit that sequentially scans each row of the pixel array, a horizontal readout circuit, and a final amplifier. The solid-state imaging device 105a outputs to the signal drive control device 103a corresponding to the electric charge accumulated in each pixel in accordance with the start pulse output from the drive control device 103a. Details of the solid-state imaging device 105a will also be described later.

  The monitor unit 101 includes a display device (not shown) such as a liquid crystal display, and displays image data output from the drive control device 103a on the screen of the display device. More specifically, the monitor unit activates the display device when the main switch is turned on, and displays moving image data output from the drive control device 103a at a predetermined frame rate on the screen during the moving image mode. During the still image mode, still image data output from the drive control device 103a is displayed on the screen.

<Schematic configuration of solid-state imaging device>
FIG. 2 is a diagram showing a schematic configuration of the solid-state imaging device shown in FIG. 1, and FIG. 3 is a circuit diagram showing an example of the pixel array shown in FIG. 2 and 3, only 25 unit cells arranged in a 5 × 5 two-dimensional shape are shown for convenience of illustration, but in practice, hundreds of thousands to several numbers are shown in a two-dimensional manner. About one million unit cells are arranged. In the case of a solid-state imaging device in which unit cells are arranged one-dimensionally, hundreds to thousands of pixels are arranged in a straight line.

  With reference to FIG. 2, the solid-state imaging device 105 a includes a pixel array 1, a vertical scanning unit 7 a, a horizontal readout circuit 5, a final amplifier 6, a load circuit 8, and a signal processing circuit 9.

  The vertical scanning unit 7a includes an electronic shutter shift register 2, an image signal readout shift register 3, and a multiplexer circuit 4a. The vertical scanning unit 7a supplies pulses to the reset signal line RSOUT and the transfer signal line TROUT in accordance with the start pulse, reset pulse (RSCELL / ERSCELL), and readout pulse (TRANS / ETRANS) output from the drive control device 103a. Then, the unit cells are reset in units of rows, and signals are read from the unit cells in units of rows.

  The signal charge read from the photoelectric conversion unit of each pixel according to the read pulse is subjected to processing such as noise removal and amplification in the signal processing circuit 9 and then read to the horizontal signal line according to the signal from the horizontal read circuit 5. Further, after being sent to the final amplifier 6, it is output as a pixel signal. The load circuit 8 constitutes an amplification transistor 14 and a source follower circuit in the pixel, which will be described later.

  The pixel array 1 is an imaging region in which a plurality of unit cells that accumulate charges according to the intensity of incident light and output signals according to the accumulated charges are two-dimensionally arranged. As an example, as shown in FIG. 3, the unit cell holds a photodiode 11 that is a photoelectric conversion unit, a read transistor 12 that reads signal charges accumulated in the photodiode 11, and a read signal charge. A floating diffusion (hereinafter referred to as “FD”) 13, a reset transistor 15 that resets the potential of the FD 13 to an initial state, and an amplification transistor 14 that amplifies the signal charge in response to the potential change of the FD 13. The amplification transistor 14 constitutes a load follower circuit 16 and a source follower circuit arranged for each column, and outputs a signal from the pixel to the vertical output signal line 17. The gates of the reset transistors 15 included in the unit cells aligned in the same row are connected to the reset signal lines RSOUT (RSOUT1 to RSOUT5) shown in FIGS. 2 and 3 and included in the unit cells aligned in the same row. Each gate of the read transistor 12 is connected to the transfer signal line TROUT (TROUT1 to TROUT5) shown in FIGS.

  Referring to FIG. 2 again, electronic shutter shift register 2 (hereinafter, simply referred to as “shift register 2”) sequentially shifts the electronic shutter start pulse supplied from the drive control device 103a for each frame. During the moving image mode, the shift register 2 sequentially generates a row address signal for electronic shutter for reading an image signal for each predetermined row. Further, during the still image mode, the shift register 2 sequentially generates a row address signal for electronic shutter for reading an image signal for each row.

  The shift register 2 obtains the exposure time based on the light amount of the subject at the time of moving image display, the setting by the user, the light amount of the subject detected by the photometric sensor, and the like in the moving image mode and the still image mode. Accordingly, the exposure time is adjusted by changing the reset timing.

  The image signal readout shift register 3 (hereinafter simply referred to as “shift register 3”) sequentially shifts the image signal readout start pulse applied from the drive control device 103a for each frame. During the moving image mode, the shift register 3 sequentially generates image signal read row address signals for reading image signals for each predetermined row. Further, during the still image mode, the shift register 3 sequentially generates image signal readout row address signals for each row.

  The multiplexer circuit 4a selects and selects the output from the shift register 2, the output from the shift register 3, the reset pulse (RSCELL / ERSCELL) and the read pulse (TRANS / ETRANS) output from the drive control device 103a. This is a logic circuit that supplies the output to the unit cell in units of rows.

<Shift register for electronic shutter>
FIG. 4 is a circuit diagram showing a schematic configuration of the electronic shutter shift register shown in FIG.

  As shown in FIG. 4, the shift register 2 is composed of a MOS single channel dynamic circuit. In FIG. 4, for convenience of illustration, only the five-stage unit registers corresponding to the respective rows shown in FIG. 2 are shown, but the actual number of unit register stages is equal to the number of rows of the pixel unit 1. It is about several hundred to several thousand stages. Hereinafter, the operation of the shift register 2 will be described.

  FIG. 5 is a diagram illustrating the operation timing of the electronic shutter shift register in the still image mode.

  First, when the level of the electronic shutter start pulse becomes “H” at time t1, the level of the node IN changes to “H”, so that the transistor TR1-1 is turned on.

  Next, when the level of the clock pulse Clk rises from “L” to “H” at time t2, the potential of the node IN to which the gate of the transistor TR1-1 is connected is boosted by the capacitor C1. The potential of OUT1 transitions to “H” in synchronization with the rising edge of the clock pulse Clk. At this time, since the potential of the gate of the transistor TR1-2 is also “H”, the potential of the node NEXT1 changes to “H”.

  Next, when the level of the clock pulse Clk falls from “H” to “L” at time t3, the potential of OUT1 transitions to “L” in synchronization with the fall of the clock pulse Clk. However, since the transistor TR1-2 is a unidirectional element, the potential of the node NEXT1 at this time is maintained at “H”.

  Thereafter, the second to fifth stage unit registers operate in the same manner as the first stage unit register in order according to the clock pulse Clk, and the pulses shown in FIG. 5 are sequentially output to OUT2 to OUT5.

  FIG. 6 is a diagram showing the operation timing of the electronic shutter shift register in the moving image mode.

  The basic pulse control method in the moving image mode is the same as the control method in the still image mode shown in FIG. 5 (control method when signals are read from all pixel rows). However, as shown in FIG. 6, in the moving image mode, the specific line is skipped by increasing the clock pulse of the specific line (for example, even line). Since the signal is transferred to the next line after the idle line, the signal of the next line can be read by returning the pulse width of the clock pulse Clk to the value at the normal reading time. In this way, by applying the timing of the clock pulse Clk, it is possible to read a signal from only an arbitrary line.

  Note that the circuit configuration and operation of the image signal readout shift register 3 are the same as those of the electronic shutter shift register 2, and therefore, repeated description thereof is omitted.

<Multiplexer circuit>
FIG. 7 is a diagram showing the logic of the first stage of the multiplexer circuit shown in FIG. 1, and FIG. 8 is a circuit diagram for realizing the logic shown in FIG.

As shown in FIG. 8, the multiplexer circuit 4a is composed of a MOS single-channel dynamic circuit, and outputs an “H” level signal to the reset signal line RSOUT1 when the following condition a or b is satisfied. .
(A) Both the read shift register output (IN2-1) and the image signal read reset pulse RSCELL (RSINb) are at the “H” level.
(B) Both the electronic shutter shift register output (IN3-1) and the electronic shutter reset pulse ERSCELL (RSINa) are at the “H” level.

Further, the multiplexer circuit 4a outputs an “H” level signal to the transfer signal line TROUT1 when the following condition c or d is satisfied.
(C) Both the read shift register output (IN2-1) and the image signal read readout pulse TRANS (TRINb) are at the “H” level.
(D) Both the electronic shutter shift register output (IN3-1) and the electronic shutter pixel readout pulse ETRANS (TRINA) are at the “H” level.

  Since the second and subsequent stages of the multiplexer circuit 4 are the same as the first stage circuit, the description thereof will not be repeated here.

<Pixel signal readout>
Next, pixel signal readout will be described with reference to the timing chart of FIG. The symbols shown in the timing chart of FIG. 9 represent the following signals (pulses).
OUT1, OUT2: Output of the shift register 3 VDDCELL, LOADCELL, RSCELL, TRANS: Pulses supplied from the drive controller 103a RSOUT1, RSOUT2, TROUT1, TROUT2: Determined by the output of the shift register 3 and the state of RSCELL, TRANS Output of multiplexer 4a FD1: Potential state of FD 13 in the first row in FIG. 3 FD2: Potential state of FD 13 in the second row in FIG. 3 Output signal: Potential state of vertical output signal line 17 in FIG.

  Referring to FIG. 9 together with FIG. 3, first, when selecting the pixel in the first row, the potential of FD1 is made equal to the Hi potential of VDDCELL which is the power source of the reset transistor 15 and the amplification transistor. In addition, the reset pulse RSOUT1 is controlled to the Hi potential. When the reset pulse RSOUT1 transitions to the Hi potential, the reset transistor 15 is turned on. As a result, the potential of FD1 becomes the Hi potential, so that a potential corresponding to the potential of FD1 is output from the output portion of the amplification transistor 14, and the potential of the vertical output signal line 17 rises (time a).

  Next, when the reset pulse RSOUT1 transitions to the low potential, the reset transistor 15 is turned off. At this time, the potential of FD1 is maintained at the Hi potential (time b).

  Next, when the read pulse TROUT1 transitions to the Hi potential, the read transistor 12 is turned on. As a result, the electric charge accumulated in the photodiode 11 is read out to the FD 1 according to the incident light intensity, so that the potential of the FD 1 drops. As the potential of the FD1 drops, the potential of the output portion of the amplification transistor 14 drops, so that the potential of the output signal line drops (time c).

  Next, when the read pulse TROUT1 transitions to the low potential, the read transistor 12 is turned off (time d).

  The signal processing circuit 9 detects the potential of the output signal line at time b and the potential of the output signal line at time d, and measures the potential difference as a pixel signal.

  Next, in order to set the potential of FD1 to the low potential of VDDCELL, when the reset pulse RSOUT1 is changed to the Hi potential, the reset transistor is turned on. As a result, the potential of the FD1 becomes a low potential, and the amplification transistor 14 is turned off. As a result of the above pulse control, the pixel signal output operation of the pixel cell ends (time e).

  Then, after the pixels in the first row of the pixel array are in a non-selected state, the operations for selecting and reading out the pixels in the second row are started according to the same control as above (time f).

<Electronic shutter operation>
Next, an electronic shutter operation (charge discharging operation) for adjusting the exposure time will be described with reference to FIG. The symbols shown in the timing chart of FIG. 10 represent the following signals (pulses).
OUT1, OUT2: Output of shift register 2 ERSCELL, ETRANS: Pulses supplied from drive controller 103a RSOUT1, RSOUT2, TROUT1, TROUT2: Output of shift register 2 and output of multiplexer 4a determined by the state of ERSCELL, ETRANS The other symbols (FD1, FD2) and output signals are the same as those shown in FIG.

  Referring to FIG. 10 together with FIG. 3, the electronic shutter operation aims to discharge the charge of the photodiode 11 and initialize it. Therefore, the selection operation and the reading operation shown in FIG. 9 are simultaneously performed on the pixels in the first row (time g). As a result, charges are discharged to VDDCELL.

  Subsequently, similarly to the read operation, the reset pulse RSOUT1 is controlled to the Hi potential when the VDDCELL is at the Low potential in order to put the pixels in the first row into a non-selected state. At this time, since the potential of FD1 becomes the Low potential, the amplification transistor 14 is turned off (time h).

  Note that the signal processing circuit 9 is maintained in a non-operating state because there is no need for signal detection during the electronic shutter operation.

<Arbitrary line read operation (movie mode)>
Next, an arbitrary row reading operation (driving method in the moving image mode) will be described with reference to FIG. The driving method of the shift register 2 and the shift register 3 is the same as that shown in FIG.

  As shown in FIG. 11, the pixel signal is read from the row to which the normal clocks (OUT1, OUT3) are supplied, and the pixel signal is read from the row to which the high-speed clock (OUT2) is supplied. Not. The same applies to the electronic shutter operation, in which charges are discharged to the rows to which the normal clocks (OUT1, OUT3) are supplied, and charges are discharged to the rows to which the high-speed clock (OUT2) is supplied. Absent.

<Control method>
FIG. 12 is a flowchart showing control processing of the imaging device shown in FIG. 1, and FIG. 13 is a diagram showing pulse supply timings from the drive control device shown in FIG. 1 to the solid-state imaging device. Hereinafter, the control method of the imaging apparatus according to the present embodiment will be described with reference to FIGS. 12 and 13 together.

  (Step 1a) First, the imaging apparatus 100a determines whether or not the main switch is in an ON state. The imaging device 100a proceeds to Step 2a when the main switch is ON, and does not perform the processing after Step 2a in other cases.

  (Step 2a) When the main switch is in the ON state (YES in Step 1a), the imaging device 100a displays a moving image on the screen of the monitor unit 101. More specifically, the drive control device 103a drives the solid-state imaging device 105a in the moving image mode, and outputs moving image data acquired from the solid-state imaging device 105a to the monitor unit 101. This moving image mode refers to a driving method for reading out pixel signals only from specific lines as shown in FIG. The monitor unit 101 displays a moving image continuously read by the drive control device 103a on the screen. Thereafter, the imaging apparatus 100a proceeds to Step 3a.

  (Step 3a) The imaging apparatus 100a determines whether an imaging instruction generated in response to pressing of the shutter button or the like is received. The imaging apparatus 100a proceeds to Step 4a when the reception unit 102a receives an imaging instruction, and returns to Step 1a in other cases.

  (Step 4a) The imaging apparatus 100a supplies the first start pulse to the electronic shutter shift register 2 for the purpose of suppressing the afterimage difference between the line read in the moving image mode and the line not read. More specifically, in Step 3a, when the reception unit 102a detects an instruction to capture a still image, the drive control device 103a is instructed to output an electronic shutter start pulse to the shift register 2. In accordance with an instruction from the receiving unit 102a, the drive control device 103a outputs a first start pulse to the shift register 2 at time T11 shown in FIG. 10, and starts resetting the charges accumulated in all the pixels. In step 4a, the shift register 2 is driven in the same manner as the normal electronic shutter operation shown in FIG. 10 in order to scan all lines. Thereafter, the imaging apparatus 100a proceeds to Step 5a.

  (Step 5a) The imaging device 100a supplies the second start pulse for the purpose of controlling the exposure time (normal electronic shutter operation) after the shift register 2 scans the second line. More specifically, the drive control device 103a outputs a second start pulse to the solid-state imaging device 105a at time T12 after a predetermined time (time within one frame period) has elapsed from time T11. In the present embodiment, time T12 is a time after two lines are scanned after the first start pulse is input to the shift register 2. That is, the transition period “T12-T11” can be set to a period during which the shift register 2 scans two lines.

  When the drive control device 103a outputs the second start pulse to the shift register, exposure for the still image mode starts. After the exposure is started, the drive controller 103a supplies a pixel signal read start pulse to the shift register 3 at time T13 so that the interval between the times T12 and T13 becomes a desired exposure time, and the still image data from the solid-state imaging device 105a. Is read. In Step 5a, the shift registers 2 and 3 are driven in the same manner as the normal pixel signal reading operation and electronic shutter operation shown in FIGS. 9 and 10 in order to scan all lines. Thereafter, the still image data output from the solid-state imaging device 105 a is displayed on the screen by the monitor unit 101.

  (Step 6a) After the still image is displayed on the screen, the imaging apparatus 100 resumes the moving image display and returns to Step 1a.

<Summary>
As described above, in the imaging apparatus 100a according to the present embodiment, two start pulses are continuously input to the electronic shutter shift register 2 in response to a still image imaging instruction. When the first start pulse is input to the shift register 2, all lines are reset in order, and the afterimage difference between the line read in the moving image mode and the line not read out can be suppressed. Further, when the second start pulse is input to the shift register 2, the still image capturing process starts. Also, since two start pulses are input to the shift register 2 within the same frame period, the transition period from the moving image mode to the still image mode is made shorter than one frame period (the shift register 2 scans two lines for the shortest time). Period).

  Therefore, according to the present invention, it is possible to realize an imaging apparatus that can capture a high-quality still image with a short time required for switching between the moving image mode and the still image mode and without an afterimage difference between lines.

(Embodiment 2)
<Overview>
The imaging apparatus according to Embodiment 2 of the present invention includes an all reset unit that simultaneously resets charges accumulated in all unit cells. Since all unit cells are reset once, the afterimage difference between the lines is eliminated. In addition, after the all reset unit resets all unit cells, it is possible to start reading a still image at a desired timing, so that it is possible to reduce the time required for switching from the moving image mode to the still image mode. .

<Configuration>
FIG. 14 is a functional block diagram showing a schematic configuration of the imaging apparatus according to Embodiment 2 of the present invention.

  In the imaging device 100b according to the present embodiment, the receiving unit 102a, the drive control device 103a, and the solid-state imaging device 105a of the imaging device 100a according to Embodiment 1 are replaced with the receiving unit 102b, the drive control device 103b, and the solid-state imaging device 105b, respectively. Further, an all reset unit 104 is added. However, since the basic functions of the elements constituting the imaging apparatus 100b of the present embodiment are the same as those according to the first embodiment, the following describes the present embodiment and the first embodiment. The difference will be mainly described.

  When receiving the imaging instruction, the receiving unit 102b instructs the all reset unit 104 to reset all lines, and then sends a start pulse to the drive control device 103b in order to read still image data from the solid-state imaging device 105b. Instruct to output.

  In response to an instruction from the receiving unit 102b, the all reset unit 104 outputs an all reset pulse for resetting signal charges accumulated in all unit cells to the solid-state imaging device 105b.

  After the all reset unit 104 outputs an all reset pulse to the solid-state imaging device 105b, the drive control device 103b drives the solid-state imaging device 105b in the still image mode, and acquires still image data from the solid-state imaging device 105b.

<Schematic configuration of solid-state imaging device>
FIG. 15 is a diagram showing a schematic configuration of the solid-state imaging device 105b shown in FIG.

  The solid-state imaging device 105b is replaced with a vertical scanning unit 7b including a multiplexer circuit 4b instead of the vertical scanning unit 7a including the multiplexer circuit 4a of the solid-state imaging device according to the first embodiment. The multiplexer circuit 4 b selects one of the all reset pulse ALLRS supplied from the all reset unit 104, the output from the electronic shutter shift register 2, and the output from the image signal readout shift register 3 to select a pixel array. Is a logic circuit to be supplied.

<Multiplexer circuit>
FIG. 16 is a diagram showing the logic of the first stage of the multiplexer circuit shown in FIG. 15, and FIG. 17 is a diagram showing an example of a circuit configuration for realizing the logic shown in FIG.

Referring to FIGS. 16 and 17 together, the multiplexer circuit 4b is composed of a MOS single-channel dynamic circuit, and the reset signal line RSOUT1 is set to the “H” level when either of the following conditions e to g is satisfied. Supply the signal.
(E) Both the all reset pulse ALLRS (IN1) and the electronic shutter pixel reset pulse ERSCELL (RSINa) are “H”.
(F) Both the readout shift register output (IN2-1) and the image signal readout pixel reset pulse RSCELL (RSINb) are “H”.
(G) Both the electronic shutter shift register output (IN3-1) and the electronic shutter pixel reset pulse ERSCELL (RSINa) are “H”.

Further, the multiplexer circuit 4b outputs an “H” level signal to the transfer signal line TROUT1 when the following conditions h to j are satisfied.
(H) Both the all reset pulse ALLRS (IN1) and the electronic shutter pixel readout pulse ETRANS (RSINa) are “H”.
(I) Both the output (IN2-1) of the readout shift register 3 and the image signal readout pixel readout pulse TRANS (RSINb) are “H”.
(J) Both the output (IN3-1) of the electronic shutter shift register 2 and the electronic shutter pixel readout pulse ETRANS (RSINa) are “H”.

  Since the second and subsequent stages of the multiplexer circuit 4b are the same as the first stage circuit, description thereof will not be repeated here.

<Control method>
FIG. 18 is a flowchart showing control processing of the imaging device shown in FIG. 14, and FIG. 19 is a diagram showing pulse supply timings from the drive control device shown in FIG. 14 to the solid-state imaging device.

  (Step 1b) First, the imaging apparatus 100b determines whether or not the main switch is in an ON state. The imaging device 100b proceeds to Step 2b when the main switch is in the ON state, and does not execute the processing after Step 2b in other cases.

  (Step 2b) When the main switch is in the ON state (YES in Step 1b), the imaging device 100b displays a moving image on the screen of the monitor unit 101. More specifically, the drive control device 103b drives the solid-state imaging device 105b in the moving image mode, and outputs the moving image data acquired from the solid-state imaging device 105b to the monitor unit 101. This moving image mode refers to a driving method for reading out only a specific line shown in FIG. 11 of the first embodiment. The monitor unit 101 displays a moving image continuously read by the drive control device 103b on the screen.

  (Step 3b) The imaging apparatus 100b determines whether an imaging instruction generated in response to pressing of the shutter button or the like is received. The imaging apparatus 100b proceeds to Step 4b when the reception unit 102b receives an imaging instruction, and returns to Step 1b in other cases.

  (Step 4b) The imaging device 100b uses the all reset function to reset all the lines of the pixel array. More specifically, in response to a reset instruction from the receiving unit 102b, the all reset unit 104 supplies an all reset pulse to the multiplexer circuit 4b (T21 to T22 in FIG. 19). As shown in FIG. 19, by supplying ETRANS and ERSCELL ("H" application) during a period in which the all reset pulse is supplied (all reset period), the charges accumulated in all the pixels are reset simultaneously. The transition period can be shortened to the all reset period.

  (Step 5b) The imaging device 100b reads the pixel signal from the solid-state imaging device 105b, and outputs the read pixel signal to the monitor unit 101. More specifically, the drive control device 103b supplies a start pulse to each of the shift registers 2 and 3 at times T22 and T23 shown in FIG. 16, and acquires a still image output from the solid-state imaging device 105b. . The roles of the shift registers 2 and 3 are the same as in the first embodiment. The shift register 2 performs an electronic shutter operation for controlling the exposure time, and the shift register 2 performs an operation for reading a pixel signal corresponding to the exposure time. Thereafter, the imaging apparatus 100b proceeds to Step 6b.

  (Step 6b) After the still image is displayed on the screen, the imaging apparatus 100b resumes the moving image display and returns to Step 1b.

<Summary>
As described above, in the imaging apparatus according to the present embodiment, in response to a still image imaging instruction, the all reset unit 104 outputs an all reset pulse to the multiplexer circuit 4b to reset all lines simultaneously. After all the lines are reset at the same time, the still image mode can be started at the desired timing, so the transition period can be shortened to the all reset period, and the time required for transition from the video mode to the still image mode can be shortened. Is possible.

  Therefore, according to the present invention, it is possible to realize an imaging apparatus that can capture a high-quality still image with a short time required for switching between the moving image mode and the still image mode and no afterimage difference between lines.

  In the present embodiment, the all reset unit 104 and the drive control device 103b are configured separately, but the drive control device 103b has a function of the all reset unit 104 (that is, an all reset pulse supply function). May be.

  The present invention can be used for an imaging apparatus including a solid-state imaging apparatus in which a plurality of pixels are arranged in a one-dimensional or two-dimensional manner, such as a digital camera, a camera-equipped mobile phone, and a line sensor.

1 is a functional block diagram showing a schematic configuration of an imaging apparatus according to Embodiment 1 of the present invention. The figure which shows schematic structure of the solid-state imaging device shown by FIG. 1 is a circuit diagram showing an example of the pixel array shown in FIG. FIG. 2 is a circuit diagram showing a schematic configuration of the electronic shutter shift register shown in FIG. The figure which shows the operation timing of the shift register for electronic shutters in still picture mode The figure which shows the operation timing of the shift register for electronic shutters in animation mode The figure which shows the logic of the 1st stage of the multiplexer circuit shown by FIG. Circuit diagram for realizing the logic shown in FIG. The figure which shows the example of a timing of the pixel signal read-out operation | movement of the solid-state imaging device shown by FIG. The figure which shows the example of a timing of the electronic shutter operation | movement of the solid-state imaging device shown by FIG. The figure which shows the example of a timing of arbitrary row read-out operations of the solid-state imaging device shown in FIG. The flowchart which shows the control processing of the imaging device shown by FIG. The figure which shows the supply timing of the pulse from the drive control apparatus shown by FIG. 1 to a solid-state imaging device Functional block diagram showing a schematic configuration of an imaging apparatus according to Embodiment 2 of the present invention. The figure which shows schematic structure of the solid-state imaging device shown by FIG. The figure which shows the logic of the 1st stage of the multiplexer circuit shown by FIG. The figure which shows an example of the circuit structure which implement | achieves the logic shown by FIG. 14 is a flowchart showing control processing of the imaging apparatus shown in FIG. The figure which shows the supply timing of the pulse from the drive control apparatus shown in FIG. 14 to a solid-state imaging device Timing diagram showing a driving method of a conventional solid-state imaging device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pixel array 2 Electronic shutter shift register 3 Image signal readout shift register 4 Multiplexer circuit 7 Vertical scanning unit 100 Imaging device 102 Reception unit 103 Drive control unit 104 All reset unit

Claims (3)

An imaging device,
A pixel array that accumulates signal charges according to the intensity of incident light and has a plurality of unit cells arranged in a row direction and a column direction;
A vertical scanning means for reading out a signal corresponding to the electric charge accumulated in the unit cell in a row unit and resetting the unit cell in a row unit;
Receiving means for receiving an input of a still image capturing instruction;
Before the accepting means accepts the imaging instruction, the vertical scanning means is driven so as to read out the signal charges accumulated in the unit cell at predetermined row intervals, and the accepting means accepts the imaging instruction. In some cases, the imaging apparatus includes: a driving unit that drives the vertical scanning unit so as to perform resetting of all rows of the unit cell and reading of signals from all rows of the unit cell within one frame period. apparatus. The vertical scanning means includes
A vertical shift register for electronic shutter that resets the unit cell for each row in response to the supply of the first start pulse from the outside;
A vertical shift register for reading that reads out a signal from the unit cell for each row in response to the supply of the second start pulse from the outside;
A multiplexer circuit that selects and supplies either the output of the electronic shutter vertical shift register and the output of the readout vertical shift register to the pixel array;
In response to the input of the imaging instruction to the reception unit, the driving unit outputs the two first start pulses to the electronic shutter vertical shift register at a time interval smaller than one frame period, The imaging apparatus according to claim 1, wherein the second start pulse is supplied to the readout vertical shift register. Further comprising an all reset unit for outputting an all reset pulse for resetting all the pixel rows to the vertical scanning unit in response to the input of the imaging instruction to the receiving unit;
The vertical scanning means includes
A vertical shift register for electronic shutter that resets the unit cell for each row in response to the supply of the first start pulse from the outside;
A vertical shift register for reading that reads out a signal from the unit cell for each row in response to the supply of the second start pulse from the outside;
An output of the electronic shutter vertical shift register, an output of the readout vertical shift register, and a multiplexer circuit that selects and supplies any one of the all reset pulses to the pixel array;
The driving means outputs the first start pulse to the electronic shutter vertical shift register until one frame period elapses after the all reset pulse is output from the all reset unit, and then the second reset pulse is output. The image pickup apparatus according to claim 1, wherein the start pulse is output to the vertical shift register for reading.

Images