JP5504910B2 - Imaging apparatus and driving method of imaging apparatus - Google Patents

Description

  The present invention relates to an imaging apparatus and a driving method of the imaging apparatus.

  In recent years, video cameras and digital cameras using CMOS type imaging devices have been widely used. The CMOS type imaging device has a pixel array in which a plurality of pixels are arranged in a two-dimensional matrix. As an electronic shutter system for a CMOS type imaging device, there are a global shutter system that performs a shutter operation simultaneously on one screen and a rolling shutter system that performs a shutter operation for each selected row. In general, a rolling shutter system is often used in a CMOS type imaging apparatus.

  Here, for example, in the case of processing with a high frame rate such as moving image shooting or display of a live view image (hereinafter also referred to as a through image), thinning-out readout is performed without reading out signals of all pixels from the pixel array. When the thinning-out reading is performed, the charge accumulated in the photoelectric conversion unit of the pixel in the row to be skipped is not read out. For this reason, in the rolling shutter system, when the exposure amount is larger than the saturation level of the photoelectric conversion unit, the charge of the photoelectric conversion unit of the pixel in the row to be skipped overflows from the photoelectric conversion unit. In this case, the quality of the captured image is deteriorated due to leakage of charges overflowing from the photoelectric conversion unit to the pixels in the row from which the charges are read (blooming phenomenon).

  In addition, when thinning readout is performed by an imaging apparatus using a rolling shutter system, a technique for suppressing deterioration in image quality is proposed by performing an electronic shutter operation as a countermeasure against blooming on pixels in a row to be skipped. (For example, Patent Document 1). In the configuration of Patent Document 1, the sensor controller obtains the number of rows for which the electronic shutter is simultaneously executed based on the address addition amount, and the electronic shutter operation for preventing blooming is performed on the pixels in the row to be skipped. Controls the vertical selection decoder.

JP 2008-288904 A

  In the technique of Patent Document 1, the number of rows in which the electronic shutter is simultaneously executed is obtained by calculation, and the electronic shutter operation for countermeasures against blooming is performed on the pixels in all rows skipped, so that the control operation becomes complicated. The circuit scale may increase.

  An object of the present invention is to easily suppress deterioration in image quality of a captured image when thinning-out readout is performed without increasing the circuit scale in an imaging apparatus using a rolling shutter system.

The imaging apparatus includes a pixel array in which pixels having photoelectric conversion units that generate and accumulate signal charges according to incident light are arranged in a two-dimensional matrix, a first control that resets the photoelectric conversion units for each row , a signal It has a vertical scanning circuit that executes second control for reading out a pixel signal corresponding to the electric charge from the pixel for each row, and a timing control unit. The timing control unit outputs, to the vertical scanning circuit, a driving clock of the number of times corresponding to the interval of the rows from which the pixel signals are read for each cycle corresponding to the horizontal period for reading the pixel signals for one row. In addition, the timing control unit sends a reset timing signal for controlling the execution timing of the first control and a read timing signal for controlling the execution timing of the second control to the vertical scanning circuit to the odd-numbered driving clock and the even-numbered driving. The clock is output so as to be captured by one and the other of the clock. The vertical scanning circuit has a shift register and a vertical driving circuit. The shift register receives the reset timing signal and the read timing signal, and sequentially transmits the level of the received signal to the subsequent stage in synchronization with the drive clock. The vertical drive circuit receives the output of each stage of the shift register as a vertical shift pulse corresponding to each row of the pixel array, and receives a selection signal indicating whether a pixel signal is to be read out from an odd row or an even row, and the first control is executed. And a row on which the second control is executed are selected based on the vertical shift pulse and the selection signal. In addition, when the thinning readout is performed, the timing control unit outputs a first reset timing signal that controls the reset timing of the photoelectric conversion unit in the row from which the pixel signal is read as a reset timing signal to the shift register, and A second reset timing signal for controlling the reset timing of the photoelectric conversion unit in one row of the row adjacent to the row to be read, and a third reset for controlling the reset timing of the photoelectric conversion unit in the other row of the adjacent row The timing signal is output to the shift register as a reset timing signal.

  According to the present invention, in an imaging apparatus using a rolling shutter system, it is possible to easily suppress deterioration in image quality of a captured image when thinning readout is performed without increasing the circuit scale.

It is a figure which shows the outline | summary of the imaging device in one Embodiment. It is a figure which shows an example of the pixel shown in FIG. FIG. 2 is a diagram illustrating an example of a vertical scanning circuit illustrated in FIG. 1. It is a figure which shows an example of operation | movement of the imaging device shown in FIG. It is a figure which shows another example of operation | movement of the imaging device shown in FIG. It is a figure which shows an example of the camera comprised using the imaging device shown in FIG. It is a figure which shows an example of operation | movement of the imaging device in another embodiment. It is a figure which shows an example of operation | movement of an imaging device when 1/5 thinning-out reading is implemented. FIG. 4 is a diagram illustrating a modification example of the pixel illustrated in FIG. 2. It is a figure which shows an example of operation | movement of the imaging device using the pixel shown in FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows an embodiment of the present invention. The imaging apparatus 10 of this embodiment is a CMOS type imaging apparatus that captures a subject image by a rolling shutter system, for example, and is mounted on a digital camera. The imaging device 10 includes, for example, a pixel array 20, a vertical signal line 22, a constant current source 24, a vertical scanning circuit 30, a horizontal shift register 40, a readout circuit 50, and a timing generator 60.

  The pixel array 20 has a plurality of pixels PX arranged in a two-dimensional matrix of n rows and m columns. For example, red, green, and blue color filters (not shown) are arranged in a Bayer array on the imaging surface of the pixel array 20. Each pixel PX generates an electrical signal (hereinafter also referred to as a pixel signal) corresponding to the amount of light incident through the color filter. A plurality of pixels PX arranged in the column direction (vertical direction in the figure) are connected to the vertical signal line 22 provided for each column. In addition, a constant current source 24 is connected to each vertical signal line 22 in order to read a signal from each pixel PX.

  The vertical scanning circuit 30 receives the drive clocks V1 and V2, the vertical start signal STV, the control signals SELod, SELev, RSTS, and TXS from the timing generator 60, and generates the control signals SEL, RST, and TX. The vertical scanning circuit 30 controls the pixels PX of the pixel array 20 for each row using the control signals SEL, RST, and TX. For example, the vertical scanning circuit 30 controls the pixels PX on the (n−1) th row using the control signals SEL (n−1), RST (n−1), and TX (n−1).

  Details of the vertical scanning circuit 30 will be described later with reference to FIG. Hereinafter, the control signals SELod, SELev, and SEL are also referred to as selection signals SELod, SELev, and SEL, the control signals RSTS and RST are also referred to as reset signals RSTS and RST, and the control signals TXS and TX are also referred to as transfer signals TXS and TX, respectively. .

  The horizontal shift register 40 and the readout circuit 50 function as a horizontal scanning circuit that sequentially outputs the signals VOS and VON of the pixels PX in the row selected by the vertical scanning circuit 30. Here, the signal VON is a noise signal indicating a fixed noise component including a reset noise component of the pixel PX, for example. The signal VOS is a pixel signal including a fixed noise component such as a reset noise component of the pixel PX and a signal component corresponding to the charge generated by the photoelectric conversion unit in the pixel PX.

  The horizontal shift register 40 receives the drive clocks H 1 and H 2 and the horizontal start signal STH from the timing generator 60 and sequentially outputs the horizontal shift pulse SH to the readout circuit 50. For example, the horizontal shift register 40 outputs the horizontal shift pulse SH (m−1) to a high level when the signals VOS and VON corresponding to the signals read from the pixels PX in the m−1th column are output from the read circuit 50. And the other horizontal shift pulses SH including the horizontal shift pulse SH (m) are controlled to a low level.

  The read circuit 50 receives the control signal RH from the timing generator 60 and resets a horizontal signal line (not shown). Further, the readout circuit 50 accumulates the signal output from the pixel PX based on the control signals TS and TN received from the timing generator 60. For example, the readout circuit 50 accumulates the pixel signal output from the pixel PX while the control signal TS is at a high level, and accumulates the noise signal output from the pixel PX when the control signal TN is at a high level. . Then, the readout circuit 50 outputs the pixel signal and noise signal of the column selected by the horizontal shift pulse SH as signals VOS and VON. Here, as the horizontal shift register 40 and the readout circuit 50, well-known ones (for example, Japanese Patent Application Laid-Open No. 2008-11179) can be appropriately selected and used.

  The timing generator 60 controls operations of the vertical scanning circuit 30, the horizontal shift register 40 and the reading circuit 50. For example, when pixel signals are read from all the pixels PX, the timing generator 60 generates drive clocks V1 and V2, a start signal STV, control signals SELod, SELev, RSTS, and TXS as shown in FIG. The operation of the vertical scanning circuit 30 is controlled. Further, for example, when thinning readout is performed, the timing generator 60 generates drive clocks V1 and V2, a start signal STV, control signals SELod, SELev, RSTS, and TXS as shown in FIG. The operation of the circuit 30 is controlled.

  Note that the timing generator 60 may be integrally formed on a substrate on which peripheral circuits such as the pixel array 20 and the vertical scanning circuit 30 are formed, or a substrate other than the substrate on which the pixel array 20 and the like are formed. May be provided. For example, the timing generator 60 may be provided in the control unit 130 shown in FIG.

  FIG. 2 shows an example of the pixel PX shown in FIG. The pixel PX includes a photodiode PD as a photoelectric conversion unit, a transfer transistor MTR, an amplification transistor MAM, a pixel selection transistor MSE, a reset transistor MRS, and a floating diffusion FD (floating diffusion region). In this embodiment, the transistors MTR, MAM, MSE, and MRS formed in the pixel PX are all nMOS transistors. In addition, the floating diffusion FD is a region in which parasitic capacitance for accumulating charges transferred from the photodiode PD is formed (a drain region of the transistor MTR, a wiring region between the transistors MTR and MAM, a gate region of the transistor MAM, a reset transistor MRS). Source region, etc.).

  The photodiode PD is a photoelectric conversion unit that generates and accumulates signal charges according to incident light, and has an anode grounded and a cathode connected to the source of the transfer transistor MTR.

  The transfer transistor MTR is turned on while the transfer signal TX applied to the gate is at a high level, and transfers the signal charge accumulated in the photodiode PD to the floating diffusion FD.

  The amplification transistor MAM has a source connected to the drain of the pixel selection transistor MSE, a drain connected to the power supply VDD, and a gate connected to the drain of the transfer transistor MTR. That is, the voltage corresponding to the signal charge transferred to the floating diffusion FD is input to the gate of the amplification transistor MAM. For example, the amplification transistor MAM outputs, from the source, a voltage obtained by dropping the gate voltage by the threshold voltage of the amplification transistor MAM. As described above, the amplification transistor MAM generates a signal corresponding to the signal charge transferred to the floating diffusion FD.

  The pixel selection transistor MSE is turned on when the selection signal SEL applied to the gate is at a high level, and conducts between the vertical signal line 22 connected to the source and the source of the amplification transistor MAM. Therefore, during the period in which the pixel selection transistor MSE is on, the amplification transistor MAM, the pixel selection transistor MSE, and the constant current source 24 connected to the vertical signal line 22 constitute a source follower circuit. As a result, the signal of the pixel PX selected by the pixel selection transistor MSE is output to the vertical signal line 22.

  The reset transistor MRS has a source connected to the gate of the amplification transistor MAM and a drain connected to the power supply VDD. The reset transistor MRS is turned on while the reset signal RST applied to the gate is at a high level, and resets the charge of the floating diffusion FD.

  FIG. 3 shows an example of the vertical scanning circuit 30 shown in FIG. The vertical scanning circuit 30 includes a vertical shift register 32 and a vertical drive circuit 34.

  The vertical shift register 32 includes n stages of unit circuits 33 connected in cascade. The unit circuit 33 is driven by drive clocks V1 and V2 input to the clock input units CK1 and CK2, respectively. For example, the unit circuit 33 is a static D-type flip-flop circuit that operates in a two-phase clock system. The unit circuit 33 may be configured by omitting one of the clock input units CK1 and CK2, or may include three or more clock input units CK. The unit circuit 33 may be a dynamic D-type flip-flop circuit or a circuit other than the D-type flip-flop circuit.

  The vertical start signal STV is input to the data input section IN of the unit circuit 33 in the first stage. The data input unit IN of the unit circuit 33 in the second and subsequent stages is connected to the data output unit OUT of the unit circuit 33 in the previous stage. Further, a signal output from the data output unit OUT of the unit circuit 33 of each stage is input to the vertical drive circuit 34 as a vertical shift pulse SV corresponding to each row of the pixel array 20. For example, the vertical shift pulse SV (2) corresponds to the second row of the pixel array 20. As described above, the vertical shift register 32 receives the drive clocks V 1 and V 2 and the vertical start signal STV from the timing generator 60 and outputs the vertical shift pulse SV to the vertical drive circuit 34.

  Here, for example, the unit circuit 33 electrically connects the data input unit IN and a data holding unit (not shown) in the unit circuit 33 during a period in which the drive clock V1 is at a high level. During the low level period, the data input unit IN and the data holding unit in the unit circuit 33 are electrically disconnected. The unit circuit 33 electrically connects the data output unit OUT and the data holding unit in the unit circuit 33 when the drive clock V2 is at a high level, and outputs data when the drive clock V2 is at a low level. The unit OUT is electrically disconnected from the data holding unit in the unit circuit 33.

  Therefore, for example, the unit circuit 33 outputs the input signal (input value) of the data input unit IN at the fall of the drive clock V1 from the data output unit OUT at the rise of the drive clock V2. The output signal (output value) of the data output unit OUT is held until the drive clock V2 rises again. As a result, the level of the vertical shift pulse SV is shifted to the subsequent stage every time the drive clock V2 rises.

  The vertical drive circuit 34 has n unit circuits 35 provided for each row of the pixel array 20. Each unit circuit 35 receives one of the selection signals SELod and SELev, the reset signal RSTS, the transfer signal TXS, and the vertical shift pulse SV, and applies the selection signal SEL, the reset signal RST, and the pixel PX in the row corresponding to the vertical shift pulse SV. A transfer signal TX is output. The selection signal SELod is input to the unit circuit 35 corresponding to the odd-numbered row, and the selection signal SELev is input to the unit circuit 35 corresponding to the even-numbered row. For example, each unit circuit 35 includes an AND circuit 36, a level shift circuit 37, a NAND circuit 38, and an AND circuit 39.

  The AND circuit 36 receives the vertical shift pulse SV and the transfer signal TXS, and outputs a logical product result of the vertical shift pulse SV and the transfer signal TXS to the level shift circuit 37. For example, the level shift circuit 37 converts the signal received from the AND circuit 36 into a necessary voltage level, and outputs the converted voltage to the pixel PX as the transfer signal TX. NAND circuit 38 receives vertical shift pulse SV and reset signal RSTS. Then, the NAND circuit 38 outputs a negative logical product result of the vertical shift pulse SV and the reset signal RSTS to the pixel PX as the reset signal RST.

  AND circuit 39 receives one of selection signals SELod and SELev and vertical shift pulse SV. For example, the AND circuit 39 of the unit circuit 35 corresponding to the odd-numbered row outputs the logical product result of the vertical shift pulse SV and the selection signal SELod to the pixel PX as the selection signal SEL. The AND circuit 39 of the unit circuit 35 corresponding to the even-numbered row outputs a logical product result of the vertical shift pulse SV and the selection signal SELev to the pixel PX as the selection signal SEL.

  As described above, the vertical drive circuit 34 generates the control signals SEL, RST, TX based on the vertical shift pulse SV and the control signals SELod, SELev, RSTS, TXS received from the timing generator 60.

  FIG. 4 shows an example of the operation of the imaging apparatus 10 shown in FIG. FIG. 4 shows operations of the vertical shift register 32, the vertical drive circuit 34, and the timing generator 60 when the image signal VOS and the noise signal VON are read from all the pixels PX of the pixel array 20, respectively. Hereinafter, reading the image signal VOS and the noise signal VON from all the pixels PX of the pixel array 20 is also referred to as all-pixel reading.

  Stars in the figure indicate that control signals SEL, RST, TX for resetting the photodiode PD are generated, and triangles generate control signals SEL, RST, TX for reading signals from the pixel PX. It is shown that. That is, the star in the figure indicates that the photodiode PD is reset, and the triangle indicates that a signal is read from the pixel PX. The period TH (TH1-TH10) has the same length as each other, for example, the same length as the horizontal period for sequentially reading out the image signal VOS and the noise signal VON for one row from the pixel PX. Hereinafter, the period TH is also referred to as a horizontal period TH.

  The vertical start signal STV is, for example, a reset timing pulse STV10 for controlling the reset timing of the photodiode PD and a read timing pulse STV20 for controlling the timing of reading a signal from the pixel PX. The drive clocks V1 and V2 are clocks having different phases, for example. For example, the drive clocks V1 and V2 are generated so that the high-level periods do not overlap each other when the vertical shift register 32 is operated. In the case of all pixel readout, the high-level drive clock V2 is output once from the timing generator 60 to the vertical shift register 32 every horizontal period TH. Therefore, in the case of all pixel readout, the cycle of the drive clocks V1 and V2 is the same as the horizontal period TH.

  The selection signal SELev is an inverted signal of the selection signal SELod. For example, the timing generator 60 changes the levels of the selection signals SELev and SELod in synchronization with the rising edge of the drive clock V2. Therefore, in the case of all pixel readout, the cycle of the selection signals SELev and SELod is twice the horizontal period TH. For example, the high-level transfer signal TXS is output once from the timing generator 60 to the vertical drive circuit 34 every horizontal period TH. Therefore, the cycle of the transfer signal TXS is the same as the horizontal period TH. Although not shown in FIG. 4, the reset signal RSTS is maintained at a high level.

  First, the timing generator 60 outputs the reset timing pulse STV10 to the vertical shift register 32 so that the vertical shift pulse SV (1) generated from the reset timing pulse STV10 and the selection signal SELod are at opposite levels. For example, the timing generator 60 changes the drive clock V1 from a high level to a low level when the reset timing pulse STV10 is at a high level. Then, the timing generator 60 changes the drive clock V2 from the low level to the high level, and changes the selection signal SELod from the high level to the low level. Thereby, the operation in the horizontal period TH1 is performed.

  In the horizontal period TH1, the vertical shift register 32 changes the vertical shift pulse SV (1) from the low level to the high level at the rising edge of the drive clock V2. That is, in the horizontal period TH1, the vertical shift pulse SV (1) obtained by shifting the reset timing pulse STV10 by one stage is output from the vertical shift register 32 to the vertical drive circuit 34 at the rising edge of the drive clock V2. Note that the vertical shift pulse SV (1) is maintained at a high level until the drive clock V2 rises again.

  The selection signal SEL (1) is maintained at a low level because the selection signal SELod is at a low level. The reset signal RST (1) changes to a low level because both the reset signal RSTS and the vertical shift pulse SV (1) are at a high level. The reset signal RST (1) is kept at a low level until the vertical shift pulse SV (1) becomes a low level. Further, since the transfer signal TX (1) has the high level of the vertical shift pulse SV (1), the transfer signal TX (1) changes to the high level when the high level transfer signal TXS is input to the vertical drive circuit 34. The transfer signal TX (1) is maintained at a high level while both the transfer signal TXS and the vertical shift pulse SV (1) are at a high level.

  Therefore, in the pixel PX in the first row, the transfer transistor MTR shown in FIG. 2 described above is turned on while the transfer signal TX (1) is at a high level, and the signal charge accumulated in the photodiode PD is transferred to the floating diffusion. Transfer to FD. As a result, the photodiode PD is reset. Note that since the selection signal SEL (1) is at a low level, the charge transferred to the floating diffusion FD is not read out to the vertical signal line 22. The charge of the floating diffusion FD is reset while the reset signal RST (1) is at a high level.

  Thus, in the horizontal period TH1, the photodiode PD of the pixel PX in the first row is reset. In the horizontal period TH1, the vertical shift pulses SV other than the vertical shift pulse SV (1) are at a low level, so the control signals SEL, RST, TX other than the first row are at a low level, a high level, and a low level. Each is maintained. For this reason, in the pixels PX other than the first row, the floating diffusion FD is reset, but the photodiode PD is not reset.

  As described above, in this embodiment, the vertical drive circuit 34 sets the selection signal SEL and the reset signal RST to low level and outputs the high-level transfer signal TXS to the pixel PX in order to reset the photodiode PD. .

  In the horizontal period TH2, the vertical start signal STV is maintained at a low level, for example, at least until the drive clock V2 rises. Therefore, the vertical shift register 32 changes the vertical shift pulse SV (1) from the high level to the low level and changes the vertical shift pulse SV (2) from the low level to the high level at the rising edge of the drive clock V2. That is, in the horizontal period TH2, the vertical shift pulse SV (2) obtained by shifting the reset timing pulse STV10 by two stages is output from the vertical shift register 32 to the vertical drive circuit 34 at the rising edge of the drive clock V2. The vertical shift pulse SV (2) is maintained at a high level until the drive clock V2 rises again.

  The selection signal SEL (2) is maintained at a low level because the selection signal SELev is at a low level. Note that the selection signal SELev changes from a high level to a low level at the rising edge of the drive clock V2. The reset signal RST (2) changes to a low level because both the reset signal RSTS and the vertical shift pulse SV (2) are at a high level. The reset signal RST (2) is kept at a low level until the vertical shift pulse SV (2) becomes a low level.

  Further, the transfer signal TX (2) changes to a high level when the transfer signal TXS is input to the vertical drive circuit 34 because the vertical shift pulse SV (2) is at a high level. The transfer signal TX (2) is maintained at a high level while both the transfer signal TXS and the vertical shift pulse SV (2) are at a high level. Accordingly, in the horizontal period TH2, the photodiode PD of the pixel PX in the second row is reset. Note that, in the horizontal period TH2, the vertical shift pulses SV other than the vertical shift pulse SV (2) are at a low level, so the photodiode PD is not reset in the pixels PX other than the second row.

  In the second half of the horizontal period TH2, the timing generator 60 outputs the reset timing pulse STV10 to the vertical shift register 32 in order to set the vertical shift pulse SV (1) to the high level in the horizontal period TH3.

  In the horizontal period TH3, the vertical shift pulses SV (1) and SV (3) change from a low level to a high level and the vertical shift pulse SV (2) changes from a high level to a low level at the rising edge of the drive clock V2. Change. That is, in the horizontal period TH3, the vertical shift register 32 causes the vertical shift pulse SV (3) obtained by shifting the first reset timing pulse STV10 by three stages and the vertical shift pulse SV obtained by shifting the second reset timing pulse STV10 by one stage. (1) is output to the vertical drive circuit 34. The selection signals SEL (1) and SEL (3) are maintained at a low level because the selection signal SELod is at a low level. Accordingly, in the horizontal period TH3, the second reset is performed on the photodiode PD of the pixel PX in the first row, and the first reset is performed on the photodiode PD of the pixel PX in the third row.

  In the horizontal period TH4, the vertical start signal STV is maintained at a low level, for example, at least until the drive clock V2 rises. Therefore, in the horizontal period TH4, the vertical shift register 32 causes the vertical shift pulse SV (4) obtained by shifting the first reset timing pulse STV10 by four stages and the vertical shift pulse obtained by shifting the second reset timing pulse STV10 by two stages. SV (2) is output to the vertical drive circuit 34.

  Thereby, in the horizontal period TH4, the second reset is performed on the photodiode PD of the pixel PX in the second row, and the first reset is performed on the photodiode PD of the pixel PX in the fourth row. In the second half of the horizontal period TH4, the timing generator 60 outputs a reset timing pulse STV10 to the vertical shift register 32 in order to set the vertical shift pulse SV (1) to a high level in the horizontal period TH5.

  In the horizontal period TH5, the vertical shift register 32 vertically drives the high level vertical shift pulses SV (1) and SV (3) and the high level vertical shift pulse SV (5) not shown in FIG. Output to the circuit 34. As a result, in the horizontal period TH5, the photodiode PD of the pixel PX in the first row is reset for the third time, and the photodiode PD of the pixel PX in the third row is reset for the second time. A first reset is performed on the photodiode PD of the pixel PX.

  Note that the vertical shift pulse SV (1) in the horizontal period TH5 is a signal obtained by shifting the third reset timing pulse STV10 by one stage. The vertical shift pulses SV (3) and SV (5) in the horizontal period TH5 are signals obtained by shifting the vertical shift pulses SV (2) and SV (4) in the horizontal period TH4 by one stage. That is, in the horizontal period TH5, the vertical shift pulse SV (5) is a signal obtained by shifting the first reset timing pulse STV10 by five stages, and the vertical shift pulse SV (3) is obtained by changing the second reset timing pulse STV10 to 3 times. This is a stage shifted signal.

  As described above, the three reset timing pulses STV10 are sequentially shifted every horizontal period TH until they are transmitted to the unit circuit 33 in the final stage of the vertical shift register 32. As a result, the photodiodes PD of the pixels PX in all rows are reset three times. A read timing pulse STV20 is output from the timing generator 60 to the vertical shift register 32 after the exposure time TS after the third reset timing pulse STV10 is output (in the second half of the horizontal period TH7 in the figure). The readout timing pulse STV20 is output so that the exposure time TS is an odd number of horizontal periods TH. As long as this condition is satisfied, the exposure time TS may not be the three horizontal periods TH. In the operations of FIGS. 5, 7, 8, and 10, which will be described later, the exposure time TS is not 3 horizontal periods TH as long as the exposure time TS satisfies the condition that the exposure time TS is an odd number of horizontal periods TH. May be.

  In the horizontal period TH8, the vertical shift register 32 changes the vertical shift pulse SV (1) from the low level to the high level at the rising edge of the drive clock V2. That is, in the horizontal period TH8, the vertical shift pulse SV (1) obtained by shifting the read timing pulse STV20 by one stage is output from the vertical shift register 32 to the vertical drive circuit 34 at the rising edge of the drive clock V2.

  In the horizontal period TH8, the vertical shift register 32 receives the high-level vertical shift pulse SV (4) and the high-level vertical shift pulses SV (6) and SV (8) not shown in FIG. Output to the vertical drive circuit 34. The vertical shift pulses SV (4), SV (6), and SV (8) are signals obtained by shifting the three reset timing pulses STV10.

  The selection signal SEL (1) changes from a low level to a high level because the selection signal SELod is at a high level. The reset signal RST (1) changes to a low level because both the reset signal RSTS and the vertical shift pulse SV (1) are at a high level. Thereby, in the pixel PX in the first row, the pixel selection transistor MSE shown in FIG. 2 is turned on, and the noise signal of the pixel PX is output to the vertical signal line 22. Note that the selection signal SEL (1) is maintained at a high level until one of the vertical shift pulse SV (1) and the selection signal SELod becomes a low level.

  Since the vertical shift pulse SV (1) is at a high level, the transfer signal TX (1) changes to a high level when the transfer signal TXS is input to the vertical drive circuit 34. Accordingly, in the pixel PX in the first row, the transfer transistor MTR is turned on while the transfer signal TX (1) is at a high level, and transfers the signal charge accumulated in the photodiode PD to the floating diffusion FD.

  Since the selection signal SEL (1) is at a high level, the pixel signal corresponding to the charge transferred to the floating diffusion FD is read from the pixel PX to the vertical signal line 22. Thus, in this embodiment, the vertical drive circuit 34 sets the selection signal SEL and the reset signal RST to a high level and a low level, respectively, and reads the high-level transfer signal TX to the pixel in order to read a signal from the pixel PX. Output to PX. That is, in this embodiment, the control signal for reading a signal from the pixel PX is the same as the control signal for resetting the photodiode PD except that the selection signal SEL is at a high level.

  Further, the selection signal SEL (4) and the selection signals SEL (6) and SEL (8) not shown in FIG. 4 are maintained at a low level because the selection signal SELev is at a low level. In other words, the vertical drive circuit 34 outputs a low-level selection signal SEL, a low-level reset signal RST, and a high-level transfer signal TX as control signals for resetting the photodiode PD in the fourth and sixth rows. Output to the pixels PX in the rows and 8th row.

  Thus, in the horizontal period TH8, the pixel signal of the pixel PX in the first row is read out to the vertical signal line 22, and the photodiodes PD of the pixels PX in the fourth row, the sixth row, and the eighth row are reset. . The read timing pulse STV20 is sequentially shifted every horizontal period TH until it is transmitted to the unit circuit 33 in the final stage of the vertical shift register 32. Thereby, in this embodiment, the signals of the pixels PX in all rows can be read out.

  Here, the read timing pulse STV20 is output so as to be captured at the falling edge of the driving clock V1 after an odd number of times from the falling edge of the driving clock V1 that has read the reset timing pulse STV10. For this reason, when there are a plurality of reset timing pulses STV10, the subsequent reset timing pulse STV10 is captured at the falling edge of the driving clock V1 even times after the falling edge of the driving clock V1 that has read the previous reset timing pulse STV10. Is output. Thereby, in this embodiment, the read operation (triangle in FIG. 4) and the reset operation (star in FIG. 4) can be performed in the same horizontal period TH.

  FIG. 5 shows another example of the operation of the imaging apparatus 10 shown in FIG. FIG. 5 shows operations of the vertical shift register 32 and the timing generator 60 when 1/3 decimation readout is performed. For example, in 1/3 decimation readout, the image signal VOS and the noise signal VON are read out from the pixels PX in the 3 × i-th row (i = 1, 2, 3,...). The meanings of stars, triangles, and periods TH (TH1-TH8) in the figure are the same as those in FIG. Although not shown in FIG. 5, the reset signal RSTS is maintained at a high level.

  Further, in FIG. 5, the control signals SEL, RST, and TX output from the vertical drive circuit 34 are omitted for easy understanding of the drawing. For example, in each horizontal period TH, a low-level selection signal SEL and a low-level selection signal SEL as a control signal for resetting the photodiode PD are applied to the pixels PX in the row corresponding to the vertical shift pulse SV on which a star is written. The reset signal RST and the high-level transfer signal TX are output from the vertical drive circuit 34. Further, for example, in each horizontal period TH, the pixel PX in the row corresponding to the vertical shift pulse SV in which a triangle is described is used as a control signal for reading a signal from the pixel PX, and a low-level selection signal SEL and A level reset signal RST and a high level transfer signal TX are output from the vertical drive circuit 34.

  The vertical start signal STV is, for example, reset timing pulses STV10, STV11, and STV12 for controlling the reset timing of the photodiode PD, and a read timing pulse STV20 for controlling the timing of reading a signal from the pixel PX. The reset timing pulse STV10 is a pulse for controlling the reset timing of the photodiode PD in the read target rows (third row, sixth row, ninth row,...).

  The reset timing pulse STV11 is a pulse for controlling the reset timing of the photodiode PD in one of the rows adjacent to the read target row (for example, the fourth row, the seventh row, the tenth row,...). Further, the reset timing pulse STV12 is a pulse for controlling the reset timing of the photodiode PD in the other row (for example, the second row, the fifth row, the eighth row,...) Adjacent to the read target row. .

  For example, the drive clocks V1 and V2 are clocks having different phases. In the case of 1/3 decimation readout, the high-level drive clock V2 is output from the timing generator 60 to the vertical shift register 32 three times for each horizontal period TH. For example, when reading of the signal of the pixel PX is started from the third row, the drive clock V2 is output from the timing generator 60 to the vertical shift register 32 three times at the beginning of each horizontal period TH. Therefore, the repetition period (pattern period) of the drive clock V1 and the drive clock V2 is the same as the horizontal period TH.

  The selection signal SELev is an inverted signal of the selection signal SELod. For example, the levels of the selection signals SELod and SELev change in synchronization with the rising edge of the third drive clock V2 in each horizontal period TH. Therefore, the repetition period of the selection signals SELev and SELod is twice the horizontal period TH. Note that the levels of the selection signals SELod and SELev may change every horizontal period TH. The high-level transfer signal TXS is output once from the timing generator 60 to the vertical drive circuit 34 after, for example, the drive clock V2 is output three times in each horizontal period TH. Therefore, the cycle of the transfer signal TXS is the same as the horizontal period TH.

  First, the timing generator 60 sets the vertical shift pulse SV (1) generated from the reset timing pulse STV10 and the selection signal SELod during the period in which the high-level transfer signal TXS is output to have opposite levels. The reset timing pulse STV10 is output to the vertical shift register 32. For example, the reset timing pulse STV10 is output so as to be captured at the first falling edge of the drive clock V1 in the horizontal period TH1. In FIG. 5, the first falling edge of the drive clock V1 in each horizontal period TH coincides with the starting point of each horizontal period TH. In the operations of FIGS. 7, 8, and 10 to be described later, the first falling edge of the drive clock V1 in each horizontal period TH coincides with the starting point of each horizontal period TH.

  In the horizontal period TH1, the vertical shift register 32 outputs a vertical shift pulse SV (1) obtained by shifting the reset timing pulse STV10 by one stage to the vertical drive circuit 34 at the first rising edge of the drive clock V2. The vertical start signal STV changes to a low level before the second fall of the drive clock V1. Thus, at the second rise of the drive clock V2, the vertical shift pulse SV (1) changes from a high level to a low level, and the vertical shift pulse SV (2) changes from a low level to a high level.

  The reset timing pulse STV11 is output from the timing generator 60 to the vertical drive circuit 34 before the third fall of the drive clock V1. Thereby, at the third rise of the drive clock V2, the vertical shift pulses SV (1) and SV (3) change from the low level to the high level, and the vertical shift pulse SV (2) changes from the high level to the low level. Change to level.

  That is, in the horizontal period TH1, the vertical shift register 32 generates a vertical shift pulse SV (3) obtained by shifting the reset timing pulse STV10 by three stages and a vertical shift pulse SV (1) obtained by shifting the reset timing pulse STV11 by one stage. Output to the vertical drive circuit 34. When the vertical shift pulses SV (1) and SV (3) are at a high level, the selection signal SELod is at a low level. Therefore, in the horizontal period TH1, the photodiodes PD of the pixels PX in the first and third rows are reset. Is done.

  In the horizontal period TH2, the vertical start signal STV is maintained at a low level until, for example, the drive clock V2 rises. Thereby, at the first rise of the drive clock V2, the vertical shift pulses SV (1) and SV (3) change from the high level to the low level, and the vertical shift pulses SV (2) and SV (4) , Change from low level to high level.

  The reset timing pulse STV12 is output from the timing generator 60 to the vertical drive circuit 34 before the second fall of the drive clock V1. Thereby, at the second rise of the drive clock V2, the vertical shift pulses SV (1), SV (3), SV (5) change from the low level to the high level, and the vertical shift pulses SV (2), SV (4) changes from a high level to a low level.

  The vertical start signal STV changes to a low level before the third fall of the drive clock V1. Thereby, at the third rise of the drive clock V2, the vertical shift pulses SV (1), SV (3), SV (5) change from the high level to the low level, and the vertical shift pulses SV (2), SV (4) and SV (6) change from a low level to a high level.

  The vertical shift pulse SV (2) is a signal obtained by shifting the reset timing pulse STV12 by two stages. The vertical shift pulse SV (4) is a signal obtained by shifting the reset timing pulse STV11 by four stages. The vertical shift pulse SV (6) is a signal obtained by shifting the reset timing pulse STV10 by six stages. Since the selection signal SELev is at a low level when the vertical shift pulses SV (2), SV (4), and SV (6) are at a high level, the second, fourth, and sixth rows in the horizontal period TH2. The photodiode PD of the pixel PX is reset.

  In the second half of the horizontal period TH2, the timing generator 60 outputs the reset timing pulse STV10 to the vertical shift register 32 in order to set the vertical shift pulse SV (1) to the high level in the horizontal period TH3.

  In the horizontal period TH3, the vertical shift pulses SV (1), SV (3), SV (5), and SV (7) change from the low level to the high level at the first rise of the drive clock V2, and the vertical The shift pulses SV (2), SV (4), and SV (6) change from a high level to a low level. The vertical start signal STV changes to a low level before the second fall of the drive clock V1. Thereby, at the second rise of the drive clock V2, the vertical shift pulses SV (1), SV (3), SV (5), SV (7) change from the high level to the low level, and the vertical shift pulse SV (2), SV (4), SV (6), and SV (8) change from a high level to a low level.

  At the third rise of the drive clock V2, the vertical shift pulses SV (3), SV (5), SV (7), SV (9) change from low level to high level, and the vertical shift pulse SV (2), SV (4), SV (6), and SV (8) change from a high level to a low level. Note that the vertical shift pulse SV (1) is maintained at a low level.

  Here, the vertical shift pulse SV (3) is a signal obtained by shifting the second reset timing pulse STV10 by three stages. The vertical shift pulse SV (5) is a signal obtained by shifting the reset timing pulse STV12 by five stages. The vertical shift pulse SV (7) is a signal obtained by shifting the reset timing pulse STV11 by 7 stages. The vertical shift pulse SV (9) is a signal obtained by shifting the first reset timing pulse STV10 by nine stages.

  In the horizontal period TH3, the selection signal SELod is at a low level when the vertical shift pulses SV (3), SV (5), SV (7), and SV (9) are at a high level. Therefore, in the horizontal period TH3, the second reset is performed on the photodiode PD of the pixel PX in the third row, and the first reset is performed on the photodiode PD of the pixels PX in the fifth row, the seventh row, and the ninth row. Is implemented.

  In the horizontal period TH4, the vertical start signal STV is maintained at a low level until, for example, at least the third drive clock V2 rises. As a result, the vertical shift register 32 applies the high-level vertical shift pulses SV (6), SV (8), SV (10), SV (12) to the vertical drive circuit at the third rise of the drive clock V2. 34. Thus, the vertical shift pulse SV is shifted by three stages for each horizontal period TH.

  The selection signal SELev is at a low level when the vertical shift pulses SV (6), SV (8), SV (10), and SV (12) are at a high level. Therefore, in the horizontal period TH4, the second reset is performed on the photodiode PD of the pixel PX in the sixth row, and the first reset is performed on the photodiode PD of the pixel PX in the eighth row, the tenth row, and the twelfth row. Is implemented. Thus, the row in which the photodiode PD is reset is shifted by 3 rows for each horizontal period TH.

  In the second half of the horizontal period TH4, the timing generator 60 outputs the reset timing pulse STV10 to the vertical shift register 32 in order to set the vertical shift pulse SV (3) to the high level in the horizontal period TH5.

  In the horizontal period TH5, the vertical shift register 32 is shown in FIG. 5 as high-level vertical shift pulses SV (3), SV (9), SV (11) at the third rise of the drive clock V2. High level vertical shift pulses SV (13), SV (15) which are not present are output to the vertical drive circuit 34.

  The vertical shift pulse SV (3) is a signal obtained by shifting the third reset timing pulse STV10 by three stages. The vertical shift pulse SV (9) is a signal obtained by shifting the second reset timing pulse STV10 by nine stages. The vertical shift pulse SV (11) is a signal obtained by shifting the reset timing pulse STV12 by 11 stages. The vertical shift pulse SV (13) is a signal obtained by shifting the reset timing pulse STV11 by 13 stages. The vertical shift pulse SV (15) is a signal obtained by shifting the first reset timing pulse STV10 by 15 stages.

  The selection signal SELod is at a low level when the vertical shift pulses SV (3), SV (9), SV (11), SV (13), and SV (15) are at a high level. Therefore, in the horizontal period TH5, the third reset is performed on the photodiode PD of the pixel PX in the third row, the second reset is performed on the photodiode PD of the pixel PX in the ninth row, The first reset is performed on the photodiodes PD of the pixels PX in the 13th and 15th rows.

  As described above, the three reset timing pulses STV10 and the reset timing pulses STV11 and STV12 are shifted by three stages every horizontal period TH until they are transmitted to the unit circuit 33 at the final stage of the vertical shift register 32. As a result, the photodiode PD of the pixel PX in the read target row is reset three times, and the photodiode PD of the pixel PX in the row adjacent to the read target row is reset once.

  A read timing pulse STV20 is output from the timing generator 60 to the vertical shift register 32 after the exposure time TS after the third reset timing pulse STV10 is output (in the second half of the horizontal period TH7 in the figure).

  In the horizontal period TH8, the vertical shift register 32 changes the vertical shift pulse SV (3) from the low level to the high level at the third rise of the drive clock V2. That is, in the horizontal period TH8, the vertical shift pulse SV (3) obtained by shifting the read timing pulse STV20 by three stages is output from the vertical shift register 32 to the vertical drive circuit 34 at the third rise of the drive clock V2.

The selection signal SELod is at a high level when the vertical shift pulse SV (3) is at a high level. Thereby, as described in FIG. 4 described above, the signal of the pixel PX in the third row is read out to the vertical signal line 22. The read timing pulse STV20 is shifted by three stages for each horizontal period TH until it is transmitted to the unit circuit 33 in the final stage of the vertical shift register 32. Thereby, in this embodiment, the signal of the pixel PX in the readout target row in the 1/3 thinning readout can be read out.

  In the horizontal period TH8, when the vertical shift pulse SV (vertical shift pulse SV (12), etc.) shifted by the reset timing pulses STV10, STV11, and STV12 is at a high level, the selection signal SELev is at a low level. For this reason, the photodiodes PD of the pixels PX in the 12th, 18th, 20th, 22nd and 24th rows are reset.

  Here, the read timing pulse STV20 is output so as to satisfy the conditions described in FIG. For example, the read timing pulse STV20 is output so that the exposure time TS is an odd number of horizontal periods TH. Therefore, the reset timing pulses STV10, STV11, and STV12 are output so as to satisfy the conditions of the output timing of the reset timing pulse STV10 described in FIG. Thereby, in this embodiment, the read operation (triangle in FIG. 5) and the reset operation (star in FIG. 5) can be performed in the same horizontal period TH.

  In this embodiment, since the photodiode PD of the pixel PX in the row adjacent to the read target row is reset, the charge of the photodiode PD of the pixel PX in the row adjacent to the read target row is prevented from overflowing from the photodiode PD. it can. Thereby, in this embodiment, it is possible to prevent the charge of the photodiode PD of the pixel PX in the row to be skipped from leaking into the pixel in the readout target row (readout row) (blooming phenomenon), and the quality of the captured image Can be suppressed.

  Further, the reset count of the photodiode PD of the pixel PX in the row adjacent to the read target row is set to be smaller than the reset count of the photodiode PD of the pixel PX in the read target row. For this reason, in this embodiment, the number of rows in which the reset operation is performed in one horizontal period TH can be reduced as compared with the case where the same number of resets are performed in all the rows.

  This suppresses fluctuations in the power supply voltage when the horizontal period TH in which only the read operation is performed (horizontal period TH in which the reset operation is not performed) is shifted from the horizontal period TH in which the read operation and reset operation are performed. . For example, noise generated due to fluctuations in the power supply voltage causes a horizontal line pattern (electronic shutter flaw) on the shooting screen. In this embodiment, since fluctuations in the power supply voltage due to the presence / absence of the reset operation can be reduced, a read row in the horizontal period TH in which the read operation and the reset operation are performed, and a read row in the horizontal period TH in which the reset operation is not performed It is possible to suppress electronic shutter scratches that occur in the vicinity of the boundary.

  FIG. 6 shows an example of a camera configured using the imaging device 10 shown in FIG. The camera 100 is a digital camera, for example, and includes an imaging device 10, a photographing lens 110, a memory 120, a control unit 130, a storage medium 140, a monitor 150, and an operation unit 160. The photographing lens 110 forms an image of the subject on the light receiving surface of the imaging device 10. The control unit 130 is, for example, a microprocessor, and controls the operation of the camera 100 based on a program (not shown).

  The memory 120 is a built-in memory formed by, for example, a DRAM (Dynamic RAM), an SRAM (Static RAM), or the like, and temporarily stores image data of an image photographed by the imaging device 10. The control unit 130 is a microprocessor, for example, and controls the operation of the imaging device 10 and the operation of the photographing lens 110 and the like based on a program (not shown). For example, when performing processing with a high frame rate, such as moving image shooting or live view image (through image) display, the control unit 130 causes the imaging device 10 to perform thinning readout.

  The storage medium 140 stores image data of captured images. The monitor 150 is, for example, a liquid crystal display, and displays captured images, images stored in the memory 120, images stored in the storage medium 140, menu screens, and the like. The operation unit 160 includes a release button and other various switches, and is operated by the user in order to operate the camera 100.

  As described above, in this embodiment, the timing generator 60 vertically shifts the reset timing pulse STV10 for the read target row and the reset timing pulses STV11 and STV12 for the row adjacent to the read target row when performing the thinning readout. Output to the register 32. Thereby, in this embodiment, even in the vertical scanning circuit 30 having the vertical shift register 32, the photodiode PD of the pixel PX in the row adjacent to the read target row can be easily reset, and the blooming phenomenon can be easily prevented.

  In this embodiment, since the blooming phenomenon is suppressed with a small number of reset timing pulses (two reset timing pulses STV11 and STV12), the occurrence of electronic shutter scratches can be suppressed. That is, in this embodiment, in the imaging device 10 using the rolling shutter method, it is possible to easily suppress deterioration of the image quality of the captured image when thinning readout is performed without increasing the circuit scale.

  FIG. 7 shows an example of the operation of the imaging apparatus 10 in another embodiment. The imaging apparatus 10 of this embodiment is the same as the above-described embodiment (FIGS. 1 to 6) except for the operation of the timing generator 60. The same elements as those described in FIGS. 1 to 6 are denoted by the same reference numerals, and detailed description thereof will be omitted. FIG. 7 shows operations of the vertical shift register 32 and the timing generator 60 when 1/3 decimation readout is performed. The operation of FIG. 7 is the same as that of FIG. 5 except for the timing at which the reset timing pulses STV11 and STV12 are output. Note that the meanings of stars, triangles, and periods TH (TH1-TH8) in the figure are the same as those in FIG. Although not shown in FIG. 7, the reset signal RSTS is maintained at a high level.

  The reset timing pulse STV11 is output so as to be captured at the falling edge of the driving clock V1 immediately before the falling edge of the driving clock V1 that reads the read timing pulse STV20. For example, the reset timing pulse STV11 is output after the second falling edge of the driving clock V1 in the horizontal period TH7 and before the third falling edge of the driving clock V1.

  Thereby, in the horizontal period TH7, the vertical shift pulse SV (1) changes from the low level to the high level at the third rise of the drive clock V2. That is, the vertical shift register 32 outputs the vertical shift pulse SV (1) obtained by shifting the reset timing pulse STV11 by one stage to the vertical drive circuit 34. Further, the vertical shift register 32 outputs a vertical shift pulse SV (such as a high-level vertical shift pulse SV (9)) obtained by shifting the three reset timing pulses STV10 to the vertical drive circuit 34.

  In the horizontal period TH7, when the vertical shift pulse SV and the vertical shift pulse SV (1) obtained by shifting the three reset timing pulses STV10 are at a high level, the selection signal SELod is at a low level. For this reason, the photodiodes PD of the pixels PX in the first, ninth, fifteenth, and twenty-first rows are reset. The reset timing pulse STV10 is shifted by three stages every horizontal period TH until it is transmitted to the unit circuit 33 at the final stage of the vertical shift register 32. Thereby, in this embodiment, the photodiode PD of the pixel PX in the readout target row in the 1/3 thinning readout can be reset three times. Hereinafter, description of the operation by the reset timing pulse STV10 is omitted.

  In the second half of the horizontal period TH7, the read timing pulse STV20 is output from the timing generator 60 to the vertical shift register 32.

  In the horizontal period TH8, the timing generator 60 outputs the reset timing pulse STV12 to the vertical shift register 32 before the second fall of the drive clock V1, and before the third fall of the drive clock V1. The vertical start signal STV is returned to the low level. The read timing pulse STV20 is output from the timing generator 60 to the vertical shift register 32 before the first fall of the drive clock V1 (the second half of the horizontal period TH7). Here, the timing generator 60 may output the reset timing pulse STV12 and the read timing pulse STV20 as one pulse to the vertical shift register 32. Alternatively, the timing generator 60 may output the reset timing pulses STV11 and STV12 and the read timing pulse STV20 to the vertical shift register 32 as one pulse.

  As a result, in the horizontal period TH8, the vertical shift register 32 shifts the reset timing pulse STV12 by two stages at the third rising edge of the drive clock V2, and the read timing pulse STV20 by three stages. The shifted vertical shift pulse SV (3) and the vertical shift pulse SV (4) obtained by shifting the reset timing pulse STV11 by four stages are output to the vertical drive circuit 34.

The selection signal SELod is at a high level when the vertical shift pulse SV (3) is at a high level. Thereby, as described in FIG. 4 described above, the signal of the pixel PX in the third row is read out to the vertical signal line 22. Since the selection signal SELev is an inverted signal of the selection signal SELod, the photodiodes PD of the pixels PX in the second and fourth rows are reset.

  The read timing pulse STV20 and the reset timing pulses STV11 and STV12 are shifted by three stages for each horizontal period TH until they are transmitted to the unit circuit 33 at the final stage of the vertical shift register 32. In this embodiment, the read timing pulse STV20 and the reset timing pulses STV11 and STV12 are output continuously. For this reason, the reset timing pulses STV11 and STV12 reach the final stage unit circuit 33 at the drive clock V2 before and after the drive clock V2 when the read timing pulse STV20 reaches the final stage unit circuit 33, respectively.

  Therefore, in this embodiment, the electronic shutter flaw due to the presence or absence of the reset operation based on the reset timing pulses STV11 and STV12 occurs in the end row of the pixel array 20. In general, since the pixel signal of the pixel PX in the end row of the pixel array 20 is not used for image processing, the occurrence of electronic shutter flaws can be suppressed.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, in this embodiment, since the output timings of the read timing pulse STV20 and the reset timing pulses STV11 and STV12 are close, the occurrence of electronic shutter flaws can be further suppressed.

  In the above-described embodiment, the example in which the photodiode PD of the pixel PX in the read target row is reset three times has been described. The present invention is not limited to such an embodiment. For example, the photodiode PD of the pixel PX in the read target row may be reset four times or more. Alternatively, the number of resets of the photodiode PD of the pixel PX in the read target row may be one or two. That is, the number of resets of the photodiode PD of the pixel PX in the read target row may be set according to the capacitance of the photodiode PD and the exposure time TS. Also in this case, the same effect as the above-described embodiment can be obtained.

  In the embodiment described above, an example in which 1/3 decimation readout (decimation readout for reading out pixel signals every three rows by skipping two rows between rows) has been described. The present invention is not limited to such an embodiment. For example, 1/5 decimation readout (decimation readout for skipping 4 rows and reading out pixel signals every 5 rows) may be performed. Also in this case, the same effect as the above-described embodiment can be obtained.

  FIG. 8 shows an example of the operation of the imaging apparatus 10 when 1/5 decimation readout is performed. The operation of FIG. 8 is the same as that of FIG. 5 described above except for the number of drive clocks V1 and V2 output in one horizontal period TH and the exposure time TS. In FIG. 8, in order to illustrate the read timing pulse STV20, the exposure time TS is described as one horizontal period TH. Further, the meanings of stars, triangles, and periods TH (TH1-TH8) in the figure are the same as those in FIG. Detailed descriptions of operations similar to those described in FIG. 5 are omitted.

  In the case of 1/5 decimation readout, the high level drive clock V2 is output from the timing generator 60 to the vertical shift register 32 five times for each horizontal period TH. For example, when reading of the signal of the pixel PX is started from the fifth row, the drive clock V2 is output from the timing generator 60 to the vertical shift register 32 five times at the beginning of each horizontal period TH. Further, the levels of the selection signals SELod and SELev change, for example, in synchronization with the rising edge of the fifth drive clock V2 in each horizontal period TH.

  The reset timing pulse STV11 is output from the timing generator 60 to the vertical shift register 32 so as to be captured at the fifth (last) falling edge of the drive clock V1 in the horizontal period TH1. The reset timing pulse STV12 is output from the timing generator 60 to the vertical shift register 32 so as to be captured at the second falling edge of the drive clock V1 in the horizontal period TH2. The three reset timing pulses STV10 are output from the timing generator 60 to the vertical shift register 32 so as to be captured at the first falling edge of the drive clock V1 in the horizontal periods TH1, TH3, and TH5.

  As a result, the photodiode PD of the pixel PX in the read target row is reset three times, and the photodiode PD of the pixel PX in the row adjacent to the read target row is reset once. Note that a row that is two rows away from the read target row is not reset. Even when the number of rows skipped increases, it is not necessary to increase the reset timing pulses STV11 and STV12 for preventing the blooming phenomenon, so that the level of the electronic shutter flaw can be prevented from increasing.

  In the above-described embodiment, the example in which the signal is read from the pixel PX in the third row when the 1/3 decimation readout is performed has been described. The present invention is not limited to such an embodiment. For example, when 1/3 decimation readout is performed, a signal may be read from the pixel PX on the first row, or a signal may be read from the pixel PX on the second row. In this case, the output timing of the read timing pulse STV20 and the reset timing pulses STV11 and STV12 may be shifted according to the read target row. Also in this case, the same effect as the above-described embodiment can be obtained.

  In the above-described embodiment, the example in which the amplification transistor MAM is provided for each pixel PX has been described. The present invention is not limited to such an embodiment. For example, as shown in FIG. 9, one amplification transistor MAM may be shared by a plurality of pixels PX. Also in this case, the same effect as the above-described embodiment can be obtained.

  FIG. 9 shows a modification of the pixel PX shown in FIG. The pixel configuration shown in FIG. 9 is the same as that described above except that one pixel sharing unit PXC (amplification transistor MAM, pixel selection transistor MSE, reset transistor MRS, and floating diffusion FD) is shared by two pixels. It is the same as FIG. The same elements as those described in FIGS. 1 to 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  The pixel group PXG is composed of two pixels adjacent in the column direction, and includes pixel main parts PXMa and PXMb and a pixel sharing part PXC. The pixel main part PXM (PXMa, PXMb) is provided for each pixel constituting the pixel group PXG, and the pixel sharing part PXC is shared by two pixels constituting the pixel group PXG. Each pixel main part PXM (PXMa, PXMb) includes a photodiode PD (PDa, PDb) and a transfer transistor MTR (MTRa, MTRb). The pixel sharing unit PXC includes an amplification transistor MAM, a pixel selection transistor MSE, a reset transistor MRS, and a floating diffusion FD. Note that the drains of the transfer transistors MTRa and MTRb are commonly connected to the gate of the amplification transistor MAM.

  That is, the pixel (one pixel in the pixel group PXG) configured by the pixel main part PXMa and the pixel sharing unit PXC has the same configuration as the pixel PX illustrated in FIG. Further, a pixel (another one pixel in the pixel group PXG) configured by the pixel main portion PXMb and the pixel sharing portion PXC has the same configuration as the pixel PX illustrated in FIG. Therefore, the configuration and operation of the solid-state imaging device 10 having the pixel group PXG are the same as those in FIGS. 4, 5, and 8, respectively, except that one pixel sharing unit PXC is shared by two pixels. It is.

  For example, the selection signal SELG for controlling the pixel selection transistor MSE of the pixel group PXG is generated by the logical sum of the selection signal SEL (a) and the selection signal SEL (b) shown in FIG. For example, the reset signal RSTG for controlling the reset transistor MRS of the pixel group PXG is generated by the logical product of the reset signal RST (a) and the reset signal RST (b) shown in FIG. Here, the selection signal SEL (a) and the reset signal RST (a) are output from, for example, the unit circuit 35 that generated the control signal TX (a) in the unit circuit 35 illustrated in FIG. Further, the selection signal SEL (b) and the reset signal RST (b) are output from, for example, the unit circuit 35 that generates the control signal TX (b) among the unit circuits 35 illustrated in FIG.

  FIG. 10 shows an example of the operation of the imaging apparatus 10 using the pixels shown in FIG. The operation in FIG. 10 corresponds to the operation in FIG. 7 described above, and is the same as that in FIG. 7 except for the timing at which the reset timing pulses STV11 and STV12 are output. Note that the selection signal SELG_1 and the reset signal RSTG_1 in the drawing are the selection signal SEL and the reset signal RST of the pixel group PXG including the pixels in the first and second rows. The selection signal SELG_2 and the reset signal RSTG_2 are the selection signal SEL and the reset signal RST of the pixel group PXG including the pixels in the third and fourth rows. Further, the meanings of stars, triangles, and periods TH (TH1-TH10) in the figure are the same as those in FIG. Detailed description of operations similar to those described in FIG. 7 is omitted.

  The reset operation (stars in FIG. 10) by the reset timing pulses STV11 and STV12 is performed in a row adjacent to the row read out two rows before the row in which the read operation is performed (triangle in FIG. 10). For example, the reset timing pulse STV11 is output so as to be captured at the falling edge of the driving clock V1 five times after the falling edge of the driving clock V1 that reads the read timing pulse STV20. Further, for example, the reset timing pulse STV12 is output so as to be captured at the falling edge of the driving clock V1 that is seven times after the falling edge of the driving clock V1 that reads the read timing pulse STV20.

  As a result, the read timing pulse STV20 and the reset timing pulses STV11 and STV12 arrive at the unit circuit 33 in the final stage at an interval relatively close. As a result, the occurrence of scratches on the electronic shutter can be suppressed even in the operation of FIG. Note that the reset operation for the row adjacent to the last row to be read is performed before the read operation for the next frame is performed. Therefore, the blooming phenomenon can be prevented even in the operation of FIG.

  Here, the reset operation by the reset timing pulses STV11 and STV12 may be performed on a row adjacent to a row to be read after the row on which the read operation is performed. In this case, for example, the reset timing pulse STV11 is the falling edge of the driving clock V1 seven times before the falling edge of the driving clock V1 that reads the reading timing pulse STV20 (in FIG. 10, the third driving clock V1 of the horizontal period TH5). Output at the falling edge). Further, for example, the reset timing pulse STV12 is the falling edge of the driving clock V1 five times before the falling edge of the driving clock V1 that reads the reading timing pulse STV20 (in FIG. 10, the second driving clock V1 of the horizontal period TH6). It is output so that it is captured at the falling edge. Even in this case, the occurrence of scratches on the electronic shutter can be suppressed. Further, in this case, since the reset operation for the row adjacent to the read target row is performed before the read operation (two before the horizontal period TH), the blooming phenomenon can be reliably prevented.

  Alternatively, the reset timing pulses STV11 and STV12 may be output so as to be captured at the falling edge of the driving clock V1 five times after and five times before the driving clock V1 reading the reading timing pulse STV20. Even in this case, the blooming phenomenon and the occurrence of scratches on the electronic shutter can be suppressed.

  As described above, by controlling the output timing of the reset timing pulses STV11 and STV12, the same effect as in the above-described embodiment can be obtained even in a configuration in which one amplification transistor MAM is shared by a plurality of pixels PX. it can.

  In the embodiment described with reference to FIGS. 1 to 6 described above, an example in which the interval between the output timings of the reset timing pulses STV11 and STV12 and the output timing of the reset timing pulse STV10 is set to be shorter than twice the horizontal period TH. Stated. The present invention is not limited to such an embodiment. For example, the interval between the output timings of the reset timing pulses STV11 and STV12 and the output timing of the reset timing pulse STV10 may be set to be twice or more the horizontal period TH. Furthermore, the interval between the output timing of the reset timing pulse STV11 and the output timing of the reset timing pulse STV12 may be set to be twice or more the horizontal period TH.

  In this case, the occurrence location of electronic shutter flaws depending on whether or not the reset timing pulses STV10, STV11, and STV12 are reset can be dispersed, and the level of one electronic shutter flaw can be reduced. Thereby, the electronic shutter flaw can be made inconspicuous. Therefore, also in this case, the same effect as that of the above-described embodiment can be obtained.

  As mentioned above, although this invention was demonstrated in detail, said embodiment and its modification are only examples of this invention, and this invention is not limited to this. Obviously, modifications can be made without departing from the scope of the present invention.

  It can be used for an imaging apparatus and a driving method of the imaging apparatus.

  DESCRIPTION OF SYMBOLS 10 ... Imaging device; 20 ... Pixel array; 22 ... Vertical signal line; 24 ... Constant current source; 30 ... Vertical scanning circuit; 32 ... Vertical shift register; 34 ... Vertical drive circuit; 60 timing generator; FD floating diffusion; MAM amplification transistor; MRS reset transistor; MSE pixel selection transistor; MTR transfer transistor; PD photodiode; PX pixel

Claims (8)

A pixel array in which pixels having photoelectric conversion units that generate and store signal charges according to incident light are arranged in a two-dimensional matrix;
A vertical scanning circuit that executes first control for resetting the photoelectric conversion unit for each row and second control for reading out a pixel signal corresponding to the signal charge from the pixel for each row ;
For each cycle corresponding to a horizontal period for reading out the pixel signals for one row, a drive clock of the number of times corresponding to the row interval from which the pixel signals are read out is output to the vertical scanning circuit, and the first control a reset timing signal for controlling the execution timing and read timing signals for controlling the execution timing of the second control, are taken respectively by one and the other of the odd-numbered of the drive clock and the even-numbered of the driving clock to said vertical scanning circuit And a timing control unit that outputs ,
The vertical scanning circuit includes:
A shift register that receives the reset timing signal and the read timing signal and sequentially transmits the level of the received signal to a subsequent stage in synchronization with the drive clock;
The first control is executed by receiving the output of each stage of the shift register as a vertical shift pulse corresponding to each row of the pixel array, and receiving a selection signal indicating whether the pixel signal is to be read out in an odd row or an even row. A vertical drive circuit that selects a row and a row on which the second control is executed based on the vertical shift pulse and the selection signal;
When thinning-out reading is performed, the timing control unit outputs, as the reset timing signal, the first reset timing signal that controls the reset timing of the photoelectric conversion unit in the row from which the pixel signal is read to the shift register. And a second reset timing signal for controlling a reset timing of the photoelectric conversion unit in one row adjacent to the row to be read, and a reset of the photoelectric conversion unit in the other row of the adjacent row An image pickup apparatus that outputs a third reset timing signal for controlling timing to the shift register as the reset timing signal . The imaging device according to claim 1,
The timing control unit outputs the first reset timing signal to the shift register so that the number of resets of the photoelectric conversion unit of the row to be read is a predetermined number of times of 2 or more, and the adjacent row The imaging apparatus, wherein the second reset timing signal and the third reset timing signal are output to the shift register so that the number of resets of the photoelectric conversion unit is less than the predetermined number. The imaging device according to claim 1 ,
Before Symbol timing controller, and the interval between the output timing of the respective output timing as the first reset timing signal of the second reset timing signal and said third reset timing signal is equal to or greater than 2 times the horizontal period An image pickup apparatus that outputs the drive clock, the first reset timing signal, the second reset timing signal, and the third reset timing signal to the shift register . The imaging device according to claim 3.
The timing control unit includes the second reset timing signal and the second reset timing signal so that an interval between an output timing of the second reset timing signal and an output timing of the third reset timing signal is at least twice the horizontal period . 3. An image pickup apparatus that outputs a reset timing signal to the shift register . The imaging device according to claim 3.
The timing controller, and the interval between the output timing of the respective output timing before Symbol second reset timing signal and said third reset timing signal the read timing signal is below 3 times the horizontal period, the An image pickup apparatus that outputs the second reset timing signal and the third reset timing signal to the shift register . The imaging apparatus according to claim 2, wherein
The first reset timing signal is periodically output during the first control,
The exposure time is controlled in a period between the first reset timing signal output last and the readout timing signal output in the second control,
The period is an odd number of horizontal periods
An imaging apparatus characterized by that. The imaging device according to claim 1,
The timing controller further outputs a transfer signal to the vertical drive circuit,
The vertical drive circuit executes the first control according to the transfer signal and the vertical shift pulse.
An imaging apparatus characterized by that. Corresponding to the pixel array in which pixels having photoelectric conversion units that generate and store signal charges according to incident light are arranged in a two-dimensional matrix, the first control for resetting the photoelectric conversion units for each row, and the signal charges A vertical scanning circuit that executes second control for reading out pixel signals to be read from the pixels for each row, a shift register that sequentially transmits the received signal level to a subsequent stage in synchronization with a drive clock, and The output of each stage of the shift register is received as a vertical shift pulse corresponding to each row, the selection signal indicating whether the pixel signal is to be read is an odd row or an even row, and the row in which the first control is executed and the first And a vertical driving circuit that selects a row on which control is performed based on the vertical shift pulse and the selection signal in a driving method of an imaging apparatus included in the vertical scanning circuit. I,
For each cycle corresponding to a horizontal period for reading out the pixel signals for one row, the drive clock is output to the shift register a number of times corresponding to the row interval from which the pixel signals are read out, and the first control A reset timing signal for controlling the execution timing and a read timing signal for controlling the execution timing of the second control are captured by the shift register at one and the other of the odd-numbered drive clock and the even-numbered drive clock, respectively. Output to
When thinning-out reading is performed, a first reset timing signal that controls the reset timing of the photoelectric conversion unit in the row from which the pixel signal is read is output to the shift register as the reset timing signal and is read out. A second reset timing signal for controlling a reset timing of the photoelectric conversion unit in one row adjacent to the row, and a third for controlling a reset timing of the photoelectric conversion unit in the other row of the adjacent row. A driving method of an imaging apparatus, wherein a reset timing signal is output to the shift register as the reset timing signal.

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