JP2010263509A - Solid-state imaging apparatus and driving method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus suppressing an image defect caused by lacking a capability for resetting a potential of a capacitance element to a reference potential, and to provide a driving method of the solid-state imaging apparatus. <P>SOLUTION: A solid-state imaging apparatus includes: a pixel array comprised of unit pixels 1; a row selection circuit; a capacitance element 4 for accumulating signal potentials output from the unit pixels 1; a first CP transistor 5 and a second CP transistor 16 for setting a potential of the capacitance element 4 to a black reference potential; an AMP 13; an SW 11 which causes an output amplifier to output the signal potential of the capacitance element 4; and a first S/R 8 and a second S/R 14 in which the SW 11 is selected sequentially to ON state, so that the AMP 13 sequentially outputs the signal potential of the capacitance element 4 corresponding to the turned-on SW 11, the second CP transistor 16 is sequentially selected to ON state, so that the potential of the capacitance element 4 corresponding to the turned-on second CP transistor 16 is sequentially set to the black reference potential. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, and more particularly to a MOS (Metal Oxide Semiconductor) type solid-state imaging device.

  In recent years, digital video cameras, digital still cameras, and the like using solid-state imaging devices have become widespread regardless of whether they are for home use or business use. There are two main solid-state imaging devices, a CCD image sensor and a MOS image sensor.

  Among these, the MOS type image sensor has the advantages that it can operate with lower power consumption than the CCD type image sensor and can be manufactured by an existing MOS process, and the adoption ratio is increasing. Hereinafter, a conventional solid-state imaging device disclosed in Patent Document 1 will be described with reference to FIG. FIG. 16 is a circuit diagram showing a configuration of the solid-state imaging device of Patent Document 1.

  As shown in FIG. 16, in this solid-state imaging device, a plurality of pixel MOS transistors 101 constituting a unit pixel (cell) are arranged in a matrix. The solid-state imaging device includes a vertical scanning circuit (row selection circuit) 102 and a horizontal scanning circuit 108 each including a shift register and the like, and a driving pulse φVm from the vertical scanning circuit 102 is supplied to m rows via the vertical selection line 103. Input to the gate of the pixel MOS transistor 101 of the eye.

  The source of the pixel MOS transistor 101 is connected to the vertical signal line 105 and the drain thereof is connected to the power supply line 104 to which the power supply VDD is supplied. A load capacitance element (load capacitor) 114 that holds a signal potential (pixel signal) is connected to the vertical signal line 105 via an operation MOS switch 113. The load capacitive element 114 is inserted between the vertical signal line 105 and the ground potential. An operation pulse φSH is applied to the gate of the operation MOS switch 113.

  A load capacitance reset MOS switch (clamping transistor) 115 is connected in parallel to the load capacitance element 114, and a reset pulse (clamp pulse) φCRST is applied to the gate of the load capacitance reset MOS switch 115. The load capacitance element 114 is connected to the drain of a horizontal MOS switch (column selection switch) 109, and the source of the horizontal MOS switch 109 is connected to the horizontal signal line 110. Here, the capacitance of the load capacitive element 114 is set to be equal to or larger than the capacitance of the vertical signal line 105.

  The horizontal scanning circuit 108 sequentially supplies a horizontal scanning signal (pulse voltage) φHm to the gate of each horizontal MOS switch 109, and supplies the signal potential held in each load capacitance element 114 to the output circuit through the horizontal signal line 110.

Japanese Patent Laid-Open No. 7-255013

  By the way, the solid-state imaging device of Patent Document 1 has a structure in which a clamping transistor is made conductive by a clamping pulse φCRST and reset simultaneously in order to reset the potential of the capacitive element (column selection switch) of each column to a reference potential. have. However, in the solid-state imaging device disclosed in Patent Document 1, for example, when a subject having a supersaturated light source is photographed, the ability to reset the potential of the capacitive element in each column to the black reference potential is insufficient, and resetting to the reference potential is not possible. It becomes insufficient.

  Therefore, in view of such problems, the present invention provides a solid-state imaging device and a driving method thereof that suppress an image defect caused by insufficient ability to reset the potential of a capacitive element to a reference potential.

  In order to achieve the above object, a solid-state imaging device according to the present invention includes a pixel array including a plurality of unit pixels arranged in a matrix, and a row for selecting the unit pixels in units of rows and outputting a signal potential. A selection unit; a capacitor provided for each column of the unit pixels; and a capacitor element that accumulates a signal potential output from the unit pixel selected by the row selection unit; Resetting means for setting to each of the capacitive elements, a transistor inserted between the corresponding capacitive element and a reset potential, and setting the potential of the corresponding capacitive element to a reset potential; An output amplifier that outputs a signal potential accumulated in the capacitive element, and provided corresponding to each of the capacitive elements, and inserted between the corresponding capacitive element and the output amplifier A switch that outputs the signal potential of the corresponding capacitive element to the output amplifier, and the signal potential of the capacitive element corresponding to the switch that is turned on by sequentially selecting the switch and turning it on. A shift register that sequentially outputs to the output amplifier and sequentially sets the potential of the capacitive element corresponding to the transistor that is turned on by sequentially selecting the transistor and turning it on; Features.

  Accordingly, the capacitor elements in each column can be collectively reset (main reset), and the capacitor elements in each column can be sequentially reset (pre-reset) by reset using a transistor. As a result, since the capacitor element can be reset twice, after the signal potential is output and before the signal potential is accumulated in the capacitor element again, the ability to reset the capacitor element potential to the reference potential It is possible to suppress image defects caused by the shortage of.

  The solid-state imaging device and the driving method thereof according to the present invention eliminates a false signal called streaking that occurs due to insufficient ability to reset the potential of the capacitive element of each column to the reference potential when photographing a subject having a supersaturated light source. High-quality images can be obtained. As a result, when a subject having a supersaturated light source with a strong contrast between brightness and darkness is photographed, it is possible to prevent horizontal bands from being generated on the left and right of the subject supersaturated light source in the image.

FIG. 3 is a circuit diagram illustrating a configuration of a portion in the solid-state imaging device according to the first embodiment of the present invention, in which the signal potential output from the pixel unit is output in units of column of unit pixels. 6 is a timing chart illustrating a potential change of SW (N) when a supersaturation signal is input to a pixel unit in the solid-state imaging device of the embodiment. FIG. 5 is a diagram for explaining signal outputs of a plurality of unit pixels when a subject as shown in FIG. 4 is photographed by the solid-state imaging device of the embodiment. FIG. 5 is a diagram for explaining signal outputs of a plurality of unit pixels when a subject as shown in FIG. 4 is photographed by the solid-state imaging device of the embodiment. FIG. 5 is a diagram for explaining signal outputs of a plurality of unit pixels when a subject as shown in FIG. 4 is photographed by the solid-state imaging device of the embodiment. It is a figure which shows the malfunction at the time of image | photographing the to-be-photographed object which has both a supersaturated light source and a dark part in the solid-state imaging device which concerns on a comparative example. 10 is a timing chart showing a potential change of SW (N) when a supersaturation signal is input to the pixel portion of the solid-state imaging device according to Modification Example 1 of the first embodiment of the present invention. FIG. 6 is a diagram for explaining signal outputs of a plurality of unit pixels when a subject as shown in FIG. 4 is photographed by the solid-state imaging device according to the first modification. FIG. 6 is a diagram for explaining signal outputs of a plurality of unit pixels when a subject as shown in FIG. 4 is photographed by the solid-state imaging device according to the first modification. FIG. 6 is a diagram for explaining signal outputs of a plurality of unit pixels when a subject as shown in FIG. 4 is photographed by the solid-state imaging device according to the first modification. It is a timing chart which shows potential change of SW (N) when a supersaturation signal is inputted into a pixel part of a solid imaging device concerning modification 2 of a 1st embodiment of the present invention. It is a circuit diagram which shows the structure of the part in the solid-state imaging device which concerns on the 2nd Embodiment of this invention until the signal electric potential output from the pixel part is output per column of a unit pixel. 6 is a timing chart illustrating a potential change of SW (N) when a supersaturation signal is input to a pixel unit in the solid-state imaging device of the embodiment. FIG. 5 is a diagram for explaining signal outputs of a plurality of unit pixels when a subject as shown in FIG. 4 is photographed by the solid-state imaging device of the embodiment. FIG. 5 is a diagram for explaining signal outputs of a plurality of unit pixels when a subject as shown in FIG. 4 is photographed by the solid-state imaging device of the embodiment. FIG. 5 is a diagram for explaining signal outputs of a plurality of unit pixels when a subject as shown in FIG. 4 is photographed by the solid-state imaging device of the embodiment. It is a circuit diagram which shows the structure of the part in the solid-state imaging device which concerns on the 3rd Embodiment of this invention until the signal electric potential output from the pixel part is output per column of a unit pixel. It is a circuit diagram which illustrates the composition of the portion in the solid-state imaging device concerning a comparative example until the signal potential outputted from the pixel part is outputted per unit pixel column. It is a timing chart which shows the drive method when outputting the signal potential of the unit pixel 1 of the predetermined column in the solid-state imaging device of the comparative example. It is a timing chart which shows potential change of SW (N) when a supersaturation signal is inputted into a pixel part of a solid imaging device of the comparative example. FIG. 5 is a diagram for explaining signal output of a plurality of unit pixels when a subject as shown in FIG. 4 is photographed by a solid-state imaging device of a comparative example. FIG. 5 is a diagram for explaining signal output of a plurality of unit pixels when a subject as shown in FIG. 4 is photographed by a solid-state imaging device of a comparative example. FIG. 5 is a diagram for explaining signal output of a plurality of unit pixels when a subject as shown in FIG. 4 is photographed by a solid-state imaging device of a comparative example. FIG. 5 is a diagram for explaining signal output of a plurality of unit pixels when a subject as shown in FIG. 4 is photographed by a solid-state imaging device of a comparative example. It is a circuit diagram which shows the structure of the solid-state imaging device of a prior art.

  Hereinafter, a solid-state imaging device according to an embodiment of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of a portion in which a signal potential (pixel signal) output from a pixel unit is output in units of columns of unit pixels 1 in the solid-state imaging device according to the first embodiment of the present invention. FIG.

  As shown in FIG. 1, the solid-state imaging device includes a pixel unit (pixel array), a sampling (hereinafter referred to as SP) transistor group, a column memory group, and a first clamp (hereinafter referred to as CP). ) Transistor group, a column selection first shift register (hereinafter referred to as S / R) 8, a column selection switch (hereinafter referred to as SW) group, a horizontal signal line 12, and an output amplifier ( (Hereinafter referred to as AMP) 13, second S / R 14, second CP transistor group, vertical signal line 18, and row selection circuit (not shown).

The pixel portion is composed of a plurality of unit pixels 1 provided in a matrix.
The SP transistor group is configured such that an SP transistor 3 for sampling the signal potential of the unit pixel 1 transmitted in the column direction via the vertical signal line 18 is provided for each column of the unit pixel 1. An SP pulse 2 for driving the SP transistor 3 is input to the gate of the SP transistor 3.

  The column memory group is configured such that the capacitive element 4 is provided for each column of the unit pixels 1. The capacitive element 4 accumulates the signal potential output from the unit pixel 1 selected by the row selection circuit.

  In the first CP transistor group, the first CP transistor 5 for resetting the potential of the capacitive element 4 (SW11) is provided for each column of the unit pixels 1 corresponding to each of the capacitive elements 4. Composed. The first CP transistor 5 is inserted between the corresponding capacitive element 4 and the black reference potential 6, and sets the potential of the corresponding capacitive element 4 to the black reference potential 6. A CP pulse 7 for driving the first CP transistor 5 is input to the gate of the first CP transistor 5. The first CP transistor group is an example of the reset means of the present invention, and the potentials of the capacitive elements 4 are collectively set to the black reference potential 6 as a reset.

  The first S / R 8 includes a flip-flop provided for each column of the unit pixels 1 and corresponds to the SW 11 that is turned on by sequentially selecting the SW 11 in the horizontal direction and turning it on. The signal potential of the capacitive element 4 is sequentially output to the AMP 13. That is, the first S / R 8 drives the SW 11 (supplies a drive pulse to the SW 11) and outputs the signal potential of the unit pixel 1 in a predetermined column to the horizontal signal line 12. A trigger pulse 9 and an S / R clock 10 as a driving clock are input to the first S / R 8.

  The SW group is configured such that SW 11 is provided for each column of unit pixels 1 corresponding to each of the capacitive elements 4. The SW 11 is inserted between the corresponding capacitive element 4 and the AMP 13 and causes the signal potential of the corresponding capacitive element 4 to be output to the AMP 13.

The horizontal signal line 12 transmits the signal potential output via the SW 11 in the horizontal direction.
The AMP 13 outputs the signal potential stored in the capacitive element 4 and transmitted through the horizontal signal line 12.

  In the second CP transistor group, a second CP transistor 16 for pre-resetting the potential of the capacitive element 4 (SW11) is provided for each column of the unit pixels 1 corresponding to each of the capacitive elements 4. Composed. The second CP transistor 16 is inserted between the corresponding capacitive element 4 and the black reference potential 6, and sets the potential of the corresponding capacitive element 4 to the black reference potential 6.

  The second S / R 14 is configured by providing a flip-flop for each column of the unit pixels 1 corresponding to each of the capacitive elements 4, and sequentially selecting the second CP transistors 16 in the horizontal direction. By setting the ON state, the potential of the capacitive element 4 corresponding to the second CP transistor 16 turned ON is sequentially set to the black reference potential 6. In other words, the second S / R 14 individually drives the second CP transistor 16 (supplies a drive pulse to the second CP transistor 16), and sets the potential of the capacitor elements 4 (SW11) in a predetermined column. Pre-reset to black reference potential 6. The second S / R 14 receives the trigger pulse 15 and the S / R clock 10 as a driving clock.

  Note that the shift register including the first S / R 8 and the second S / R 14 is an example of the shift register of the present invention.

  The row selection circuit selects a unit pixel for each row and outputs a signal potential to the vertical signal line 18. The vertical signal line 18 transmits the signal potential in the vertical direction.

  Next, the operation (driving method) of the solid-state imaging device according to the present embodiment will be described with reference to FIGS.

  FIG. 2 is a timing chart showing potential changes of SW11 (hereinafter abbreviated as SW (N)) in the N (N is a natural number) column when a supersaturation signal is input to the pixel portion.

  First, in the vertical shift period, the CP pulse 7 is set to the high level, and the potentials of the SWs 11 (capacitance elements 4) in all the columns are reset to the black reference potential 6 (main reset). Thereafter, the CP pulse 7 is returned to the low level, and the signal potentials of the unit pixels 1 in all the columns are held in the corresponding capacitive elements 4 (SW11) during the period in which the SP pulse 2 is at the high level.

  Next, in response to the trigger pulse 9 being input to the first S / R 8, the SW 11 is sequentially selected by the S / R clock 10, and when SW (N) is selected, the capacity of the Nth column The signal potential held in the element 4 (capacitance element (N)) is output from the AMP 13.

  At this time, in response to the trigger pulse 15 being input to the second S / R 14 with a delay of one clock cycle from the trigger pulse 9, each of the S / R clocks 10 is delayed by one clock cycle from the SW11. The second CP transistors 16 in the column are sequentially selected. When SW11 (SW (N + 1)) in the (N + 1) th column is selected, the second CP transistor 16 in the Nth column is selected and the black reference potential 6 is set to SW (N) (capacitance element (N)). Supplied. This operation is pre-reset. This pre-reset operates only on the SW11 (capacitance element 4) in the selected column. Accordingly, the SW11 of each column is sequentially selected by the first S / R8, and the signal potential of the capacitive element 4 (SW11) of each column is output from the AMP13. At the same time, the clock is generated by the second S / R14. The potential of the capacitive element 4 (SW11) in the column selected by the first S / R 8 (column in which the signal potential is output to the AMP 13) is sequentially pre-reset to the black reference potential 6 with a delay of one cycle. go.

  3A to 3C show a plurality of unit pixels 1 (when surrounded by a dotted line on the line A2 in FIG. 4 between the supersaturated light source and the dark part) when a subject having both the supersaturated light source and the dark part as shown in FIG. It is a figure for demonstrating the signal output of 4 pixels of the supersaturated light source in a boundary, and 4 pixels of a dark part (total 8 pixels). In FIG. 3A, the pixels 1 to 4 indicate the unit pixel 1 in the oversaturated state, and the pixels 5 to 8 indicate the unit pixel 1 in the dark state close to the black reference potential 6.

  First, signal potentials output from the pixels 1 to 8 in different columns are respectively held in the corresponding SW11 (SW (1) to SW (8)).

  Next, as shown in the timing charts of FIGS. 3B and 3C, when the trigger pulse 15 is input with a delay of one cycle of the S / R clock 10 with respect to the trigger pulse 9 input to the first S / R 8. SW (1) is selected at the rising edge of the S / R clock 10, and the signal potential of SW (1) is output from the AMP13. Then, SW (2) is selected at the next rising edge of the S / R clock 10, the signal potential of SW (2) is output from the AMP 13, and for the second CP connected to SW (1). Transistor 16 conducts and only the potential of SW (1) is pre-reset to black reference potential 6.

  With the above procedure, the signal potential of the SW11 in each column is sequentially read from the AMP 13 under the control of the first S / R 8 receiving the supply of the S / R clock 10, and delayed by one clock cycle. The potential of SW11 in each column is sequentially pre-reset to black reference potential 6 one by one.

  Since the outputs from the pixels 5 to 8 are the outputs of the dark unit pixel 1 and are close to the black reference potential 6, SW11 can be reset to the black reference potential 6 by pre-reset. On the other hand, since the outputs of the pixels 1 to 4 are outputs of the unit pixel 1 in a supersaturated state, the SW 11 may not be completely reset to the black reference potential 6 by pre-reset. However, in the next vertical shift period, all the columns are simultaneously reset when the CP pulse 7 is at the high level, so that the SW11 that could not be reset to the black reference potential 6 as in SW (1) to SW (4). In the end, all the SW11 (SW (1) to SW (8)) are reset to the black reference potential 6. This reset by the CP pulse 7 in the vertical shift period resets all the columns simultaneously, whereas the pre-reset sequentially resets each column one by one. Therefore, there are advantages that the load such as the load capacity at the time of pre-reset is light and the reset period is short. In addition, even if the corresponding SW 11 cannot be reset to the black reference potential 6 in the pre-reset period when the oversaturation signal is reset or the like, even if the potential becomes a little higher than the black reference potential 6, the next vertical shift period In this reset by the CP pulse 7 in FIG. 4, the black reference potential 6 can be sufficiently reset. In other words, the state of the signal potential of the SW11 in each column is determined by performing the reset twice, that is, the pre-reset for each column in the signal output period and the main reset performed simultaneously for all the columns in the vertical shift period. Even if it is, the black reference potential 6 can be reset.

  As described above, in the solid-state imaging device according to this embodiment, the second S / R 14 and the second CP transistor group are added so that the reset operation can be performed in units of columns. In the signal output period, the SW 11 of each column is sequentially selected in the first S / R 8 and the signal potential of the capacitive element 4 is output from the AMP 13, and the signal is output in the second S / R 14. The capacitive element 4 (SW11) from which the potential is output is selected and pre-reset to the black reference potential 6 is performed. Further, during the subsequent vertical shift period, the main reset to the black reference potential 6 is performed with the CP pulse 7 to surely reset the potential of the capacitive element 4 (SW11) in each column to the black reference potential 6. As a result, by compensating for the shortage of capacity at the time of this reset, it is possible to prevent the occurrence of horizontal bands that occur on the left and right sides of the supersaturated light source called streaking.

  Note that the solid-state imaging device according to the present embodiment has a configuration in which the second S / R 14 operates with a delay of several clocks from the first S / R 8. However, the solid-state imaging device further includes a comparison circuit that starts supplying a trigger pulse to the second S / R 14 when the output of the AMP 13 is equal to or greater than an arbitrary threshold value, and the second S / R 14 is output only for a predetermined period. You may have the structure which operates. In other words, the configuration may be such that the output of the AMP 13 is input to a comparator or the like, and the comparator output and the trigger pulse 15 that outputs a high level above an arbitrary threshold value are selectively output by the AND circuit. According to this configuration, when shooting a subject without a supersaturated light source that causes streaking, the second S / R 14 can be stopped to reduce power consumption.

  In the solid-state imaging device according to the present embodiment, both the first CP transistor 5 and the second CP transistor 16 are connected to the same fixed reference potential (black reference potential), and the pre-reset and the main reset are performed. In any case, the potential of the capacitive element 4 (SW11) is reset to the same fixed reference potential (black reference potential 6). However, the fixed reference potential connected to the second CP transistor 16 is different from the fixed reference potential set by the first CP transistor group, and the potential of the capacitor 4 (SW11) is fixed differently in the pre-reset and the main reset. It may be reset to the reference potential. For example, by setting the reference potential at the pre-reset higher than the reference potential at the main reset, the potential at the pre-reset of the capacitor elements 4 (SW11) in all the columns can be set higher, and the pre-reset is insufficient. Even if the predetermined reference potential is not reached, it can be made closer to the predetermined reference potential by this reset.

(Modification 1)
Hereinafter, another driving method of the solid-state imaging device (FIG. 1) according to the first embodiment of the present invention will be described using the first modification.

  FIG. 5 is a timing chart showing a potential change of SW (N) when a supersaturation signal is input to the pixel portion of the solid-state imaging device according to this modification.

  First, in the vertical shift period, the CP pulse 7 is set to the high level, and the potentials of the SWs 11 (capacitance elements 4) in all the columns are fully reset to the black reference potential 6. Thereafter, the CP pulse 7 is returned to the low level, and the signal potentials of the unit pixels 1 in all the columns are held in the corresponding capacitive elements 4 (SW11) during the period in which the SP pulse 2 is at the high level.

  Next, in response to the trigger pulse 9 being input to the first S / R 8, the SW 11 is sequentially selected by the S / R clock 10, and when SW (N) is selected, the capacitive element (N) The signal potential held at (SW (N)) is output from the AMP 13.

  At this time, in response to the trigger pulse 15 being input to the second S / R 14 with a delay of two clock cycles from the trigger pulse 9, the S / R clock 10 is delayed with respect to the selection of the SW 11 by two clock cycles. Thus, the second CP transistor 16 in each column is sequentially selected. When SW11 (SW (N + 2)) in the N + 2th column is selected, the second CP transistor 16 in the Nth column is selected, and the capacitor element (N) (SW (N)) is pre-reset. Therefore, an interval of one clock is generated between the selection of SW (N) and the pre-reset of the capacitor element (N).

  6A to 6C show a plurality of unit pixels 1 (a supersaturated light source and a dark part surrounded by dotted lines on the line A2 in FIG. 4) when a subject having both a supersaturated light source and a dark part as shown in FIG. Is a diagram for explaining the signal output of a total of 8 pixels including 4 pixels of a supersaturated light source and 4 pixels in a dark portion at the boundary of In FIG. 6A, the pixels 1 to 4 indicate the unit pixel 1 in the oversaturated state, and the pixels 5 to 8 indicate the unit pixel 1 in the dark state close to the black reference potential 6.

  First, signal potentials output from the pixels 1 to 8 in different columns are respectively held in the corresponding SW11 (SW (1) to SW (8)).

  Next, as shown in the timing charts of FIGS. 6B and 6C, when the trigger pulse 15 is input after being delayed by two cycles of the S / R clock 10 with respect to the trigger pulse 9 input to the first S / R 8. SW (1) is selected at the rising edge of the S / R clock 10, and the signal potential of SW (1) is output from the AMP13. Then, SW (2) is selected at the next rising edge of the S / R clock 10, and the signal potential of SW (2) is output from the AMP 13. At that time, SW (1) continues to hold the supersaturation potential. It is in the state. Further, SW (3) is selected at the next rising edge of the S / R clock 10, the signal potential of SW (3) is output from the AMP 13, and for the second CP connected to SW (1). Transistor 16 conducts and only the potential of SW (1) is pre-reset to black reference potential 6.

  As described above, an interval of one clock is generated between the selection of SW11 and the pre-reset, and the SW 11 selected at the same time (clock rise) and the pre-reset SW 11 are not adjacent to each other. One row is separated (provided with one SW 11 in between).

  As described above, according to the driving method of the present modification, the input timing of the trigger pulse 15 is delayed by two cycles or more of the S / R clock 10 with respect to the input timing of the trigger pulse 9. Therefore, since the pre-reset is performed at intervals of 1 clock after the selection of the SW 11, the pre-reset cannot be effectively performed due to the influence of switching, or the pre-reset is performed next to the selected SW 11. Therefore, it is possible to prevent the noise caused by the pre-reset from being generated and affecting the output of the selected SW 11.

  In the driving method of the present modification, the second S / R 14 delays two clocks from the selection of the SW 11 and sets the potential of the capacitive element 4 corresponding to the selected SW 11 to the black reference potential 6. The CP transistor 16 is selected. However, the interval between the selection of SW11 and the selection of the second CP transistor 16 is not limited to two clocks as long as it is one clock or more.

(Modification 2)
Hereinafter, another driving method of the solid-state imaging device (FIG. 1) according to the first embodiment of the present invention will be described using a second modification.

  FIG. 7 is a timing chart showing the potential change of SW (N) when a supersaturation signal is input to the pixel portion of the solid-state imaging device according to this modification.

  First, in the vertical shift period, the CP pulse 7 is set to the high level, and the potentials of the SWs 11 (capacitance elements 4) in all the columns are reset to the black reference potential 6. Thereafter, the CP pulse 7 is returned to the low level, and the signal potentials of the unit pixels 1 in all the columns are held in the corresponding capacitive elements 4 (SW11) during the period in which the SP pulse 2 is at the high level.

  Next, in response to the trigger pulse 9 being input to the first S / R 8, the SW 11 is sequentially selected by the S / R clock 10, and when SW (N) is selected, the capacitive element (N) The signal potential held at (SW (N)) is output from the AMP 13.

  At this time, in response to the trigger pulse 15 being input to the second S / R 14 with a delay of one clock cycle from the trigger pulse 9, each of the S / R clocks 10 is delayed by one clock cycle from the SW11. The second CP transistors 16 in the column are sequentially selected. When SW (N + 1) is selected, the second CP transistor 16 in the Nth column is selected, and SW (N) (capacitance element (N)) is pre-reset.

  Here, since the trigger pulse 15 has a width corresponding to two clock cycles, the pre-reset period by the second S / R 14 is equal to two clock cycles, which is a pre-reset compared to the driving method of the solid-state imaging device according to the present embodiment. The period is doubled. Therefore, pre-reset is twice as effective.

  As described above, according to the driving method of the present modification, the pre-reset period becomes long. Even when the capacitive element 4 that accumulates the signal potential of the unit pixel 1 in the oversaturated state cannot be sufficiently reset, the reset period can be increased by expanding the selection period of the trigger pulse 15 in units of clocks as described above. Or the potential of the capacitor 4 (SW11) can be reset to the black reference potential 6 only by pre-reset. When the reset is performed only by the pre-reset, this reset by the CP pulse 7 in the vertical shift period becomes unnecessary. As a result, the period during which the CP pulse 7 is at a high level in the vertical shift period can be shortened, and the width of a pulse required in the vertical shift period such as a vertical shift can be increased, or the vertical shift period itself can be shortened.

  In the driving method of the present modification, a pulse different from the trigger pulse 9 is input from the outside as the trigger pulse 15. However, a third S / R configured by an arbitrary number of stages and driven by the S / R clock 10 is provided in the same manner as the first S / R 8 and the second S / R 14, and the third S / R is provided with the second S / R. 1 S / R8 trigger pulse (trigger pulse 9) is input, and the pulse obtained by shifting the first S / R8 trigger pulse by an arbitrary number of clocks is used for the second S / R14. The effect is not changed even if it is configured to be input as a trigger pulse.

  In the driving method of the present modification, the second S / R 14 selects one second CP transistor 16 only for a period twice as long as the period for selecting one SW 11. However, the period during which the second CP transistor 16 is selected is not limited to twice as long as the period is longer by at least one clock than the period during which one SW 11 is selected.

(Second Embodiment)
FIG. 8 is a circuit diagram showing a configuration of a part in which the signal potential (pixel signal) output from the pixel unit is output in units of columns of the unit pixel 1 in the solid-state imaging device according to the second embodiment of the present invention. FIG.

  As shown in FIG. 8, this solid-state imaging device includes a pixel unit including a unit pixel 1, an SP transistor group including an SP transistor 3, and a column memory group including a capacitor element 4. The first CP transistor group including the first CP transistor 5, the S / R 28, the SW group, the horizontal signal line 12, the AMP 13, the second CP transistor group, and the vertical signal line 18 and a row selection circuit (not shown).

  The SP pulse 2 is input to the gate of the SP transistor 3, and the CP pulse 7 is input to the gate of the first CP transistor 5.

  The SW group is configured such that SW 31 is provided for each column of unit pixels 1 corresponding to each of the capacitive elements 4. The SW 31 is inserted between the corresponding capacitive element 4 and the AMP 13 and causes the signal potential of the corresponding capacitive element 4 to be output to the AMP 13.

  The S / R 28 is configured by providing two flip-flops corresponding to each of the capacitive elements 4 for each column of the unit pixels 1. The S / R 28 is turned on by sequentially selecting the SW 31 in the horizontal direction and turning it on. The signal potential of the capacitive element 4 corresponding to the SW 31 in the state is sequentially output to the AMP 13. That is, the S / R 28 drives the SW 31 (supplies a drive pulse to the SW 31) and outputs the signal potential of the unit pixel 1 in a predetermined column to the horizontal signal line 12.

  The S / R 28 sequentially selects the second CP transistor 34 in the horizontal direction and turns it on so that the capacitance element 4 (SW31) corresponding to the second CP transistor 34 turned on is turned on. The potential is sequentially set to the black reference potential 6. In other words, the S / R 28 drives the second CP transistor 34 (supplying a drive pulse to the second CP transistor 34), and precharges the potential of the capacitive element 4 (SW31) in a predetermined column to the black reference potential 6. Reset.

  The S / R 28 is supplied with one trigger pulse 29 and an S / R clock 30 as a drive clock. The S / R 28 is driven by the drive pulse for driving the SW 31 and the first pulse based on the one trigger pulse 29 and the S / R clock 30. A drive pulse for driving the second CP transistor 34 is generated.

  The S / R 28 selects the SW 31 and the second CP transistor 34 provided corresponding to the same capacitive element 4 in a predetermined period of the S / R clock 30. At this time, the period in which the SW 31 is selected and the period in which the second CP transistor 34 is selected are each half of a predetermined one period of the S / R clock 30. Therefore, for a given column, the signal potential of the capacitive element 4 (SW31) is output to the AMP 13 in the half cycle of the S / R clock 30 that drives the S / R 28, and the potential of the capacitive element 4 (SW31) in the remaining half cycle. Black reference potential 6 is set.

  In the second CP transistor group, a second CP transistor 34 for pre-resetting the potential of the capacitive element 4 (SW 31) is provided for each column of the unit pixels 1 corresponding to each of the capacitive elements 4. Composed. The second CP transistor 34 is inserted between the corresponding capacitive element 4 and the black reference potential 6, and sets the potential of the corresponding capacitive element 4 to the black reference potential 6.

  Next, the operation of the solid-state imaging device according to the present embodiment will be described with reference to FIGS. 9 and 10A to 10C.

  FIG. 9 is a timing chart showing the potential change of SW (N) in the Nth column when a supersaturation signal is input to the pixel portion.

  First, in the vertical shift period, the CP pulse 7 is set to the high level, and the potentials of the SWs 31 (capacitance elements 4) in all the columns are fully reset to the black reference potential 6. Thereafter, the CP pulse 7 is returned to the low level, and the signal potentials of the unit pixels 1 in all the columns are held in the corresponding capacitive elements 4 (SW31) during the period in which the SP pulse 2 is at the high level.

  Next, in response to the trigger pulse 29 being input to the S / R 28, the SW 31 is sequentially selected at the rising edge of the S / R clock 30, and when the SW (N) is selected, the capacitive element (N) The signal potential held at (SW (N)) is output from the AMP 13.

  At this time, the second CP transistor 34 in the Nth column is selected (conducted) at the falling edge of the S / R clock 30 with a delay of a half cycle of the clock from the selection of SW (N), and the black reference potential 6 becomes the capacitive element. (N) (SW (N)) is supplied to perform pre-reset. The selection period of SW (N) is one cycle of the S / R clock 30, but the signal potential of the capacitive element (N) (SW (N)) is output from the AMP 13 while the S / R clock 30 is at the high level. In the low level period after the falling edge of the S / R clock 30, the potential of the capacitive element (N) (SW (N)) is pre-reset.

  10A to 10C show a plurality of unit pixels 1 (when surrounded by a dotted line on the line A2 in FIG. 4 between the supersaturated light source and the dark part) when a subject having both the supersaturated light source and the dark part as shown in FIG. It is a figure for demonstrating the signal output of 4 pixels of the supersaturated light source in a boundary, and 4 pixels of a dark part (total 8 pixels). In FIG. 10A, the pixels 1 to 4 indicate the unit pixel 1 in the oversaturated state, and the pixels 5 to 8 indicate the unit pixel 1 in the dark state close to the black reference potential 6.

  First, the signal potentials output from the pixels 1 to 8 in different columns are respectively held in the corresponding SW31 (SW (1) to SW (8)).

  Next, as shown in the timing charts of FIGS. 10B and 10C, SW (1) is selected at the rising edge of the S / R clock 30, and the signal potential of SW (1) is output from the AMP13. Then, a signal for conducting the second CP transistor 34 is output from the S / R 28 at the fall of the S / R clock 30, and only the signal potential of SW (1) is output during the period when the S / R clock 30 is at the low level. Pre-reset to black reference potential 6.

  In the above procedure, the signal potentials of the SW31 in each column are sequentially read out from the AMP 13 in the clock cycle under the control of the S / R 28 that is supplied with the S / R clock 30, and delayed by a half cycle of the clock. In the low level period after the falling edge of the clock, the potential of the SW 31 in each column is sequentially pre-reset to the black reference potential 6 one by one.

  Since the output from the pixels 5 to 8 is the output of the dark unit pixel 1 and is close to the black reference potential 6, SW31 can be reset to the black reference potential 6 by pre-reset. On the other hand, since the pixels 1 to 4 are outputs of the unit pixel 1 in a supersaturated state, the SW 31 may not be completely reset to the black reference potential 6 by pre-reset. However, in the next vertical shift period, all the columns are reset at the same time when the CP pulse 7 is at the high level, so that the SW31 that could not be reset to the black reference potential 6 as in SW (1) to SW (4). In the end, all the SW11 (SW (1) to SW (8)) are reset to the black reference potential 6.

  In the solid-state imaging device according to the first embodiment, two S / Rs of a first S / R and a second S / R are provided, and the two S / Rs are driven in synchronization in consideration of a clock tree. There was a need. However, in the solid-state imaging device of this embodiment, since there is only one S / R, it is not necessary to perform driving considering the clock tree. However, in the configuration of the solid-state imaging device of this embodiment, when the signal potential of SW (N) is output from the AMP 13, the signal output period becomes a half cycle of the clock, and the pre-reset period also becomes a half cycle of the clock. However, by adopting a configuration in which the pre-reset signal is extracted from the S / R 28 in the (N + 1) th column, the pre-reset is performed with a delay of 1.5 cycles, so that the signal potential of the capacitive element 4 (SW31) in the N-th column is conventional Can be set to one period of the clock. It is also possible to cope with this by adjusting the CDS (correlated double sampling) timing of the analog front end (AFE) and applying the CDS with a half period as compared with the solid-state imaging device of the first embodiment. .

  As described above, the solid-state imaging device according to the present embodiment sequentially selects and pre-resets the SW 31 by using the rising and falling edges of the S / R clock 30 supplied to the S / R 28. That is, in the solid-state imaging device, after the S31 of the S / R clock 30 is in the high level and the SW31 in the predetermined column is selected and the signal potential is output from the AMP 13, the S / R clock 30 is selected in the period of the low level. Further, the pre-reset to the black reference potential 6 is performed on the capacitor elements 4 in the predetermined column. Therefore, the two S / Rs operate in parallel as in the solid-state imaging device according to the first embodiment, and there is no delay difference due to the layout and other effects. In addition, by correcting the lack of capability at the time of resetting by the method of performing the main reset to the black reference potential 6 with the CP pulse 7 in the vertical shift period, it is possible to prevent the occurrence of horizontal bands, called streaking, on the left and right sides of the supersaturated light source.

(Third embodiment)
FIG. 11 is a circuit diagram showing a configuration of a portion where a signal potential (pixel signal) output from the pixel unit is output in units of columns of the unit pixel 1 in the solid-state imaging device according to the third embodiment of the present invention. FIG.

  As shown in FIG. 11, this solid-state imaging device includes a pixel unit configured by unit pixels 1, an SP transistor configured by SP transistor 3, and a column memory group configured by capacitive element 4, The first CP transistor group including the first CP transistor 5, the S / R 48, the SW group, the horizontal signal line 12, the AMP 13, the second CP transistor group, and the vertical signal line 18 and a row selection circuit (not shown).

  The SP pulse 2 is input to the gate of the SP transistor 3, and the CP pulse 7 is input to the gate of the first CP transistor 5.

  The SW group is configured such that SW 51 is provided for each column of unit pixels 1 corresponding to each of the capacitive elements 4. The SW 51 is inserted between the corresponding capacitive element 4 and the AMP 13 and causes the signal potential of the corresponding capacitive element 4 to be output to the AMP 13.

  The S / R 48 is configured by providing a flip-flop for each column of the unit pixels 1 corresponding to each of the capacitive elements 4, and sequentially selecting the SW 51 in the horizontal direction to turn it on. The signal potential of the capacitive element 4 corresponding to the SW 51 thus made is sequentially output to the AMP 13. That is, the S / R 48 drives the SW 51 (supplies a drive pulse to the SW 51) to output the signal potential of the unit pixels 1 in a predetermined column to the horizontal signal line 12.

  The S / R 48 selects the second CP transistor 54 sequentially in the horizontal direction and turns it on so that the potential of the capacitive element 4 corresponding to the second CP transistor 54 turned on is black. The reference potential 6 is sequentially set. In other words, the S / R 48 drives the second CP transistor 54 (supplying a drive pulse to the second CP transistor 54), and precharges the potential of the capacitor 4 (SW51) in a predetermined column to the black reference potential 6. Reset.

  A trigger pulse 49 and an S / R clock 50 are input to the S / R 48 as a driving clock. In the S / R 48, the output of the flip-flop of the Nth column is connected to SW51 (SW (N)) of the Nth column, and the output of the flip-flop of the N + 1th column is connected to the second CP transistor 54 of the Nth column. The With this configuration, the S / R 48 supplies the first drive pulse (the output pulse of the Nth column flip-flop) to the predetermined SW51 and then selects the predetermined SW51, and then the second drive pulse (N + 1th column). Output flip-flop) is supplied to a SW 51 different from the predetermined SW 51 to select a SW 51 different from the predetermined SW 51, and a second drive pulse is provided corresponding to the same capacitive element 4 as the predetermined SW 51. The predetermined second CP transistor 54 is selected by supplying the predetermined second CP transistor 54 (the second CP transistor 54 in the Nth column).

  In the second CP transistor group, a second CP transistor 54 for pre-resetting the potential of the capacitive element 4 (SW 51) is provided for each column of the unit pixels 1 corresponding to each of the capacitive elements 4. Composed. The second CP transistor 54 is inserted between the corresponding capacitive element 4 and the black reference potential 6, and sets the potential of the corresponding capacitive element 4 to the black reference potential 6.

  The operation of the solid-state imaging device according to the present embodiment is the same as the operation of the solid-state imaging device according to the first and second embodiments.

  That is, first, in the vertical shift period, the CP pulse 7 is set to the high level, and the potentials of the SWs 51 (capacitance elements 4) in all the columns are fully reset to the black reference potential 6. Thereafter, the CP pulse 7 is returned to the low level, and the signal potentials of the unit pixels 1 in all the columns are held in the corresponding capacitive elements (SW51) during the period in which the SP pulse 2 is at the high level.

  Next, in response to the trigger pulse 49 being input to the S / R 48, the SW 51 is sequentially selected at the rising edge of the S / R clock 50, and when the SW (N) is selected, the capacitive element (N). The signal potential held at (SW (N)) is output from the AMP 13. When the low level is supplied to the second CP transistor 54 in the Nth column, the signal potential is continuously held in the capacitive element (N) (SW (N)).

  At this time, when SW51 (SW (N + 1)) in the (N + 1) th column is selected at the rise of the S / R clock 50, the second CP transistor in the Nth column from the (N + 1) th flip-flop in S / R48. A high level is supplied to 54, and the potential of the capacitive element (N) (SW (N)) is pre-reset to the black reference potential 6. Therefore, a time difference corresponding to one cycle of the S / R clock 50 occurs between the selection of the SW 51 and the pre-reset for a predetermined column.

  In the solid-state imaging device having the above-described configuration, it is not necessary to separately provide a pre-reset S / R as in the solid-state imaging device of the first embodiment, and the pre-reset S / R is not required as in the solid-state imaging device of the second embodiment. It is not necessary to separately provide a flip-flop that operates at the falling edge of the clock for using the falling edge of the S / R clock 50 for resetting.

  In the solid-state imaging device having the above configuration, SW (N) is pre-reset by the output of the flip-flop of the (N + 1) th column of S / R 48 after selecting SW (N). However, SW (N) may be pre-reset by the output of the flip-flop of the (N + 2) th column of S / R48.

  In the solid-state imaging device having the above-described configuration, the S / R 48 supplies the first drive pulse (the output pulse of the flip-flop in the Nth column) to the predetermined SW51 (SW (N)), thereby the predetermined SW51. After selecting the second drive pulse (output pulse of the flip-flop of the (N + 1) th column) and the third drive pulse (output pulse of the flip-flop of the (N + 2) th column), two SW51 (SW (N + 1) ) And SW (N + 2)) to select two SW51 different from the predetermined SW51, and the solid-state imaging device further outputs the OR output of the second drive pulse and the third drive pulse to the predetermined SW51. And a predetermined second CP transistor 54 (second CP in the Nth column) provided corresponding to the same capacitive element 4 (capacitive element (N)). It may include a computing circuit for selecting a predetermined second CP transistor 54 by supplying to the transistor 54). In this case, the second CP transistor 54 is turned on by the OR outputs of a plurality of flip-flops such as the OR outputs of the flip-flops in the N + 1 and N + 2 columns of the S / R 48, and SW (N) is pre-reset. As a result, the pre-reset period can be extended.

  As described above, according to the solid-state imaging device according to the present embodiment, the S / R 48 selects the SW 51 in the M column (M may be a natural number and N = M in some cases) at the output of the N-th flip-flop. Then, the signal potential is output from the AMP 13, the second CP transistor 54 in the M column is turned on by the output of the flip-flop in the (N + 1) th column, and the potential of the capacitive element 4 (SW51) in the M column is set to the black reference potential. Pre-reset to 6. Therefore, an S / R is provided separately from the S / R 48 that drives the SW 51 for pre-resetting the black reference potential 6, or the number of falling-synchronous flip-flops is increased in order to use the falling edge of the clock for the pre-reset. Pre-reset can be performed without In addition, in the vertical shift period after the pre-reset, the main reset to the black reference potential 6 is performed with the CP pulse 7 so that the potentials of the capacitive elements 4 (SW51) in the respective columns are reliably reset to the black reference potential 6. As a result, by compensating for the shortage of capacity at the time of this reset, it is possible to prevent the occurrence of horizontal bands that occur on the left and right sides of the supersaturated light source called streaking.

(Comparative example)
Hereinafter, solid-state imaging devices to be compared with the solid-state imaging devices of the first to third embodiments of the present invention will be described using comparative examples.

  FIG. 12 is a circuit diagram illustrating the configuration of a portion in the solid-state imaging device (MOS type image sensor) according to this comparative example until the signal potential output from the pixel unit is output in units of columns of the unit pixel 1. .

  As shown in FIG. 12, this solid-state imaging device includes a pixel unit composed of unit pixels 1, an SP transistor group composed of SP transistors 3, and a column memory group composed of capacitive elements 4. A CP transistor group including the first CP transistor 5, an S / R 78, a SW group, a horizontal signal line 12, an AMP 13, a vertical signal line 18, and a row selection circuit (not shown). Prepare.

  The SP pulse 2 is input to the gate of the SP transistor 3, and the CP pulse 7 is input to the gate of the first CP transistor 5. A black reference potential 6 is connected to the first CP transistor 5.

The SW group is configured by providing the SW 81 for each column of the unit pixels 1.
The S / R 78 is configured by providing a flip-flop for each column of the unit pixels 1, and drives the SW 81 provided for each column of the unit pixels 1 (supplying a drive pulse to the SW 81). Is output to the horizontal signal line 12. A trigger pulse 79 and an S / R clock 80 are input to the S / R 78 as a driving clock.

  In the solid-state imaging device of FIG. 12 having the above-described configuration, the capacitive element 4 is operated by operating the first CP transistor 5 with the CP pulse 7 so that all the capacitive elements 4 (SW81) are simultaneously supplied with the black reference potential 6. Is reset once. A signal potential corresponding to the amount of light received is generated in the unit pixel 1, and the SP transistor 3 receives the operation by the SP pulse 2, and the SP transistor 3 collects the generated signal potential in units of rows in a period in which the SP pulse 2 is at a high level. The capacitor 4 (SW81) holds the capacitor. The S / R 78 sequentially selects the SW 81 of each column with an S / R clock 80 starting from an arbitrary trigger pulse 79, and the signal potential of the capacitive element 4 (SW 81) is output from the AMP 13 through the horizontal signal line 12.

  FIG. 13 is a timing chart showing a driving method when outputting the signal potential of the unit pixels 1 in a predetermined column in the solid-state imaging device of FIG.

  First, the signal potential output from the unit pixel 1 is held in the capacitive element 4 by setting the SP pulse 2 to the high level and turning on the SP transistor 3. At this time, the CP pulse 7 is set to the high level to connect the capacitive element 4 (SW81) to the black reference potential 6, and the potential of the capacitive element 4 (SW81) in each column is set to the black reference potential during the period in which the CP pulse 7 is at the high level. The signal potential of the unit pixel 1 in each column is held in the capacitive element 4 so as to be reset to 6.

  Next, SW81 is sequentially selected in units of one column by S / R 78, and the signal potential of the capacitive element 4 (SW81) in the selected column is sequentially output from AMP13.

  According to the above driving method, the potentials of the capacitive elements 4 (SW81) of all the columns are once reset to the black reference potential 6 by the CP pulse 7, and the signal potential is set in the form of a potential based on the black reference potential 6. Therefore, a uniform signal potential with no variation in the reference level between columns can be obtained. On the other hand, in the case of a solid-state imaging device that does not have a structure that is reset to the black reference potential 6, the reference potential varies from column to column, so that the variation in each column is displayed as a vertical line in the image.

  In such a solid-state imaging device according to the comparative example, the first CP transistor 5 is turned on by the CP pulse 7 in order to reset the potential of the capacitive element 4 (SW81) of each column to the black reference potential 6. The capacitor elements 4 (SW81) in each column are simultaneously reset. However, resetting to the black reference potential 6 is insufficient for the following reason.

  The first reason is that the unit pixel 1 has a large number of columns and a large load capacity. The second reason is that the line connecting the black reference potential 6 and the first CP transistor 5 is long and the load capacitance is large. The third reason is that the supply capability of the black reference potential 6 is small. The fourth reason is that the capability of the first CP transistor 5 is small. The fifth reason is that the high level (reset) period of the CP pulse 7 is short, and a sufficient time to reach the black reference potential 6 cannot be secured.

  The circuit design of the solid-state imaging device is performed so that the characteristic failure due to the above first to fifth reasons does not occur. However, in that case, the circuit scale and area are increased, which is disadvantageous in terms of cost. Also, in order to cope with higher speeds for improving the continuous shooting performance, the reset period must be shortened, and in the case of large format sensors for single-lens cameras that tend to increase the load capacity, the load capacity is reduced. Is difficult. Therefore, in the solid-state imaging device of the comparative example of FIG. 12, there may be variations in each column in resetting to the black reference potential 6 depending on the amount of incident light.

  Details of the characteristic failure of the solid-state imaging device of the comparative example of FIG. 12 will be described below with reference to the drawings.

FIG. 4 is a diagram showing a characteristic failure (problem) in the solid-state imaging device of the comparative example of FIG.
When a subject such as that shown in FIG. 4A is photographed by the solid-state imaging device shown in FIG. 12, the output level of the dark portion in the horizontal line indicated by A1 and A2 in FIGS. 4A and 4B is the same. In this case, in the sensor output image shown in FIG. 4B, the output level of the dark part on the left and right of the supersaturated light source of A2 is larger than the output level of the dark part of A1, and strip-like false signals are generated on the left and right of the supersaturated light source. May occur. This false signal is called streaking. Note that the subject as shown in FIG. 4A has a supersaturated light source in the center of the background of the dark part, and in an actual case, this corresponds to a case where a window where bright outside light enters from a dark room.

Next, the reason why streaking occurs will be described with reference to FIGS.
FIG. 14 is a timing chart showing a potential change of SW (N) when a supersaturation signal is input to the pixel portion.

  The driving of the solid-state imaging device according to this comparative example is roughly divided into two periods, a vertical shift period and a signal output period. In the vertical shift period, row scanning of the unit pixel 1 and potential reset are mainly performed, and no signal potential is output. In the signal output period, the signal potential held in the capacitive element 4 (SW81) in units of rows of the unit pixel 1 is driven by the S / R 78 and sequentially output from the AMP 13.

  In the driving of the solid-state imaging device according to this comparative example, first, the row of the unit pixel 1 is selected in the vertical shift period, and the signal potential of the unit pixel 1 in the selected row is set to the capacity in the period of the high level of the SP pulse 2. It is held in SW 81 through element 4. At this time, the potential of the capacitive element 4 (SW81) is reset to the black reference potential 6 while the CP pulse 7 is at the high level, and after the CP pulse 7 returns to the low level, the signal is output when the SP pulse 2 is at the high level. The potential is held in the capacitive element 4 (SW81).

  Next, in response to the trigger pulse 79 being input to the S / R 78, the SW 81 is sequentially selected by the S / R clock 80, SW (N) is selected, and the capacitive element (N) (SW ( The signal potential held in N)) is output from the AMP 13. Thereafter, the potential of the capacitive element (N) (SW (N)) is again set by the CP pulse 7 before the signal potential of the next row of unit pixels 1 is held in the capacitive element (N) (SW (N)). Reset to black reference potential 6.

  Here, if the signal potential of the capacitive element (N) (SW (N)) is small, the potential of the capacitive element (N) (SW (N)) can be easily set to the black reference in the period when the next CP pulse 7 is at a high level. Although the potential can be reset to 6, when the signal potential of the capacitive element (N) (SW (N)) is large as in the case of a supersaturated light source, the capacitive element (N) (SW (N)) is reset during the reset period. There is a case where the potential does not return to the black reference potential 6.

  15A and 15B are diagrams for explaining signal outputs of a plurality of unit pixels 1 (eight pixels surrounded by a dotted line on the A1 line in FIG. 4) when the subject in FIG. 4 is photographed. 15C and 15D are diagrams for explaining potential changes of a plurality of unit pixels 1 (eight pixels surrounded by a dotted line on the A2 line in FIG. 4) when the subject of FIG. 4 is photographed. 15C and 15D, the pixels 1 to 4 indicate the unit pixel 1 in the supersaturated state, and the pixels 5 to 8 indicate the unit pixel 1 in the dark state close to the black reference potential 6.

  As shown in FIGS. 15A and 15B, when all eight pixels are in the dark state and the levels of the eight SWs 81 provided corresponding to the eight pixels are uniformly equal to the black reference potential 6, the CP pulse 7 By simultaneously resetting the eight SWs 81, the eight SWs 81 can be uniformly reset to the black reference potential 6. However, as shown in FIG. 15C and FIG. 15D, 8 pixels include a supersaturated state and a dark state, and 8 SW81 levels provided corresponding to 8 pixels include a black reference potential 6 and a supersaturated level. In this case, even if the eight SWs 81 are simultaneously reset by the CP pulse 7, the eight SWs 81 cannot be reset to the black reference potential 6 uniformly. This is because, as shown in FIG. 14, the reset capability is used up to reset the oversaturated potential SW 81, so in addition to the four SW 81 provided corresponding to the supersaturated pixels 1 to 4, This is because even the four SWs 81 provided corresponding to the pixels 5 to 8 in the dark state cannot be completely reset to the black reference potential 6. In particular, when the reset to the black reference potential 6 is insufficient for the first to fifth reasons, a problem that all eight SWs 81 cannot be reset to the black reference potential 6 becomes significant. At this time, the reset potential in the SW 81 provided corresponding to the pixels 5 to 8 in the dark state on the A2 line in FIG. 4 corresponds to the pixels 1 to 8 in the dark state on the A1 line in FIG. It becomes larger than the potential after reset in SW81 provided. Therefore, the signal potential of the unit pixel 1 in the dark state in the line including the unit pixel 1 in the supersaturated state increases, and streaking that causes a white band in the image occurs.

  In addition, since the reset by the CP pulse 7 is simultaneously performed on the SWs 81 of all the columns, the optical black area (OB portion) may be affected and a false signal may be generated. In this case, when OB clamping is performed with AFE, the OB level of the unit pixel 1 on the A2 line in FIG. 4 is higher than the optical black level (OB level) of the unit pixel 1 on the A1 line in FIG. Black sinking occurs in the black level in signal processing after AFE, and another factor of streaking that becomes a black belt occurs.

  As described above, the solid-state imaging device and the driving method thereof according to the present invention have been described based on the embodiment, but the present invention is not limited to this embodiment. The present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention.

  The present invention is useful for a solid-state imaging device and a driving method thereof, and particularly useful as a high pixel MOS type solid-state imaging device and a driving method thereof.

1 unit pixel 2 SP pulse 3 SP transistor 4 capacitive element 5 first CP transistor 6 black reference potential 7 CP pulse 8 first S / R
9, 15, 29, 49, 79 Trigger pulse 10, 30, 50, 80 S / R clock 11, 31, 51, 81 SW
12 Horizontal signal line 13 AMP
14 Second S / R
16, 34, 54 Second CP transistor 18, 105 Vertical signal line 28, 48, 78 S / R
DESCRIPTION OF SYMBOLS 101 Pixel MOS transistor 102 Vertical scanning circuit 103 Vertical selection line 104 Power supply line 108 Horizontal scanning circuit 109 Horizontal MOS switch 110 Horizontal signal line 113 Operation | movement MOS switch 114 Load capacity element 115 Load capacity reset MOS switch

Claims (11)

A pixel array composed of a plurality of unit pixels arranged in a matrix;
Row selection means for selecting the unit pixel in units of rows and outputting a signal potential;
A capacitive element that is provided for each column of the unit pixels and accumulates a signal potential output from the unit pixel selected by the row selection unit;
Reset means for collectively setting the respective potentials of the capacitive elements to a reset potential;
A transistor provided corresponding to each of the capacitive elements, inserted between the corresponding capacitive element and a reset potential, and setting a potential of the corresponding capacitive element to a reset potential;
An output amplifier that outputs a signal potential accumulated in the capacitive element;
A switch provided corresponding to each of the capacitive elements, inserted between the corresponding capacitive element and the output amplifier, and causing the output amplifier to output a signal potential of the corresponding capacitive element;
By sequentially selecting the switches and turning them on, the signal potentials of the capacitive elements corresponding to the switches that are turned on are sequentially output to the output amplifier, and the transistors are sequentially selected and turned on. A solid-state imaging device comprising: a shift register that sequentially sets a potential of the capacitive element corresponding to the transistor that is turned on at a reset potential. The solid-state imaging device according to claim 1, wherein the shift register selects the transistor that sets the potential of the capacitive element corresponding to the selected switch to a reset potential with a delay of one clock or more from the selection of the switch. 2. The solid-state imaging device according to claim 1, wherein the shift register selects one transistor for a period longer by at least one clock than a period for selecting one switch. The solid-state imaging device according to claim 1, wherein a reset potential connected to the transistor is different from a reset potential set by the reset unit. 2. The solid state according to claim 1, wherein the shift register includes a first shift register that sequentially selects the switches and turns them on, and a second shift register that sequentially selects the transistors and turns them on. Imaging device. The solid-state imaging device according to claim 5, further comprising a comparison unit that starts supplying a trigger pulse to the second shift register when the output of the output amplifier is equal to or greater than an arbitrary threshold value. The solid-state imaging device according to claim 1, wherein the shift register generates a driving pulse for driving the switch and a driving pulse for driving the transistor based on one trigger pulse and a clock. The shift register selects the switch and the transistor provided corresponding to the same capacitive element in a predetermined period of the clock;
The solid-state imaging device according to claim 7, wherein a period during which the switch is selected and a period during which the transistor is selected are each a half cycle of the predetermined one period. The shift register selects the predetermined switch by supplying a first drive pulse to the predetermined switch, and then supplies a second drive pulse to the switch different from the predetermined switch. A switch different from a switch is selected, and the predetermined transistor is selected by supplying the second drive pulse to a predetermined transistor provided corresponding to the same capacitive element as the predetermined switch. The solid-state imaging device according to 1. The shift register selects the predetermined switch by supplying a first drive pulse to the predetermined switch, and then selects the second drive pulse and the third drive pulse different from the predetermined switch. To select two switches different from the predetermined switch,
The solid-state imaging device further supplies an OR output of the second drive pulse and the third drive pulse to a predetermined transistor provided corresponding to the same capacitive element as the predetermined switch. The solid-state imaging device according to claim 1, further comprising a calculation unit that selects the predetermined transistor. A method for driving a solid-state imaging device,
The solid-state imaging device
A pixel array composed of a plurality of unit pixels arranged in a matrix;
Row selection means for selecting the unit pixel in units of rows and outputting a signal potential;
A capacitive element that is provided for each column of the unit pixels and accumulates a signal potential output from the unit pixel selected by the row selection unit;
Reset means for collectively setting the respective potentials of the capacitive elements to a reset potential;
A transistor provided corresponding to each of the capacitive elements, inserted between the corresponding capacitive element and a reset potential, and setting a potential of the corresponding capacitive element to a reset potential;
An output amplifier that outputs a signal potential accumulated in the capacitive element;
A switch provided corresponding to each of the capacitive elements, inserted between the corresponding capacitive element and the output amplifier, and a switch for outputting the signal potential of the corresponding capacitive element to the output amplifier,
By sequentially selecting the switches and turning them on, the signal potentials of the capacitive elements corresponding to the switches that are turned on are sequentially output to the output amplifier, and the transistors are sequentially selected and turned on. A method for driving a solid-state imaging device, wherein the potential of the capacitor corresponding to the transistor turned on in step S1 is sequentially set to a reset potential.

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