JP2008118371A - Image pickup element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the occurrence of moire or the like while accelerating a frame rate. <P>SOLUTION: A CMOS image pickup element has a plurality of pixels. The pixels are arrayed according to a Bayer method. Each pixel generates a pixel signal being a signal potential corresponding to a received light amount. A vertical output line is provided in each column for forming pixels. Each pixel is connected to an adjacent vertical output line. Each vertical output line is connected to a horizontal output line. Pixel signals of pixels of the first and third columns are outputted to a horizontal output line at timing T1 (Φsr1 and Φsr3). In the horizontal output line, the pixel signals of pixels of the first and third columns are equalized. Pixel signals of pixels of the second and fourth columns are outputted to the horizontal output line at timing T2 (Φsr2 and Φsr4). In the horizontal output line, the pixels signals of pixels of the second and fourth columns are equalized. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an image sensor that reduces the occurrence of moire while ensuring a frame rate.

  A digital camera that has an image sensor with a large number of pixels and can capture still images and moving images is known. When shooting a moving image with such a digital camera, it is known to thin out pixels for outputting signals from the image sensor. Note that such thinning-out output means reading out signals from some pixels during the reading period of the entire image when outputting image signals from the image sensor.

  Decreasing the frame rate is prevented by thinning out the output pixels. That is, the reading operation on the entire light receiving surface is speeded up while keeping the time required for generating and outputting the pixel signal by a single pixel constant. However, by performing pixel thinning necessary to prevent a decrease in the frame rate, there is a problem that a false pattern or moire occurs because actual information is lost.

In view of this, it has been proposed to obtain an image signal having the same data size as that obtained when thinning output is performed by outputting signals from all pixels of the image sensor and performing pixel addition in subsequent image processing (see Patent Document 1). ). Although it is possible to prevent the occurrence of moire by adding pixels, it is difficult to increase the output speed of the image sensor because it is necessary to output signals from all pixels of the image sensor.
JP 2003-333610 A

  Therefore, an object of the present invention is to provide an image sensor that prevents the occurrence of moire while securing the frame rate.

  A first imaging element of the present invention includes a pixel having a photoelectric conversion element that generates a signal charge according to the amount of received light, and a selection transistor that switches between outputting and stopping output of a pixel signal that is a signal potential according to the signal charge. An output signal line connected to selection transistors of a plurality of pixels arranged in the first direction and outputting a pixel signal; and a plurality of pixels connected to the same output signal line for outputting the pixel signal to the output signal line And a pixel selection unit to be executed by the selection transistor.

  Furthermore, each of the plurality of pixels arranged along the first direction is alternately and repeatedly covered with a plurality of types of color filters, and the pixel selection unit is configured to select pixels in the plurality of pixels covered with the same type of color filter. It is preferable to execute output of a signal.

  A second imaging element of the present invention includes a photoelectric conversion element that generates a signal charge according to the amount of received light, and a first selection transistor that switches between outputting and stopping the output of a pixel signal having a signal potential according to the signal charge. Selection of pixels arranged along the second direction and a plurality of pixels arranged for each pixel arranged along the second direction and arranged along a first direction different from the second direction Output of the plurality of first output signal lines connected to the transistors and outputting the pixel signals and output of the pixel signals connected to each of the plurality of first output signal lines and output to the first output signal lines and output stop A plurality of second selection transistors, a second output signal line connected to the plurality of second selection transistors and outputting a pixel signal, and a first output signal line to a second output signal line 2 or more second selection of pixel signal output to It is characterized by comprising a pixel selection unit to be performed by the transistor.

  Further, each of the plurality of pixels arranged along the second direction is alternately and repeatedly covered with a plurality of types of color filters, and the pixel selection unit is a second selection transistor in the plurality of pixels covered with the same type of color filter. It is preferable to cause the pixel signal to be output.

  Further, it is preferable that the pixel selection unit causes the first selection transistors in the plurality of pixels connected to the same first output signal line to execute the output of the pixel signal from the pixel to the first output signal line.

  Furthermore, each of the plurality of pixels arranged along the first direction is alternately and repeatedly covered with a plurality of types of color filters, and the pixel selection unit is configured to select pixels in the plurality of pixels covered with the same type of color filter. It is preferable to execute output of a signal.

  According to the present invention, it is possible to average pixel signals of a plurality of pixels in an image sensor. Therefore, it is possible to suppress the occurrence of moire while increasing the frame rate.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram schematically showing an internal configuration of a digital camera having an image sensor to which an embodiment of the present invention is applied. The digital camera 10 includes a lens 11, an image sensor 20, a digital signal processing circuit 12, a system controller 13, a timing generator 14, and the like.

  The lens 11 is optically connected to the image sensor 20. An optical image of the subject that passes through the lens 11 enters the light receiving surface of the image sensor 20. The image sensor 20 is a CMOS image sensor. When the optical image of the subject is received on the light receiving surface, an image signal corresponding to the optical image is generated.

  The image signal generated by the image sensor 20 is converted from an analog signal to a digital signal by the A / D converter 15. The image signal converted into the digital signal is sent to the digital signal processing circuit 12.

  The image signal sent to the digital signal processing circuit 12 is stored in a DRAM 16 which is a signal processing working memory. The image signal stored in the DRAM 16 is subjected to predetermined signal processing in the digital signal processing circuit 12.

  The image signal that has undergone predetermined signal processing is sent to the monitor 17. On the monitor 17, an image corresponding to the transmitted image signal is displayed. The image signal that has undergone predetermined signal processing can be stored in an external memory 18 connected via a connector (not shown).

  The imaging device 20 and the shutter 19 are driven by the timing generator 14. An image signal is generated by driving the image sensor 20 and the shutter 19. The driving of each part by the timing generator 14 is controlled by the system controller 13.

  Next, the configuration of the image sensor 20 will be described with reference to FIG. FIG. 2 is a block diagram showing the configuration of the image sensor.

  The imaging device 20 is a CMOS imaging device, and includes an imaging unit 21, a row selection circuit 22, a column selection circuit 23, a horizontal output line 24, a column selection transistor (second selection transistor) 25, and the like. The imaging unit 21 and the row selection circuit 22 are directly connected. The horizontal output line (second output signal line) 24 is connected to the imaging unit 21 via the column selection transistor 25. Column selection circuit 23 and column selection transistor 25 are connected.

  A plurality of pixels 30 are arranged in a matrix on the imaging surface of the imaging unit 21. Each pixel 30 is covered with a color filter of any one of an R (ed) color filter, a G (reen) color filter, and a B (lue) color filter. The color filter is arranged according to the Bayer method.

  Accordingly, two types of color filters, an R color filter and a G color filter, are alternately and repeatedly arranged in the row direction (second direction). Alternatively, two types of color filters, the G color filter and the B color filter, are alternately and repeatedly arranged.

  Also, two types of color filters, an R color filter and a G color filter, are alternately and repeatedly arranged in the column direction (first direction). Alternatively, the G color filter and the B color filter are alternately and repeatedly arranged.

  The pixel 30 covered with the R color filter receives red component light. The pixel 30 covered with the G color filter receives green component light. The pixel 30 covered with the B color filter receives blue component light.

  A signal charge corresponding to the amount of light received through the color filter is generated in each pixel 30. The image signal of the entire subject image is composed of a set of pixel signals corresponding to the signal charges of the pixels 30 arranged on the imaging surface. Reading of the generated pixel signal is performed for each pixel 30. The pixel 30 to be read is selected directly or indirectly by the row selection circuit 22 and the column selection circuit 23.

  A row of pixels 30 is selected by the row selection circuit 22. A pixel signal output from the selected pixel 30 is output to the column selection transistor 25 via a vertical output line (first output signal line, not shown in FIG. 2).

  The pixel signal output to the column selection transistor 25 is selected by the column selection circuit 23 and output to the horizontal output line 24. The pixel signal output to the horizontal output line 24 is sent to the digital signal processing circuit 12 via the output unit 26 and the A / D converter 15. The pixel signal is subjected to predetermined signal processing in the digital signal processing circuit 12 and is sent as an image signal to the monitor 17 or the external memory 18.

  The row selection circuit 22 and the column selection circuit 23 are connected to the timing generator 14. The timing generator 14 drives the row selection circuit 22 and the column selection circuit 23 to select a pixel 30 that outputs a pixel signal.

  The configuration of the pixel 30 will be described in detail with reference to FIG. FIG. 3 is a circuit diagram showing the configuration of the pixel. The pixel 30 includes a photodiode (PD) 31, a floating diffusion (FD) 32, a transfer transistor 33, a reset transistor 34, an amplification transistor 35, and a row selection transistor (first selection transistor) 36.

  In the PD 31, signal charges are generated according to the amount of light received for each pixel 30, and the generated signal charges are accumulated. The FD 32 is connected to the PD 31 via the transfer transistor 33. The transfer transistor 33 transfers the signal charge accumulated in the PD 31 to the FD 32 at a predetermined timing. When the signal charge is transferred to the FD 32, the potential of the FD 32 changes to a potential corresponding to the transferred charge.

  The FD 32 is connected to the voltage source Vdd via the reset transistor 34. The reset transistor 34 sweeps the signal charge stored in the FD 32 to the voltage source Vdd at a predetermined timing and resets it. Further, the potential of the FD 32 is reset to the potential of the voltage source Vdd.

  The FD 32 is connected to the gate of the amplification transistor 35. The drain of the amplification transistor 35 is connected to the voltage source Vdd. The source of the amplification transistor 35 is connected to the vertical output line 27 via the row selection transistor 36. The output impedance is adjusted by the amplification transistor 35, and a signal potential corresponding to the potential of the FD 32 can be output as a pixel signal.

  A row selection signal Φsl for switching between HIGH and LOW is supplied to the gate of the row selection transistor 36 at a different timing for each row. When the row selection signal Φsl in the HIGH state is supplied to the gate, the row selection transistor 36 is turned ON, and the pixel signal can be output to the vertical output line 27. On the other hand, when the row selection signal Φsl in the LOW state is supplied to the gate, the row selection transistor 36 is turned OFF, and the output of the pixel signal to the vertical output line 27 is stopped. The row selection signal Φsl is transmitted from the row selection circuit 22.

  The vertical output line 27 is connected to the current source Iss above the imaging surface. The vertical output line 27 is connected to the horizontal output line 24 via the column selection transistor 25 below the imaging surface.

  A column selection signal Φsr for switching between HIGH and LOW is supplied to the gate of the column selection transistor 25 at a different timing for each column. By supplying a HIGH column selection signal Φsr to the gate, the column selection transistor 25 is turned ON, and a pixel signal is output to the horizontal output line 24. On the other hand, when the column selection signal Φsr in the LOW state is supplied to the gate, the column selection transistor 25 is turned OFF, and the output of the pixel signal to the horizontal output line 24 is stopped. As described above, the pixel signal output to the horizontal output line 24 is output to the external device of the image sensor 20. The column selection signal Φsr is transmitted from the column selection circuit 23.

  Next, a pixel signal output method from the image sensor 20 will be described. Output of pixel signals from the image sensor 20 is performed according to the all-pixel output method and the first to third averaged output methods. Note that according to the all-pixel output method, pixel signals of all the pixels 30 are output. According to the first averaging output method, a plurality of pixel signals of the pixels 30 arranged in the row direction are averaged and output. According to the second averaged output method, a plurality of pixel signals of the pixels 30 arranged along the column direction are averaged and output. According to the third averaged output method, a plurality of pixel signals of the pixels 30 arranged along the row direction and the column direction are averaged and output. Hereinafter, each output method will be described in detail.

  The selection operation of the pixels 30 in the image sensor 20 in the all-pixel output method will be described with reference to the timing chart of FIG. FIG. 4 shows only pixel signal output timings by the row selection transistor 36 and the column selection transistor 25.

  On the other hand, although the timing of the signal charge transfer operation by the transfer transistor 33 is omitted, the transfer operation is executed before or while the specific pixel 30 by the row selection transistor 37 and the column selection transistor 25 is selected. . Although the timing of the reset operation of the FD 32 by the reset transistor 34 is also omitted, the reset operation is executed before the next transfer operation after the pixel signal is output from the pixel 30.

  At the timing of T1, the row selection signal Φsl1 input to the row selection transistors 36 of the pixels 30 arranged in the first row from the top is switched to HIGH. By switching the row selection signal Φsl1 to HIGH, a pixel signal generated in the pixels 30 arranged in the first row is output to the vertical output line 27.

  At the same timing T1, the column selection signal Φsr1 input to the column selection transistor 25 in the first column from the left is switched to HIGH. By switching the column selection signal Φsr1 to HIGH, the pixel signal output to the vertical output line 27 of the first column is output to the outside of the image sensor 20 via the horizontal output line 24.

  In the same manner, 2, 3, 4, 5, 6, 7, 8,..., The column selection signals Φsr2, Φsr3, Φsr4, Φsr5, Φsr6, Φsr7, Φsr8,. ... ΦsrN is sequentially switched to HIGH. By switching the column selection signal, the pixel signal output to the vertical output line 27 of the second, third, fourth, fifth, sixth, seventh, eighth,... Output to the outside of the element 20.

  When the column selection signal ΦsrN of the Nth column is switched from HIGH to LOW, the row selection signal Φsl1 of the first row is also switched to LOW (see timing T2). When the row selection signal Φsl1 is switched to LOW, the selection of the pixels 30 arranged in the first row is released.

  At the timing of T3, the row selection signal Φsl2 input to the row selection transistor 36 of the pixels 30 arranged in the second row is switched to HIGH. By switching the row selection signal Φsl2 to HIGH, a pixel signal generated in the pixels 30 arranged in the second row is output to the vertical output line 27.

  In the same manner as the output of the pixel signal in the first row, 1, 2, 3, 4, 5, 6, 7, 8,..., N-th column selection signals Φsr1, Φsr2, Φsr3, Φsr4, Φsr5, Φsr6, Φsr7, Φsr8,..., ΦsrN are sequentially switched to HIGH. By switching the column selection signal, the pixel signal output to the vertical output line 27 of the 1st, 2nd, 3rd, 4th, 5th, 6th, 7th, 8th,. And output to the outside of the image sensor 20 (see timing T3 to timing T4).

  Thereafter, similarly, pixel signals generated by the pixels 30 arranged in the Mth row as the last row are sequentially output to the outside of the image sensor 20.

  Next, the selection operation of the pixels 30 in the image sensor 20 in the first averaging output method will be described with reference to the timing chart of FIG. FIG. 5 shows only the output timing of the pixel signal by the row selection transistor 36 and the column selection transistor 25 as in FIG. Further, the timing of the transfer operation and the reset operation is omitted.

  At the timing of T1, the row selection signal Φsl1 input to the row selection transistors 36 of the pixels 30 arranged in the first row from the top is switched to HIGH. By switching the row selection signal Φsl1 to HIGH, a pixel signal generated in the pixels 30 arranged in the first row is output to the vertical output line 27.

  At the same timing T1, the column selection signals Φsr1 and Φsr3 input to the first and third column selection transistors 25 from the left are switched to HIGH. By switching the column selection signals Φsr1 and Φsr3 to HIGH, the column selection transistor 25 in the first row, the third column, and the horizontal output line 24 become conductive.

  The potential of the horizontal output line 24 when the first and third column selection transistors 25 are turned on will be described with reference to FIG. FIG. 6 is an equivalent circuit diagram of the pixels 30 in the first and third columns, the vertical output line 27, and the horizontal output line 24 when the row selection transistor 36 and the column selection transistor 25 are turned on.

  Signal potentials and reactances that are pixel signals of the pixels 30 in the first column are V1 and R1. Further, the signal potential and reactance which are pixel signals of the pixels 30 in the third column are V3 and R3. As shown in FIG. 6, the pixels 30 in the first and third columns are connected in parallel by a horizontal output line 24. Therefore, the potential V0 in the horizontal output line 24 is (R3 × V1 + R1 × V3) / (R1 + R3).

  The reactance of each pixel 30 is substantially the same, that is, R1 = R3. Therefore, the potential V0 in the horizontal output line 24 is (V1 + V3) / 2, which is the average value of the signal levels of the pixel signals in the pixels 30 in the first and third columns.

  Therefore, at the timing of T1, a signal obtained by averaging the pixel signals of the pixels 30 in the first and third columns is output to the outside of the image sensor 20 as the pixel signal via the horizontal output line 24. Since the color filters are arranged according to the Bayer method as described above, the signal levels of the pixel signals of the odd-numbered pixels 30 in the odd-numbered rows such as the first row 1, the third column are the light levels of the same color components. Depending on the amount of light received.

  At the timing of T2, the column selection signals Φsr2 and Φsr4 input to the column selection transistor 25 of the second and fourth columns from the left are switched to HIGH while the row selection signal Φsl1 of the first row remains HIGH (see FIG. 5). . By switching the column selection signals Φsr2 and Φsr4 to HIGH, the column selection transistors 25 in the first row 2, the fourth column and the horizontal output line 24 become conductive.

  Similarly to the pixel signals of the pixels 30 in the first and third columns at the timing T1, a signal obtained by averaging the pixel signals of the pixels 30 in the second and fourth columns at the timing T2 is passed through the horizontal output line 24 as a pixel signal. It is output to the outside of the image sensor 20. As described above, since the color filters are arranged according to the Bayer method, the signal level of the pixel signal of the even column 30 in the odd row such as 1 row 2 and 4 columns is the light reception of the light of the same color component. Depending on the amount.

  Furthermore, the signal level of the pixel signal of the pixel in the odd column in the even row depends on the amount of light received by the same color component, and the signal level of the pixel signal in the pixel in the even column in the even row is the same color component light. Depending on the amount of received light.

  Thereafter, similarly, two consecutive odd columns and two consecutive even columns are sequentially switched to HIGH. For example, the fifth, seventh, sixth, eighth,..., N-3, N−1, and N−2, Nth column selection signals Φsr are sequentially switched to HIGH.

  By switching the column selection signal Φsr of two consecutive odd columns or two consecutive even columns to HIGH, the pixel signals of the two pixels 30 in the columns simultaneously switched to HIGH are averaged, and the image sensor 20 Is output outside of.

  When the column selection signals ΦsrN-2 and ΦsrN of the N-2 and Nth columns are switched from HIGH to LOW, the row selection signal Φsl1 of the first row is also switched to LOW (see timing T3). The selection of the pixels 30 arranged in the first row is canceled by switching the row selection signal Φsl1 to LOW.

  At the timing of T4, the row selection signal Φsl2 input to the row selection transistor 36 of the pixels 30 arranged in the second row is switched to HIGH. By switching the row selection signal Φsl2 to HIGH, a pixel signal generated in the pixels 30 arranged in the second row is output to the vertical output line 27.

  Similar to the output of the pixel signal in the first row, as in the first, third, second, fourth,..., N-3, N-1 and N-2, N columns. The column selection signals Φsr of two consecutive odd columns and two consecutive even columns are sequentially switched to HIGH. By such switching, the pixel signals of the two pixels 30 in the column simultaneously switched to HIGH are averaged and output to the outside of the image sensor 20 (see timing T4 to timing T5).

  Thereafter, similarly, pixel signals generated by the pixels 30 arranged in the 3, 4, 5, 6, 7, 8,... M rows are averaged and output to the outside of the image sensor 20.

  Next, the selection operation of the pixels 30 in the image sensor 20 in the case of the second averaged output method will be described with reference to the timing chart of FIG. 7 shows only the output timing of the pixel signal by the row selection transistor 36 and the column selection transistor 25 as in FIG. Further, the timing of the transfer operation and the reset operation is omitted.

  At the timing of T1, the row selection signals Φsl1 and Φsl3 input to the row selection transistors 36 of the pixels 30 arranged in the first and third rows from the top are switched to HIGH. By switching the row selection signals Φsl1 and Φsl3 to HIGH, pixel signals generated in the pixels 30 arranged in the first and third rows are output to the vertical output line 27.

  Similar to the equivalent circuit shown in FIG. 6, the potential of the vertical output line 27 from which the pixel signals from the pixels 30 in the first and third rows are output is the potential of the pixel signal output from the pixels 30 in the first and third rows. This is the average signal level.

  At the same timing T1, the column selection signal Φsr1 input to the column selection transistor 25 in the first column from the left is switched to HIGH. By switching the column selection signal Φsr1 to HIGH, a signal obtained by averaging the pixel signals of the pixels 30 in the first, third, and first columns is output to the outside of the image sensor 20 as a pixel signal via the horizontal output line 24. .

  In the same manner, the column selection signals Φsr2, Φsr3, Φsr4, Φsr5, Φsr6, Φsr7, Φsr8,. It is switched to HIGH in order. By switching the column selection signal, the averaged pixel signal output to the vertical signal lines of the second, third, fourth, fifth, sixth, seventh, eighth,..., N columns is output via the horizontal output line 24. It is output to the outside of the image sensor 20.

  When the column selection signal ΦsrN of the Nth column is switched from HIGH to LOW, the row selection signals Φsl1 and Φsl3 of the first and third rows are also switched to LOW (see timing T2). When the row selection signals Φsl1 and Φsl3 are switched to LOW, the selection of the pixels 30 arranged in the first and third rows is released.

  At the timing of T3, the row selection signals Φsl2 and Φsl4 input to the row selection transistors 36 of the pixels 30 arranged in the second and fourth rows are switched to HIGH. By switching the row selection signals Φsl2 and Φsl4 to HIGH, pixel signals generated in the pixels 30 arranged in the second and fourth rows are output to the vertical output line 27 and averaged.

  1, 2, 3, 4, 5, 6, 7, 8,... N column selection signals Φsr1, Φsr2, Φsr3, Φsr4, Φsr5 , Φsr6, Φsr7, Φsr8,..., ΦsrN are sequentially switched to HIGH. By switching the column selection signal, the averaged pixel signal output to the vertical signal lines of the second, third, fourth, fifth, sixth, seventh, eighth,..., N columns is output via the horizontal output line 24. It is output to the outside of the image sensor 20 (see timing T3 to timing T4).

  Thereafter, similarly, two consecutive odd rows and two consecutive even rows are sequentially switched to HIGH. For example, the row selection signals Φsl in the fifth, seventh, sixth, eighth,..., M-3, M−1, M-2, and M rows are sequentially switched to HIGH. While the two rows are selected, the averaged pixel signal is output to the outside of the image sensor 20 in order for each column.

  Next, the selection operation of the pixel 30 in the image sensor 20 in the case of the third averaged output method will be described with reference to the timing chart of FIG. 8 shows only the output timing of the pixel signal by the row selection transistor 36 and the column selection transistor 25 as in FIG. Further, the timing of the transfer operation and the reset operation is omitted.

  At the timing of T1, the row selection signals Φsl1 and Φsl3 input to the row selection transistors 36 of the pixels 30 arranged in the first and third rows from the top are switched to HIGH. By switching the row selection signals Φsl1 and Φsl3 to HIGH, pixel signals generated in the pixels 30 arranged in the first and third rows are output to the vertical output line 27 and averaged.

  At the same timing T1, the column selection signals Φsr1 and Φsr3 input to the first and third column selection transistors 25 from the left are switched to HIGH.

  By switching the column selection signals Φsr1 and Φsr3 to HIGH, the pixel signals output and averaged to the vertical output lines 27 of the first and third columns are output to the horizontal output line 24 and further averaged. That is, the pixel signals output from the four pixels 30 arranged in the first row 1, the third column and the third row 1, the third column in the vertical output line 27 and the horizontal output line 24 are averaged. Pixel signals averaged in the vertical output line 27 and the horizontal output line 24 are output to the outside of the image sensor 20.

  At the timing of T2, the column selection signals Φsr2 and Φsr4 input to the column selection transistors 25 of the second and fourth columns from the left are switched to HIGH while the row selection signals Φsl1 and Φsl3 of the first and third rows remain HIGH.

  By switching the column selection signals Φsr2 and Φsr4 to HIGH, the pixel signals output and averaged to the vertical output lines 27 of the second and fourth columns are output to the horizontal output line 24 and further averaged. The pixel signal averaged in the horizontal output line 24 is output to the outside of the image sensor 20.

  Thereafter, similarly, two consecutive odd columns and two consecutive even columns are sequentially switched to HIGH. For example, the fifth, seventh, sixth, eighth,..., N-3, N−1, and N−2, Nth column selection signals Φsr are sequentially switched to HIGH.

  By switching the column selection signal Φsr of two consecutive odd columns or two consecutive even columns in the first and third rows to HIGH, the pixel signals of the two pixels 30 in the columns simultaneously switched to HIGH are averaged. And output to the outside of the image sensor 20.

  When the column selection signals ΦsrN-2 and ΦsrN of the N-2th and Nth columns are switched from HIGH to LOW, the row selection signals Φsl1 and Φsl3 of the first and third rows are also switched to LOW (see timing T3). The selection of the pixels 30 arranged in the first and third rows is canceled by switching the row selection signals Φsl1 and Φsl3 to LOW.

  At the timing of T4, the row selection signals Φsl2 and Φsl4 input to the row selection transistors 36 of the pixels 30 arranged in the second and fourth rows are switched to HIGH. By switching the row selection signals Φsl2 and Φsl4 to HIGH, pixel signals generated in the pixels 30 arranged in the second and fourth rows are output to the vertical output line 27 and averaged.

  Similar to the output of the pixel signals in the first and third rows, the first, third, second, fourth,..., N-3, N−1, and N−2, Nth columns. As described above, the column selection signals Φsr of two consecutive odd columns and two consecutive even columns are sequentially switched to HIGH. By such switching, the pixel signals of the two pixels 30 in the columns simultaneously switched to HIGH in the second and fourth rows are further averaged and output to the outside of the image sensor 20 (see timing T4 to timing T5). ).

  Thereafter, similarly, two consecutive odd rows and two consecutive even rows are sequentially switched to HIGH. For example, the row selection signals Φsl in the fifth, seventh, sixth, eighth,..., M-3, M−1, M-2, and M rows are sequentially switched to HIGH. While each two rows are selected, pixel signals output from two consecutive odd columns or two consecutive even columns are averaged and output to the outside of the image sensor 20.

  According to the imaging device having the above configuration, it is possible to output an averaged pixel signal to the imaging device itself. Accordingly, since the number of output times of the pixel signals forming one frame image signal is reduced, it is possible to increase the output speed of one frame image signal. For example, the first and second averaged output methods are twice as fast as the all-pixel output method, and the third averaged output method is four times faster.

  Also, according to the image sensor of the present embodiment, unlike the conventional thinned output, there is no missing pixel signal, so it is possible to reduce the occurrence of moire and false colors.

  In the present embodiment, the image signal can be output at high speed in accordance with any one of the first to third averaged output methods, but at least one of the first to third averaged output methods. The image signal may be output according to one output method.

  In the present embodiment, the pixel signals of the pixels 30 in two consecutive odd rows and two consecutive even rows, and / or two consecutive odd columns and two even columns are averaged. Is not limited to two rows or two columns. Averaging may be performed using pixel signals of pixels 30 in a plurality of rows or columns.

  In this embodiment, the color filters are arranged according to the Bayer method, but may be arranged by other methods. If pixel signals corresponding to light components of the same color in the row direction and the column direction are averaged, the same effect as in the present embodiment can be obtained.

  Further, in the present embodiment, each pixel is configured to be covered with the color filter, but may not be covered with the color filter. Even with an image sensor that captures a black and white image without being covered by the color filter, it is possible to obtain an effect capable of capturing an image with less moire at high speed. In this case, it is only necessary to average pixel signals of a plurality of continuous pixels, not pixels in consecutive odd rows or even rows, continuous odd columns or even columns.

  In this embodiment, the image sensor is a CMOS image sensor, but may be any other XY address image sensor.

1 is a block diagram schematically showing an internal configuration of a digital camera having an image sensor to which an embodiment of the present invention is applied. It is a block diagram which shows the structure of an image pick-up element. It is a circuit diagram which shows the structure of a pixel. 6 is a timing chart showing pixel signal output timing in the image sensor when the all-pixel output method is used. It is a timing chart which shows the output timing of the pixel signal in an image sensor at the time of the 1st average output system. FIG. 5 is an equivalent circuit diagram of a pixel, a vertical output line, and a horizontal output line when a row selection transistor and a column selection transistor are made conductive. It is a timing chart which shows the output timing of the pixel signal in an image sensor at the time of the 2nd average output system. 12 is a timing chart showing the output timing of pixel signals in the image sensor when the third averaging method is used.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Digital camera 14 Timing generator 20 Image pick-up element 22 Row selection circuit 23 Column selection circuit 24 Horizontal output line 25 Column selection transistor 27 Vertical output line 30 Pixel 36 Row selection transistor

Claims (6)

A pixel having a photoelectric conversion element that generates a signal charge according to the amount of received light, and a selection transistor that switches between output and stop of a pixel signal that is a signal potential according to the signal charge;
An output signal line connected to the selection transistors of a plurality of the pixels arranged in a first direction and outputting the pixel signal;
An image sensor comprising: a pixel selection unit that causes the selection transistors in the plurality of pixels connected to the same output signal line to output the pixel signal to the output signal line. Each of the plurality of pixels arranged along the first direction is alternately and repeatedly covered with a plurality of types of color filters,
The image sensor according to claim 1, wherein the pixel selection unit causes the selection transistors in the plurality of pixels covered by the same type of color filter to output the pixel signal. A photoelectric conversion element that generates a signal charge according to the amount of received light and a first selection transistor that switches between output and stop of output of a pixel signal having a signal potential according to the signal charge, along a second direction Arranged pixels,
Provided for each of the pixels arranged along the second direction, connected to the selection transistors of the plurality of pixels arranged along a first direction different from the second direction, and the pixel signal A plurality of first output signal lines to be output;
A plurality of second selection transistors connected to each of the plurality of first output signal lines and configured to switch between outputting and stopping the output of the pixel signal output to the first output signal line;
A second output signal line connected to the plurality of second selection transistors and outputting the pixel signal;
A pixel selection unit that causes two or more second selection transistors to output the pixel signal from the first output signal line to the second output signal line. element. Each of the plurality of pixels arranged along the second direction is alternately and repeatedly covered with a plurality of types of color filters,
The image sensor according to claim 3, wherein the pixel selection unit causes the second selection transistor in the plurality of pixels covered by the same type of color filter to output the pixel signal.   The pixel selection unit outputs the output of the pixel signal from the pixel to the first output signal line to the first selection transistor in the plurality of pixels connected to the same first output signal line. The image pickup device according to claim 3, wherein the image pickup device is executed. Each of the plurality of pixels arranged along the first direction is alternately and repeatedly covered with a plurality of types of color filters,
The image sensor according to claim 5, wherein the pixel selection unit causes the selection transistors in the plurality of pixels covered by the same type of color filter to output the pixel signal.

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