JP2005203516A - Light emitting diode element and manufacturing method thereof - Google Patents

Light emitting diode element and manufacturing method thereof Download PDF

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JP2005203516A
JP2005203516A JP2004007263A JP2004007263A JP2005203516A JP 2005203516 A JP2005203516 A JP 2005203516A JP 2004007263 A JP2004007263 A JP 2004007263A JP 2004007263 A JP2004007263 A JP 2004007263A JP 2005203516 A JP2005203516 A JP 2005203516A
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light emitting
doped semiconductor
semiconductor layer
emitting diode
electrode
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Chao-Huang Lin
照晃 林
Hakujin Go
伯仁 呉
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SHURAI KAGI KOFUN YUGENKOSHI
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SHURAI KAGI KOFUN YUGENKOSHI
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a light emitting diode element which assures sufficient electrode-to-electrode distance when the size is reduced and ensures uniform luminance by enhancing the yield of scribing of an element and providing a flip chip light emitting diode element in the reduced size, and also to provide a method of manufacturing a light emitting diode which can enhance manufacturing yield and amount of production. <P>SOLUTION: A substrate and a light emitting diode have the water-caltrop type contours, electrodes thereof are located at both ends of the diagonal line of the longer side in the water-caltrop shape, and accordingly, the electrode distance becomes longer and the light emitting area becomes large. This light emitting diode is fixed to the substrate with the flip chip package system. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は一種の発光ダイオード素子とその製造方法に係り、特に、歩留りが高く発光面積が大きい発光ダイオード素子及びその製造方法に関する。   The present invention relates to a kind of light emitting diode device and a method for manufacturing the same, and more particularly, to a light emitting diode device having a high yield and a large light emitting area and a method for manufacturing the same.

近年、発光ダイオード産業の発展は窒化ガリウムベース半導体例えば窒化ガリウム化合物半導体を、発生する波長の範囲が緑光、青光と紫外光の間の短波長発光ダイオードとなす方向にある。短波長発光ダイオードは高周波数或いは短波長を有するため緑光或いは青光フルカラーの応用に用いられ、青光と紫外光発光ダイオードは更にエネルギー変換により白光光源とされうる。   In recent years, the development of the light-emitting diode industry is in the direction of producing gallium nitride-based semiconductors such as gallium nitride compound semiconductors as short-wavelength light-emitting diodes that generate green light, blue light, and ultraviolet light. Since short wavelength light emitting diodes have high frequencies or short wavelengths, they can be used for green light or blue light full color applications, and blue light and ultraviolet light emitting diodes can be further converted into white light sources by energy conversion.

伝統的に、窒化ガリウム／サファイヤ基板発光ダイオードは、電極接点を対角線の両端に置くことで発光面積を増している。しかし、電極接点と外界を接続し発光ダイオードを駆動するためには、電極接点に導線を通して発光ダイオード上端のパッド或いはコンタクトパッドを形成しなければならない。このような設計は、発光ダイオードの発光面積を遮蔽し、特に平面視によると、発光ダイオードの発光面積が実質上、小さくなる。このほか、この伝統的な構造は電流の二つの金属パッドの間への過度の集中を形成しやすく、すなわち電流輻輳を形成して素子の寿命に影響を与える。   Traditionally, gallium nitride / sapphire substrate light emitting diodes have increased light emitting area by placing electrode contacts at opposite ends of the diagonal. However, in order to connect the electrode contact and the outside world to drive the light emitting diode, it is necessary to form a pad or contact pad at the top of the light emitting diode through the electrode contact through the lead wire. Such a design shields the light emitting area of the light emitting diode, and the light emitting area of the light emitting diode is substantially reduced particularly in plan view. In addition, this traditional structure tends to form an excessive concentration of current between the two metal pads, i.e., current convergence, which affects the lifetime of the device.

以上述べたように、この化合物半導体発光ダイオードは電極接点を発光面積の対角線両端に置かねばならない。電極接点と外界を接続して発光ダイオードを駆動するためには、電極接点を導線で外界と接続して発光ダイオードを駆動しなければならず、電極接点と導線体積はあまり小さくすることはできないため、発光ダイオードの発光面積が実質的に縮小されてしまう。このほか、素子サイズが縮小される時、一般に正方形輪郭を具えた発光ダイオードはその電極接点がその対角線両端に位置し、この時、電極接点は十分に接近し更に容易に電流輻輳を形成して素子特性に影響を与え、信頼度を下げ且つ電極が過度に接近するため、ワイヤボンディングの歩留りが下がる。このほか、サファイヤ基板は六角格子に属するため発光ダイオードをスクライビングして正方形とすると、素子の亀裂を発生し工程の歩留りが下がる。   As described above, in this compound semiconductor light emitting diode, the electrode contacts must be placed at both ends of the diagonal line of the light emitting area. In order to drive the light emitting diode by connecting the electrode contact and the outside world, the electrode contact must be connected to the outside world by a conducting wire and the light emitting diode must be driven, and the electrode contact and the conducting wire volume cannot be made very small. The light emitting area of the light emitting diode is substantially reduced. In addition, when the element size is reduced, generally, the light emitting diode having a square outline has its electrode contacts located at both ends of the diagonal line. At this time, the electrode contacts are sufficiently close to form current convergence more easily. The device characteristics are affected, the reliability is lowered, and the electrodes are excessively approached, so that the yield of wire bonding is lowered. In addition, since the sapphire substrate belongs to a hexagonal lattice, if the light emitting diode is scribed to be square, the device cracks and the process yield decreases.

以上の伝統的な素子構造と製造方法の欠点を鑑み、新規な素子構造と製造方法が求められている。   In view of the drawbacks of the above-described traditional element structure and manufacturing method, a novel element structure and manufacturing method are required.

本発明の目的は素子のスクライビング（Ｓｃｒｉｂｉｎｇ）の歩留りを高めることにある。   An object of the present invention is to increase the yield of device scribing.

本発明のもう一つの目的は、サイズを縮小したフリップチップ発光ダイオード素子を提供することにある。   Another object of the present invention is to provide a flip chip light emitting diode device having a reduced size.

本発明の別の目的は、素子サイズ縮小時にも十分な電極間距離を具えている発光ダイオード素子を提供することにある。   Another object of the present invention is to provide a light emitting diode device having a sufficient interelectrode distance even when the device size is reduced.

本発明のまた別の目的は、輝度が均一な発光ダイオード素子を提供することにある。   Another object of the present invention is to provide a light emitting diode device having uniform brightness.

本発明のさらにまた別の目的は、生産歩留りと生産量を高めることができる発光ダイオードの製造方法を提供することにある。   Still another object of the present invention is to provide a method of manufacturing a light emitting diode capable of increasing the production yield and the production amount.

請求項１の発明は、
基板と、
該基板の上に位置し菱形輪郭を具え、該菱形輪郭の一対の平行辺が該基板の亀裂しやすい方向と平行である多層化合物半導体構造と、
該菱形輪郭の長い方の対角線の二端に位置して電流分布を均一とする第１電極と第２電極と、
を具えたことを特徴とする、発光ダイオード素子としている。
請求項２の発明は、請求項１記載の発光ダイオード素子において、基板がサファイヤ基板とされたことを特徴とする、発光ダイオード素子としている。
請求項３の発明は、請求項１記載の発光ダイオード素子において、多層化合物半導体構造が、
前記基板の上に位置する第１導電型の第１ドープ半導体層と、
該第１ドープ半導体層の上に位置する発光活性層と、
該発光活性層の上に位置する第２導電型の第２ドープ半導体層と、
該第２ドープ半導体層の上に位置する透光導体層と、
前記菱形輪郭の長い方の対角線の一端に位置してその深さが第１ドープ半導体層に至り、第１ドープ半導体層に接続された第２電極を収容し、並びに一部の第２ドープ半導体層、一部の発光活性層及び一部の第１ドープ半導体層を露出させる凹溝と、
該透光導体層、露出した第２ドープ半導体層、露出した発光活性層及び露出した第１ドープ半導体層を被覆して第１電極と第２電極を隔離する誘電層と、
を具えたことを特徴とする、発光ダイオード素子としている。
請求項４の発明は、請求項１記載の発光ダイオード素子において、第１電極と第２電極の上にフリップチップパッケージに供されるバンプが形成されたことを特徴とする、発光ダイオード素子としている。
請求項５の発明は、請求項１記載の発光ダイオード素子において、第１電極と第２電極の上に表面実装による接合に供されるバンプが形成されたことを特徴とする、発光ダイオード素子としている。
請求項６の発明は、請求項１記載の発光ダイオード素子において、第１電極と第２電極の上にフリップチップパッケージに供される導電樹脂が設けられたことを特徴とする、発光ダイオード素子としている。
請求項７の発明は、請求項１記載の発光ダイオード素子において、第１電極と第２電極の上に表面実装による接合に供される導電樹脂が設けられたことを特徴とする、発光ダイオード素子としている。
請求項８の発明は、
基板を提供する工程、
該基板の第１導電型を具えた第１ドープ半導体層を形成する工程、
該第１ドープ半導体層の上に発光活性層を形成する工程、
該発光活性層の上に第２導電型を具えた第２ドープ半導体層を形成する工程、
該第２ドープ半導体層の上に透光導体層を形成する工程、
複数の第１の菱形パターンの長い方の対角線の一端に位置する第１電極パターンを該透光導体層、第２ドープ半導体層と発光活性層を通り第１ドープ半導体層の所定の深さに進入するように転移させ、そのうち第１の菱形パターンの一辺とサファイヤ基板の亀裂を発生しやすい方向を平行とする工程、
誘電層で該基板を被覆する工程、
複数の第２の菱形パターンの長い方の対角線の二端の複数の第１電極と第２電極パターンを誘電層に転移させ並びに透光導体層と第１ドープ半導体層を露出させ、そのうち、第２の菱形パターンの一辺を該基板の亀裂を発生しやすい方向と平行とする工程、
複数の第１電極と複数の第２電極を第１ドープ半導体層と透光導体層に形成する工程、 該基板の亀裂を発生しやすい方向に沿って複数の菱形輪郭の素子をスクライビングする工程、
以上の工程からなる発光ダイオード素子の製造方法としている。
請求項９の発明は、請求項８記載の発光ダイオード素子の製造方法において、第１ドープ半導体層と第２ドープ半導体層をＭＯＣＶＤ法で形成することを特徴とする、発光ダイオード素子の製造方法としている。
請求項１０の発明は、請求項８記載の発光ダイオード素子の製造方法において、第１ドープ半導体層と第２ドープ半導体層をＭＢＥ法で形成することを特徴とする、発光ダイオード素子の製造方法としている。 The invention of claim 1
A substrate,
A multilayer compound semiconductor structure comprising a rhombus contour located on the substrate, wherein a pair of parallel sides of the rhombus contour is parallel to a direction in which the substrate is liable to crack;
A first electrode and a second electrode which are located at two ends of the longer diagonal of the rhombus outline and make the current distribution uniform;
The light emitting diode element is characterized by comprising:
According to a second aspect of the present invention, there is provided the light emitting diode element according to the first aspect, wherein the substrate is a sapphire substrate.
The invention of claim 3 is the light-emitting diode device according to claim 1, wherein the multilayer compound semiconductor structure is
A first doped semiconductor layer of a first conductivity type located on the substrate;
A light-emitting active layer located on the first doped semiconductor layer;
A second doped semiconductor layer of a second conductivity type located on the light emitting active layer;
A light transmissive conductor layer located on the second doped semiconductor layer;
Located at one end of the longer diagonal line of the rhombus outline, the depth reaches the first doped semiconductor layer, accommodates the second electrode connected to the first doped semiconductor layer, and part of the second doped semiconductor A groove exposing the layer, a part of the light emitting active layer and a part of the first doped semiconductor layer;
A dielectric layer that covers the light-transmissive conductor layer, the exposed second doped semiconductor layer, the exposed light-emitting active layer, and the exposed first doped semiconductor layer to isolate the first electrode and the second electrode;
The light emitting diode element is characterized by comprising:
According to a fourth aspect of the present invention, there is provided the light emitting diode element according to the first aspect, wherein bumps provided for the flip chip package are formed on the first electrode and the second electrode. .
According to a fifth aspect of the present invention, there is provided the light emitting diode element according to the first aspect, wherein a bump used for bonding by surface mounting is formed on the first electrode and the second electrode. Yes.
According to a sixth aspect of the present invention, there is provided the light emitting diode element according to the first aspect, wherein a conductive resin used for a flip chip package is provided on the first electrode and the second electrode. Yes.
The invention of claim 7 is the light emitting diode element according to claim 1, characterized in that a conductive resin for bonding by surface mounting is provided on the first electrode and the second electrode. It is said.
The invention of claim 8
Providing a substrate;
Forming a first doped semiconductor layer having a first conductivity type of the substrate;
Forming a light emitting active layer on the first doped semiconductor layer;
Forming a second doped semiconductor layer having a second conductivity type on the light emitting active layer;
Forming a translucent conductor layer on the second doped semiconductor layer;
The first electrode pattern located at one end of the longer diagonal line of the plurality of first rhombus patterns passes through the light-transmitting conductive layer, the second doped semiconductor layer, and the light emitting active layer to a predetermined depth of the first doped semiconductor layer. A step of making transition so that one side of the first rhombus pattern is parallel to a direction in which cracks of the sapphire substrate are likely to occur,
Coating the substrate with a dielectric layer;
Transferring a plurality of first electrodes and second electrode patterns at two ends of a longer diagonal of the plurality of second rhombus patterns to a dielectric layer, and exposing the light-transmitting conductor layer and the first doped semiconductor layer, A step of making one side of the rhombus pattern of 2 parallel to a direction in which cracks of the substrate tend to occur,
Forming a plurality of first electrodes and a plurality of second electrodes on the first doped semiconductor layer and the light-transmitting conductor layer; scribing a plurality of rhombus-shaped elements along a direction in which cracks of the substrate are likely to occur;
The light emitting diode device manufacturing method including the above steps is used.
The invention of claim 9 is the method for manufacturing a light emitting diode element according to claim 8, wherein the first doped semiconductor layer and the second doped semiconductor layer are formed by MOCVD. Yes.
According to a tenth aspect of the present invention, in the method for manufacturing a light-emitting diode element according to the eighth aspect, the first doped semiconductor layer and the second doped semiconductor layer are formed by an MBE method. Yes.

本発明はサファイヤ基板結晶格子配列の特性を利用し、結晶の亀裂を発生しやすい方向に沿ってウエハをスクライビングし並びに菱形輪郭を具えた発光ダイオード素子を形成する。これにより大きな発光面積を具え、電極距離が遠い発光ダイオード素子を提供でき、また発光ダイオード素子の製造工程の生産歩留りと生産量を高め、特にスクライビング時の歩留りと素子サイズ縮小時の電流輻輳を防止できる。このほか、フリップチップパッケージ方式を使用した製造方法及び電極を菱形輪郭の対角線に置くことにより、発光輝度を均一とし、並びに小さいフリップチップパッケージ素子を製造することができる。   The present invention utilizes the characteristics of a sapphire substrate crystal lattice arrangement to scribe a wafer along a direction in which crystal cracks are likely to occur, and to form a light emitting diode element having a rhombus outline. This makes it possible to provide a light emitting diode device with a large light emitting area and a long electrode distance, and increase the production yield and output of the manufacturing process of the light emitting diode device, especially preventing the yield at the time of scribing and the current congestion when the device size is reduced. it can. In addition, by placing the manufacturing method using the flip chip package method and the electrodes on the diagonal line of the rhombus outline, the emission luminance can be made uniform and a small flip chip package element can be manufactured.

本発明の製造方法は以下の工程を具えている。まず、基板を提供し、続いて、第１導電型を具えた第１ドープ半導体層を該基板の上に形成する。その後、発光活性層を第１ドープ半導体層の上に形成する。続いて、第２導電型を具えた第２ドープ半導体層を該発光活性層の上に形成する。その後、透光導体層を第２ドープ半導体層の上に形成し、並びに複数の第１菱形パターンの長い方の対角線の一端に位置する複数の第１電極パターンを該透光導体層、該第２ドープ半導体層と発光活性層及び第１ドープ半導体層の所定の深さまで進入するようにして転移させる。そのうち、第１菱形パターンの一辺と該基板の亀裂を発生しやすい方向は平行とする。続いて、誘電層に該基板を被覆させ、並びに複数の第２菱形パターンの長い方の対角線の二端の複数の第１及び第２電極パターンを該誘電層に転移させ並びに透光導体層と第１ドープ半導体層を露出させ、そのうち第２菱形パターンの一辺と該基板の亀裂を発生しやすい方向を平行とする。その後、複数の第１電極と複数の第２電極を第１ドープ半導体層と該透光導体層に形成する。該基板の亀裂を発生しやすい方向に沿って菱形輪郭を具えた複数の素子をスクライビングして形成し、フリップチップパッケージ方式で該素子の該第１電極と該第２電極をソルダバンプで二つの素子の固定電極に接続する。   The manufacturing method of the present invention includes the following steps. First, a substrate is provided, and then a first doped semiconductor layer having a first conductivity type is formed on the substrate. Thereafter, a light emitting active layer is formed on the first doped semiconductor layer. Subsequently, a second doped semiconductor layer having a second conductivity type is formed on the light emitting active layer. Thereafter, a translucent conductor layer is formed on the second doped semiconductor layer, and a plurality of first electrode patterns positioned at one end of the longer diagonal line of the plurality of first rhombus patterns are formed on the translucent conductor layer, the first The two-doped semiconductor layer, the light emitting active layer, and the first doped semiconductor layer are transferred so as to enter a predetermined depth. Among them, one side of the first rhombus pattern is parallel to the direction in which the substrate is likely to crack. Subsequently, the dielectric layer is coated with the substrate, and a plurality of first and second electrode patterns at two ends of the longer diagonal line of the plurality of second rhombus patterns are transferred to the dielectric layer, and The first doped semiconductor layer is exposed, and one side of the second rhombus pattern is parallel to the direction in which the substrate is likely to crack. Thereafter, a plurality of first electrodes and a plurality of second electrodes are formed on the first doped semiconductor layer and the light transmitting conductor layer. A plurality of elements having a rhombus outline are formed by scribing along a direction in which cracks of the substrate are likely to occur, and two elements are formed by solder bumps for the first electrode and the second electrode of the element in a flip chip package system. Connect to the fixed electrode.

本発明と周知の技術の機能を比較すると、周知の化合物半導体発光ダイオードは電極接点を発光面の対角線の両端に置かねばならず、ゆえに発光ダイオードの発光面積を実質的に縮小し、且つ輝度を不均一とした。本発明はサファイヤ基板の結晶格子配列の特性を利用し、その格子の亀裂を発生しやすい方向に沿ってウエハをスクライビングし並びに菱形輪郭を具えた発光ダイオード素子を形成し、これにより大きな発光面積を有する発光ダイオード素子を形成し、また、発光ダイオード素子製造工程の生産歩留りと生産量を増す。このほか、フリップチップパッケージの製造方法を利用し、及び菱形輪郭の対角線に電極を置くことにより、信頼性の高いフリップチップパッケージの製品を製造することができる。   Comparing the functions of the present invention with known techniques, known compound semiconductor light emitting diodes must have electrode contacts placed at opposite ends of the light emitting surface, thus substantially reducing the light emitting area of the light emitting diode and increasing the brightness. It was uneven. The present invention utilizes the characteristics of the crystal lattice arrangement of the sapphire substrate, scribing the wafer along the direction in which cracks of the lattice are likely to occur, and forming a light emitting diode element having a rhombus outline, thereby increasing the light emitting area. The light emitting diode element is formed, and the production yield and production amount of the light emitting diode element manufacturing process are increased. In addition, a flip chip package product with high reliability can be manufactured by using a flip chip package manufacturing method and placing electrodes on diagonal lines of a rhombus outline.

図１に示されるのは、本発明の発光ダイオード素子１０である。この発光ダイオード素子１０は、基板１０２を具え、該基板１０２の上に多層化合物半導体構造、例えば窒化ガリウム系化合物半導体層が設けられる。この多層化合物半導体構造はＭＯＣＶＤで形成されるが、ＭＢＥ或いはその他の化学気相成長法により形成可能である。この多層化合物半導体構造は半導体層１０６、１０８、１１０を具えている。   Shown in FIG. 1 is a light emitting diode device 10 of the present invention. The light emitting diode element 10 includes a substrate 102 on which a multilayer compound semiconductor structure, for example, a gallium nitride compound semiconductor layer is provided. This multilayer compound semiconductor structure is formed by MOCVD, but can be formed by MBE or other chemical vapor deposition. This multilayer compound semiconductor structure comprises semiconductor layers 106, 108, 110.

発光ダイオード素子１０は別に透光導電層１０４を具えている。この透光導電層１０４は透光導体層（Ｔｒａｎｓｐａｒｅｎｔ Ｃｏｎｄｕｃｔｉｖｅ Ｌａｙｅｒ；ＴＣＬ）とされ、半導体層１０８は活性（発光）層（Ａｃｔｉｖｅ Ｌａｙｅｒ）を具えている。半導体層１０６と１１０は相反する導電性質（ｎ型或いはｐ型）を具えた半導体層であり、すなわち、半導体層１０６と１１０は多層構造を具えうる。この多層構造は、アンドープの半導体層をバッファ層（Ｂｕｆｆｅｒ Ｌａｙｅｒ）或いはクラッド層（Ｃｌａｄｄｉｎｇ Ｌａｙｅｒ）として具えるか、或いはＡｌＧａＮ／ＧａＮ及びＩｎＧａＮ等の層の組合せとされうる。   The light emitting diode element 10 includes a light transmitting conductive layer 104. The translucent conductive layer 104 is a translucent conductive layer (TCL), and the semiconductor layer 108 includes an active (light emitting) layer (Active Layer). The semiconductor layers 106 and 110 are semiconductor layers having opposite conductive properties (n-type or p-type), that is, the semiconductor layers 106 and 110 can have a multilayer structure. This multi-layer structure can include an undoped semiconductor layer as a buffer layer or a cladding layer, or a combination of layers such as AlGaN / GaN and InGaN.

本発明の菱形輪郭を具えた発光ダイオード素子は、各種の製造方法により形成されうる。一種の製造方法は、まず、エピタキシーで半導体層１０６、１０８、１１０を形成し、続いて半導体層１１０、１０８、及び１０６の一部をエッチングして凹溝を形成して電極を収容し並びに半導体層１０６に接続し、さらに透光導電層１０４と透明誘電層１１２を形成する。続いて、電極を菱形パターンの長い方の対角線の両端に形成し、最後に図２に示されるようにスクライビング方式で本発明の発光ダイオード素子を形成する。本発明の菱形輪郭を具えた発光ダイオード素子はその他の製造方法によっても製造可能である。図１に示される電極１１４、１１６と導体層（電極１１８）は僅かに一例にすぎず、これに限定されるものではない。電極１１４と１１６は同じ材料を使用し且つ同時に形成されるか、或いは異なる材料を使用しうる。或いは電極１１８は省略可能である。菱形パターンと電極の形成にはマウク、リソグラフィーとエッチング工程を利用できる。電極１１４と１１６と１１８及び透光導電層１０４はリソグラフィーと物理／化学堆積法或いは伝統的な蒸着方式により形成可能である。誘電層１１２は半導体層１０６と１１０を隔離する。半導体層１０６と１１０は電極１１６と１１４を通して駆動回路に接続される。誘電層１１２は二酸化ケイ素層とされうるが、それに限定されるわけではなく、窒化けい素或いは透明の高分子層とされうる。誘電層１１２はリソグラフィー、エッチングと化学気相成長法或いは伝統的な蒸着法で形成されうる。誘電層１１２はフリップチップ素子に対して必要であるが、フリップチップ素子でないものに対しては省略可能である。   The light emitting diode element having a rhombus outline of the present invention can be formed by various manufacturing methods. In one type of manufacturing method, first, the semiconductor layers 106, 108, and 110 are formed by epitaxy, and then a part of the semiconductor layers 110, 108, and 106 are etched to form concave grooves to accommodate the electrodes and the semiconductors A light-transmitting conductive layer 104 and a transparent dielectric layer 112 are formed in contact with the layer 106. Subsequently, electrodes are formed on both ends of the longer diagonal of the rhombus pattern, and finally the light emitting diode element of the present invention is formed by a scribing method as shown in FIG. The light emitting diode device having a rhombus outline according to the present invention can be manufactured by other manufacturing methods. The electrodes 114 and 116 and the conductor layer (electrode 118) shown in FIG. 1 are only an example, and the present invention is not limited thereto. The electrodes 114 and 116 may use the same material and be formed simultaneously, or different materials may be used. Alternatively, the electrode 118 can be omitted. Mauch, lithography and etching processes can be used to form the diamond pattern and the electrodes. The electrodes 114, 116, and 118 and the transparent conductive layer 104 can be formed by lithography and physical / chemical deposition methods or traditional deposition methods. Dielectric layer 112 isolates semiconductor layers 106 and 110. The semiconductor layers 106 and 110 are connected to a driving circuit through electrodes 116 and 114. The dielectric layer 112 may be a silicon dioxide layer, but is not limited thereto, and may be silicon nitride or a transparent polymer layer. The dielectric layer 112 may be formed by lithography, etching and chemical vapor deposition, or a traditional deposition method. The dielectric layer 112 is required for flip chip elements, but can be omitted for non-flip chip elements.

もし窒化ガリウム（ＧａＮ）化合物半導体を使用するなら、基板１０２は六角格子（Ｈｅｘａｇｏｎａｌ Ｌａｔｔｉｃｅ）のサファイヤ（Ｓａｐｐｈｉｒｅ）基板とされ、半導体層１０６と１１０は第１導電型の第１ドープ窒化ガリウム半導体層と第２導電型の第２ドープ窒化ガリウム半導体層を具える。半導体層１０６と１１０は同時にアンドープ窒化ガリウムバッファ層或いはクラッド層を具えうる。半導体層１０６と１１０はｎ型層或いはｐ型層とされ、電極１１４と１１６はｐ型電極とｎ型電極層とされる。このほか、基板１０２はまた炭化ケイ素基板或いはその他の高温に耐え且つ透明な基板とされうる。   If a gallium nitride (GaN) compound semiconductor is used, the substrate 102 is a hexagonal lattice sapphire substrate, and the semiconductor layers 106 and 110 are first conductivity type first doped gallium nitride semiconductor layers. A second conductivity type second doped gallium nitride semiconductor layer is provided. The semiconductor layers 106 and 110 can simultaneously comprise an undoped gallium nitride buffer layer or a cladding layer. The semiconductor layers 106 and 110 are n-type layers or p-type layers, and the electrodes 114 and 116 are p-type electrodes and n-type electrode layers. In addition, the substrate 102 can also be a silicon carbide substrate or other high temperature and transparent substrate.

図２は図１の発光ダイオード素子１０を具えたウエハ１の平面図である。図１に示される発光ダイオード素子１０は平面視によると菱形輪郭を具え、電極１１４と１１８は長い方の対角線の両端に位置し、これは図３に示されるとおりである。図４と図５は異なる形態の電極１１４と１１８を表示する。図４に示される電極１１４は二つの延伸領域を具え、電極１１４と１１８の間の距離はどこであっても差が大き過ぎない。図５に示される電極１１４と１１８はそれぞれ一つの延伸領域を具え、電極１１４と１１８の間の距離はどこでも十分に均一である。スクライビングのために発光ダイオード素子の図３に示される切断線上に溝を形成可能である。   FIG. 2 is a plan view of the wafer 1 including the light emitting diode element 10 of FIG. The light-emitting diode element 10 shown in FIG. 1 has a rhombus outline in plan view, and the electrodes 114 and 118 are located at both ends of the longer diagonal line, as shown in FIG. 4 and 5 display different forms of electrodes 114 and 118. The electrode 114 shown in FIG. 4 comprises two stretched regions, and the difference between the electrodes 114 and 118 is not too great wherever the distance is. The electrodes 114 and 118 shown in FIG. 5 each have one stretch region, and the distance between the electrodes 114 and 118 is sufficiently uniform everywhere. A groove can be formed on the cutting line shown in FIG. 3 for the light emitting diode element for scribing.

図６を参照されたい。本発明の発光ダイオード素子１０はバンプ１６と１８で素子固定電極１２、１４の上に固定される。電極１２、１４は回路に接続され、これにより本発明の発光ダイオード素子１０が発光ダイオードランプに形成される。発光ダイオード素子１０はフリップチップパッケージ方式で電極１１４と１１８がバンプ１６と１８と接合される。ただし上述の構造はフリップチップパッケージ方式による結合に限定されるわけではなく、表面実装技術による接合も可能である。図１に示される電極１１８は並びに必要でない。図６中のバンプ１６と１８の代わりに導電樹脂を使用可能である。上述の構造はフリップチップパッケージ方式による結合に限定されるわけではなく、表面実装技術による接合も使用可能である。   See FIG. The light emitting diode element 10 of the present invention is fixed on the element fixing electrodes 12 and 14 by bumps 16 and 18. The electrodes 12 and 14 are connected to a circuit, whereby the light emitting diode element 10 of the present invention is formed in a light emitting diode lamp. In the light emitting diode element 10, electrodes 114 and 118 are bonded to bumps 16 and 18 in a flip chip package system. However, the above-described structure is not limited to the bonding by the flip chip package method, and bonding by surface mounting technology is also possible. The electrode 118 shown in FIG. 1 is not necessary as well. A conductive resin can be used in place of the bumps 16 and 18 in FIG. The above-described structure is not limited to the bonding by the flip chip package method, and bonding by surface mounting technology can also be used.

図７は本発明の発光ダイオード素子１０をフリップチップパッケージ方式で基板１２２の電極コンタクトパッド１２０に固定した状態を示す。電極コンタクトパッド１２０は回路に接続される。発光ダイオード素子１０はフリップチップパッケージ方式で、電極１１４と１１８がそれぞれコンタクトパッド１２０とはんだ付けされるか或いは導電樹脂で接合される。上述の構造はフリップチップパッケージ方式による結合に限定されるわけではなく、表面実装技術による接合も可能である。   FIG. 7 shows a state in which the light emitting diode device 10 of the present invention is fixed to the electrode contact pad 120 of the substrate 122 by the flip chip package method. The electrode contact pad 120 is connected to the circuit. The light-emitting diode element 10 is a flip-chip package method, and the electrodes 114 and 118 are soldered to the contact pads 120 or bonded with a conductive resin. The above-described structure is not limited to the bonding by the flip chip package method, and bonding by surface mounting technology is also possible.

本発明の実施例の半導体発光ダイオード素子の構造表示図である。It is a structure display figure of the semiconductor light emitting diode element of the Example of this invention. 図１の発光ダイオード素子を具えたウエハの平面図である。It is a top view of the wafer provided with the light emitting diode element of FIG. 本発明の実施例の半導体発光ダイオード素子の平面図である。It is a top view of the semiconductor light emitting diode element of the Example of this invention. 本発明の別の実施例の半導体発光ダイオード素子の平面図である。It is a top view of the semiconductor light emitting diode element of another Example of this invention. 本発明のさらに別の実施例の半導体発光ダイオード素子の平面図である。It is a top view of the semiconductor light-emitting-diode element of another Example of this invention. 本発明の半導体発光ダイオード素子をフリップチップパッケージ方式で素子固定電極の上に固定した状態表示図である。It is a state display figure which fixed the semiconductor light-emitting diode element of this invention on the element fixed electrode by the flip-chip package system. 本発明の半導体発光ダイオード素子をフリップチップパッケージ方式で基板上に固定した状態表示図である。It is a state display figure which fixed the semiconductor light emitting diode element of this invention on the board | substrate by the flip-chip package system.

符号の説明Explanation of symbols

１ ウエハ
１０ 発光ダイオード素子
１２ 電極
１４ 電極
１６ バンプ
１８ バンプ
１０２ 基板
１０４ 透光導電層
１０６ 半導体層
１０８ 半導体層
１１０ 半導体層
１１２ 誘電層
１１８ 電極
１２０ コンタクトパッド
１２２ 基板
DESCRIPTION OF SYMBOLS 1 Wafer 10 Light emitting diode element 12 Electrode 14 Electrode 16 Bump 18 Bump 102 Substrate 104 Translucent conductive layer 106 Semiconductor layer 108 Semiconductor layer 110 Semiconductor layer 112 Dielectric layer 118 Electrode 120 Contact pad 122 Substrate

Claims (10)

基板と、
該基板の上に位置し菱形輪郭を具え、該菱形輪郭の一対の平行辺が該基板の亀裂しやすい方向と平行である多層化合物半導体構造と、
該菱形輪郭の長い方の対角線の二端に位置して電流分布を均一とする第１電極と第２電極と、
を具えたことを特徴とする、発光ダイオード素子。 A substrate,
A multilayer compound semiconductor structure comprising a rhombus contour located on the substrate, wherein a pair of parallel sides of the rhombus contour is parallel to a direction in which the substrate is liable to crack;
A first electrode and a second electrode which are located at two ends of the longer diagonal of the rhombus outline and make the current distribution uniform;
A light-emitting diode element comprising: 請求項１記載の発光ダイオード素子において、基板がサファイヤ基板とされたことを特徴とする、発光ダイオード素子。   2. The light emitting diode element according to claim 1, wherein the substrate is a sapphire substrate. 請求項１記載の発光ダイオード素子において、多層化合物半導体構造が、
前記基板の上に位置する第１導電型の第１ドープ半導体層と、
該第１ドープ半導体層の上に位置する発光活性層と、
該発光活性層の上に位置する第２導電型の第２ドープ半導体層と、
該第２ドープ半導体層の上に位置する透光導体層と、
前記菱形輪郭の長い方の対角線の一端に位置してその深さが第１ドープ半導体層に至り、第１ドープ半導体層に接続された第２電極を収容し、並びに一部の第２ドープ半導体層、一部の発光活性層及び一部の第１ドープ半導体層を露出させる凹溝と、
該透光導体層、露出した第２ドープ半導体層、露出した発光活性層及び露出した第１ドープ半導体層を被覆して第１電極と第２電極を隔離する誘電層と、
を具えたことを特徴とする、発光ダイオード素子。 The light emitting diode device according to claim 1, wherein the multilayer compound semiconductor structure is
A first doped semiconductor layer of a first conductivity type located on the substrate;
A light-emitting active layer located on the first doped semiconductor layer;
A second doped semiconductor layer of a second conductivity type located on the light emitting active layer;
A light transmissive conductor layer located on the second doped semiconductor layer;
Located at one end of the longer diagonal line of the rhombus outline, the depth reaches the first doped semiconductor layer, accommodates the second electrode connected to the first doped semiconductor layer, and part of the second doped semiconductor A groove exposing the layer, a part of the light emitting active layer and a part of the first doped semiconductor layer;
A dielectric layer that covers the light-transmissive conductor layer, the exposed second doped semiconductor layer, the exposed light-emitting active layer, and the exposed first doped semiconductor layer to isolate the first electrode and the second electrode;
A light-emitting diode element comprising: 請求項１記載の発光ダイオード素子において、第１電極と第２電極の上にフリップチップパッケージに供されるバンプが形成されたことを特徴とする、発光ダイオード素子。   2. The light emitting diode device according to claim 1, wherein bumps provided for a flip chip package are formed on the first electrode and the second electrode. 請求項１記載の発光ダイオード素子において、第１電極と第２電極の上に表面実装による接合に供されるバンプが形成されたことを特徴とする、発光ダイオード素子。   2. The light emitting diode element according to claim 1, wherein bumps provided for bonding by surface mounting are formed on the first electrode and the second electrode. 請求項１記載の発光ダイオード素子において、第１電極と第２電極の上にフリップチップパッケージに供される導電樹脂が設けられたことを特徴とする、発光ダイオード素子。   2. The light emitting diode element according to claim 1, wherein a conductive resin used for a flip chip package is provided on the first electrode and the second electrode. 請求項１記載の発光ダイオード素子において、第１電極と第２電極の上に表面実装による接合に供される導電樹脂が設けられたことを特徴とする、発光ダイオード素子。   2. The light emitting diode element according to claim 1, wherein a conductive resin used for bonding by surface mounting is provided on the first electrode and the second electrode. 基板を提供する工程、
該基板の第１導電型を具えた第１ドープ半導体層を形成する工程、
該第１ドープ半導体層の上に発光活性層を形成する工程、
該発光活性層の上に第２導電型を具えた第２ドープ半導体層を形成する工程、
該第２ドープ半導体層の上に透光導体層を形成する工程、
複数の第１の菱形パターンの長い方の対角線の一端に位置する第１電極パターンを該透光導体層、第２ドープ半導体層と発光活性層を通り第１ドープ半導体層の所定の深さに進入するように転移させ、そのうち第１の菱形パターンの一辺とサファイヤ基板の亀裂を発生しやすい方向を平行とする工程、
誘電層で該基板を被覆する工程、
複数の第２の菱形パターンの長い方の対角線の二端の複数の第１電極と第２電極パターンを誘電層に転移させ並びに透光導体層と第１ドープ半導体層を露出させ、そのうち、第２の菱形パターンの一辺を該基板の亀裂を発生しやすい方向と平行とする工程、
複数の第１電極と複数の第２電極を第１ドープ半導体層と透光導体層に形成する工程、 該基板の亀裂を発生しやすい方向に沿って複数の菱形輪郭の素子をスクライビングする工程、
以上の工程からなる発光ダイオード素子の製造方法。 Providing a substrate;
Forming a first doped semiconductor layer having a first conductivity type of the substrate;
Forming a light emitting active layer on the first doped semiconductor layer;
Forming a second doped semiconductor layer having a second conductivity type on the light emitting active layer;
Forming a translucent conductor layer on the second doped semiconductor layer;
The first electrode pattern located at one end of the longer diagonal line of the plurality of first rhombus patterns passes through the light-transmitting conductive layer, the second doped semiconductor layer, and the light emitting active layer to a predetermined depth of the first doped semiconductor layer. A step of making transition so that one side of the first rhombus pattern is parallel to a direction in which cracks of the sapphire substrate are likely to occur,
Coating the substrate with a dielectric layer;
Transferring a plurality of first electrodes and second electrode patterns at two ends of a longer diagonal of the plurality of second rhombus patterns to a dielectric layer, and exposing the light-transmitting conductor layer and the first doped semiconductor layer, A step of making one side of the rhombus pattern of 2 parallel to a direction in which cracks of the substrate tend to occur,
Forming a plurality of first electrodes and a plurality of second electrodes on the first doped semiconductor layer and the light-transmitting conductor layer; scribing a plurality of rhombus-shaped elements along a direction in which cracks of the substrate are likely to occur;
The manufacturing method of the light emitting diode element which consists of the above process. 請求項８記載の発光ダイオード素子の製造方法において、第１ドープ半導体層と第２ドープ半導体層をＭＯＣＶＤ法で形成することを特徴とする、発光ダイオード素子の製造方法。   9. The method for manufacturing a light-emitting diode element according to claim 8, wherein the first doped semiconductor layer and the second doped semiconductor layer are formed by MOCVD. 請求項８記載の発光ダイオード素子の製造方法において、第１ドープ半導体層と第２ドープ半導体層をＭＢＥ法で形成することを特徴とする、発光ダイオード素子の製造方法。
9. The method for manufacturing a light emitting diode element according to claim 8, wherein the first doped semiconductor layer and the second doped semiconductor layer are formed by an MBE method.
JP2004007263A 2004-01-14 2004-01-14 Light emitting diode element and manufacturing method thereof Pending JP2005203516A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007173575A (en) * 2005-12-22 2007-07-05 Showa Denko Kk Light-emitting diode and manufacturing method thereof
CN101807660A (en) * 2010-04-02 2010-08-18 中国科学院苏州纳米技术与纳米仿生研究所 Chip for flip type opto-electronic device
JP2019216254A (en) * 2010-02-09 2019-12-19 晶元光電股▲ふん▼有限公司Ｅｐｉｓｔａｒ Ｃｏｒｐｏｒａｔｉｏｎ Photoelectric element and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007173575A (en) * 2005-12-22 2007-07-05 Showa Denko Kk Light-emitting diode and manufacturing method thereof
JP2019216254A (en) * 2010-02-09 2019-12-19 晶元光電股▲ふん▼有限公司Ｅｐｉｓｔａｒ Ｃｏｒｐｏｒａｔｉｏｎ Photoelectric element and manufacturing method thereof
CN101807660A (en) * 2010-04-02 2010-08-18 中国科学院苏州纳米技术与纳米仿生研究所 Chip for flip type opto-electronic device

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