KR101203138B1 - Luminous device and the method therefor - Google Patents

Abstract

The light emitting device of the present invention includes a first semiconductor layer on a substrate, a second semiconductor layer formed on one region of the first semiconductor layer, and an active layer interposed between the first semiconductor layer and the second semiconductor layer. A plurality of light emitting cells, a first electrode layer of one light emitting cell, and a connection electrode electrically connected to a second semiconductor layer of another adjacent light emitting cell are provided, and the light emitting cells flip-bonded to a submount substrate through metal bumps. And an anti-reflection layer formed on the surface of the substrate and the light emitting cells except for the connection electrode, the light emission efficiency is increased by maximizing the reflectance so that the light emitted from the active layer is reflected toward the substrate.

Light emitting element, light emitting cell, metal bump, reflective layer, antireflective layer

Description

Light emitting device and manufacturing method {Luminous device and the method therefor}

1 is a conceptual cross-sectional view for explaining a light emitting device having a conventional flip chip structure;

2 is a partial cross-sectional view showing an embodiment of a light emitting cell for flip chip according to the present invention;

3 to 12 are views illustrating a manufacturing process for manufacturing a flip chip light emitting device according to the present invention.

<Brief Description of Major Codes in Drawings>

100: light emitting cell 110: substrate

120: buffer layer 130: first semiconductor layer

131 electrode 140 active layer

150: second semiconductor layer 151: transparent electrode

160: antireflection layer 170: metal wiring

180: metal bump

210: substrate 220: dielectric film

230: electrode layer 250: reflective layer

The present invention relates to a light emitting device, and more particularly, to a light emitting device in the form of a flip chip and a method of manufacturing the same.

A light emitting diode refers to a device that produces a minority carrier (electron or hole) injected by using a p-n junction structure of a semiconductor, and emits predetermined light by recombination thereof. Such light emitting diodes are used as display devices and backlights, and active research is being conducted to apply them to general lighting applications.

This is because a light emitting diode consumes only a few to several tens of power and a lifetime of several to several tens of times compared to a conventional light bulb or a fluorescent lamp, and is superior in terms of power consumption reduction and durability.

1 is a conceptual cross-sectional view for describing a light emitting device having a conventional flip chip structure. Referring to FIG. 1, a light emitting cell forms a first electrode 12 and a second electrode 14 on a predetermined substrate 10. A P-type connection electrode (not shown) is formed on the first electrode 12, and an N-type connection electrode (not shown) is formed on the second electrode 14. Next, the light emitting cells are bonded to the submount substrate 20, wherein the first electrode 12 is connected to the first bump 22 through the P-type connecting electrode, and the second electrode 14 is connected to the N-type connecting electrode. Bonding to the second bump 24.

However, the conventional light emitting device having a flip chip structure has a problem in that light emitted from the light emitting cells is reflected through the substrate 10 and absorbed toward the submount substrate 20, thereby reducing light efficiency.

The present invention has been made to solve the problems described above, an object of the present invention to provide a light emitting device for emitting light generated by the light emitting device to the outside effectively and a method of manufacturing the same.

The present invention for achieving the above object is interposed between a first semiconductor layer on the substrate, a second semiconductor layer formed on one region of the first semiconductor layer and between the first semiconductor layer and the second semiconductor layer. A plurality of light emitting cells including the active layer, a first semiconductor layer of one light emitting cell, and a connecting electrode to which the second semiconductor layer of another adjacent light emitting cell is electrically connected are provided, and flipped to the submount substrate through metal bumps. Provided is a light emitting device including the light emitting cells bonded to each other and an antireflection layer formed on a surface of the substrate and the light emitting cells except for the connection electrode.

The antireflection layer is preferably formed to a thickness of wavelength / (4 × refractive index).

It is preferable that the sub-mount substrate is provided with a reflective layer.

The present invention also provides a plurality of semiconductor layers including a first semiconductor layer, a second semiconductor layer formed on one region of the first semiconductor layer, and an active layer interposed between the first semiconductor layer and the second semiconductor layer. Forming light emitting cells, electrically connecting two adjacent light emitting cells, forming a reflective layer on the sub-mount substrate, and forming metal bumps on the light emitting cells to flip bond to the submount substrate. Provide a method.

The substrate may be further separated from the light emitting cells to expose the first semiconductor layer.

The method may further include partially etching the exposed surfaces of the first semiconductor layers to form a roughened surface.

The present invention provides a package including a lead frame having metal leads and a light emitting device positioned on the lead frame, wherein the light emitting device and the metal leads are electrically connected to each other.

Hereinafter, an embodiment of a light emitting device according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a partial cross-sectional view showing an embodiment of a flip chip light emitting cell according to the present invention, Figures 3 to 12 are views showing a manufacturing process for manufacturing a flip chip light emitting device according to the present invention.

As shown in these drawings, the light emitting device according to the present invention is for flip chip, and the light emitting cell 100 includes a buffer layer 120 formed on the substrate 110 and a first semiconductor layer formed on the buffer layer 120. 130, an active layer 140 formed on a portion of the first semiconductor layer 130, a second semiconductor layer 150 formed on the active layer 140, and an anti-reflection layer 160. Here, it is preferable that the first semiconductor layer 130 is an N-type semiconductor layer, and the second semiconductor layer 150 is a P-type semiconductor layer.

The substrate 110 is a conventional wafer for fabricating a light emitting diode, and may use at least one of Al₂O ₃, SiC, ZnO, Si, GaAs, GaP, LiAl₂O₃, BN, AIN, and GaN. The substrate 110 is selected in consideration of the lattice constant of the semiconductor layer to be formed thereon. For example, when a GaN-based semiconductor layer is formed on the substrate 110, the substrate 110 may be made of sapphire.

A buffer layer 120 may be formed on the substrate 110 to serve as a buffer when the first semiconductor layer 130 to be described later is formed. The buffer layer 120 may reduce lattice mismatch between the substrate 110 and subsequent layers during crystal growth. The buffer layer 120 may be formed of nitride such as AlN or GaN. In addition, the buffer layer 120 may be spaced apart from each other in units of cells, but is not limited thereto. When the buffer layer 120 is formed of an insulating material or a semi-insulating material, the buffer layers 120 may be continuous with each other. However, since the buffer layer 120 may not be formed, the present invention is not limited thereto.

The first semiconductor layer 130 (hereinafter referred to as an 'N-type semiconductor layer') is an electron generation layer, and the N-type semiconductor layer 130 is formed of an N-type compound semiconductor layer and an N-type cladding layer. In this case, it is preferable that the N-type semiconductor layer 130 uses a GaN film into which N-type impurities are injected. However, the present invention is not limited thereto, and material layers having various semiconductor properties are possible. In the present embodiment, an N-type semiconductor layer 130 including an N-type Al _x Ga _{1 - x} N (0 ≦ _x ≦ 1) film may be formed.

The second semiconductor layer 150 (hereinafter referred to as a 'P-type semiconductor layer') may be a hole generation layer, and the P-type semiconductor layer 150 may be formed of a P-type cladding layer and a P-type compound semiconductor layer. . At this time, the P-type semiconductor layer 150 uses AlGaN implanted with P-type impurities. In this embodiment, a P-type semiconductor layer 150 including a P-type Al _x Ga _{1 - x} N (0 ≦ _x ≦ 1) film is formed. In addition, an InGaN film may be used as the P-type semiconductor layer film.

The N-type semiconductor layer 130 and the P-type semiconductor layer 150 may be formed of a multilayer film.

The active layer 140 is a region where electrons and holes are recombined, and a multilayer film in which a quantum well layer and a barrier layer are repeatedly formed on the N-type semiconductor layer 130 may be used. As the barrier layer and the well layer, binary compounds GaN, InN, AIN, etc. may be used, and ternary compounds In _x Ga _{1- x} N (0≤x≤1) and Al _x Ga _{1 - x} N (0≤x≤ 1) and the like, and the quaternary compound Al _x In _y Ga _1-xy N (0 ≦ x, y, x + y ≦ 1) may be used. Of course, the N-type semiconductor layer 130 and the P-type semiconductor layer 150 may be formed by implanting predetermined impurities into the binary or quaternary compounds. Herein, the emission wavelength generated by the combination of electrons and holes in the active layer 140 is changed according to the type of material forming the active layer 140. Therefore, it is preferable that the active layer 140 adjusts a material included according to a target wavelength.

The active layer 140 is located on a portion of the N-type semiconductor layer 130, and the P-type semiconductor layer 150 is located on the active layer 140. Accordingly, a portion of the N-type semiconductor layer 130 is covered by an upper surface of the active layer 140 and the P-type semiconductor layer 150, the remaining portion is exposed.

Meanwhile, since the light emitted from the active layer 140 should be emitted toward the submount substrate to be described later, the antireflection layer 160 is formed to have a thickness of wavelength / (4 × refractive index) so that the light is reflected toward the substrate 110. Serves to prevent this from happening. The anti-reflection layer 160 includes the substrate 110, the buffer layer 120, the N-type semiconductor layer 130, the active layer 140, and the P-type semiconductor layer 150, which are sequentially stacked, and then the light emitting cell 100. It is formed on the side of the substrate 110 and the light emitting cell 100 in a state separated by.

An additional transparent electrode 151 is further formed on the P-type semiconductor layer 150 to reduce the resistance of the P-type semiconductor layer 150. The transparent electrode 151 may be indium tin oxide (ITO) or ITO oxide as a transparent conductor. In addition, a reflective metal layer (not shown) may be formed on the transparent electrode 151. The reflective metal layer may be formed of a single layer or a multilayer. The reflective metal layer may be formed of silver (Ag), and barrier metal layers for preventing diffusion of silver (Ag) may be further formed above and below the reflective metal layer. The reflective metal layer reflects light generated from the active layer 140 toward the substrate 110.

The electrode 131 may be further included on the N-type semiconductor layer 130. In addition, an additional ohmic metal layer may be further formed on the N-type semiconductor layer 130 and the P-type semiconductor layer 160 to reduce the bonding resistance and facilitate the supply of current.

The electrode 131 of the light emitting cell 100 adjacent to the transparent electrode 151 of the light emitting cell 100 electrically connects the light emitting cells 100 through the connection electrode 170.

A metal bump 180 is formed on the connection electrode 170 on an upper side of the transparent electrode 151 to which the connection electrode 170 is connected. The metal bumps 180 are bonded to a submount substrate to be described later to transfer heat generated in the light emitting cell 100.

The sub-mount substrate includes a substrate 210 having a plurality of N and P regions defined therein, a dielectric film 220 formed on the surface of the substrate 210, and a plurality of electrode layers connecting the adjacent N and P regions to one. 230 and a reflective layer 250.

The substrate 210 may use various films having electrical conductivity and thermal conductivity. If the substrate 210 is a conductive material, an insulating film having a thickness of at least 50 μm may be formed on the substrate 210, or an insulating material in which no current flows may be used in the dielectric film 220, which will be described later.

The dielectric film 220 uses all dielectric materials through which a current flows at 1 μm or less. In addition, the dielectric film 220 may be formed in multiple layers. In the present embodiment, at least one of SiO ₂ , MgO, and SiN may be used as the dielectric film 220.

The electrode layer 230 may use a metal having excellent electrical conductivity.

The reflective layer 250 is formed on the electrode layer 230. The reflective layer 250 is discontinuously formed so as not to be connected to the metal bumps 180.

Hereinafter, the manufacturing process according to the manufacturing method of the light emitting device of the present invention having the above-described structure will be described in detail.

Referring to FIG. 3, the buffer layer 120, the N-type semiconductor layer 130, the active layer 140, and the P-type semiconductor layer 150 are sequentially stacked on the substrate 110. In this case, the above-described materials may be formed through various deposition and growth methods such as organometallic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and hydride vapor phase epitaxy (HVPE). .

Next, referring to FIG. 4, the stacked N-type semiconductor layer 130, the active layer 140, the P-type semiconductor layer 150, and a portion of the buffer layer 120 are removed to separate the light emitting cells 100. . To this end, after forming a mask pattern (not shown) on the P-type semiconductor layer 150, the N-type semiconductor layer 130, the active layer 140, the P-type semiconductor layer 150 in the area exposed by the mask pattern And etching the buffer layer 120 to electrically separate the plurality of light emitting cells 100. As a result, the light emitting cell 100 having a plurality of patterns is formed on the substrate 110. If the buffer layer 120 is an insulating or semi-insulating material, the etching of the buffer layer 120 may be omitted.

Next, a portion of the P-type semiconductor layer 150, a portion of the N-type semiconductor layer 130, and an active layer 140 are removed through an etching process to expose a portion of the N-type semiconductor layer 130. In other words, after forming an etch mask pattern on the P-type semiconductor layer 150, a dry / wet etching process is performed to remove the P-type semiconductor layer 150 and the active layer 140 of the exposed region to form an N-type. A portion of the semiconductor layer 130 is exposed.

Referring to FIG. 5, the anti-reflection layer 160 is applied to the separated light emitting cells 100. Here, the anti-reflection layer 160 applied to the N-type semiconductor layer 130 and the P-type semiconductor layer 150 is removed. Therefore, the anti-reflection layer 160 is formed on the exposed surface of the substrate 110 and the side surface of the light emitting cell 100.

Referring to FIG. 6, the electrode 131 and the transparent electrode 151 are formed on the N-type semiconductor layer 130 and the P-type semiconductor layer 150 from which the anti-reflection layer 160 is removed.

The transparent electrode 151 is formed by applying a photoresist film over the entire structure and then performing a photolithography process using a mask to form a photoresist pattern (not shown) to expose the P-type semiconductor layer 150. Thereafter, the transparent electrode 151 is formed on the entire structure, and the transparent electrode 151 and the photoresist pattern of the remaining regions except for the upper region of the P-type semiconductor layer 150 are removed. The electrode 131 may also be formed using such a lift-off process.

Referring to FIG. 7, the N-type semiconductor layer 130 and the P-type semiconductor layer 150 of the adjacent light emitting cells are electrically connected through an air bridge process or a step-cover process. An electrode 170 is formed.

Referring to the air bridge process, a first photoresist layer pattern exposing a portion of the transparent electrode 151 exposed by an opening of another light emitting cell adjacent to a portion of the light emitting cell electrode 131 is formed. Thereafter, a first metal film is formed on the entire structure to electrically connect the exposed electrode 131 and the transparent electrode 151. Thereafter, a second photosensitive film pattern having the same pattern shape as that of the metal wiring is formed on the entire structure again, and a second metal film is formed thereon. When the first photoresist layer pattern and the second photoresist layer pattern are removed, the metal layers except for the metal interconnection region are removed to form a metal interconnection that is a wire floated in the air to connect the electrode 131 and the transparent electrode 151. .

Referring to a step cover process, which is another method of connecting two electrodes to each other, the entire area is coated with a dielectric material and a photoresist pattern is formed thereon, so that the other light emitting cells adjacent to a part of the electrode 131 of one light emitting cell are formed. A portion of the transparent electrode 151 is developed. After that, the dielectrics in the areas to be connected to each other are etched, and a metal film is coated and connected to remove the photoresist pattern. Then, electrical wiring is formed between two adjacent electrodes.

Next, referring to FIG. 8, the metal bumps 180 are formed on the connection electrode 170 positioned above the transparent electrode 151. The metal bumps 180 are formed by coating a photoresist on the entire structure and then performing a photolithography process using a mask. The metal bumps 180 form a step to have a relatively high height so that the sub-mount substrate and the connection electrode 170 do not contact each other.

Meanwhile, referring to FIG. 9, the submount substrate forms the dielectric film 220 on the entire structure of the substrate 210 in which the N region and the P region are defined. The substrate 210 is formed of a material having a thermal conductivity of 50 W / m.k or more to increase the heat dissipation effect through the metal bumps 180. (Because it is about Fig. 9, it is not considered to fit with Fig. 10.)

Next, an electrode layer 230 is formed on the dielectric layer 220 to connect a pair of N and P regions, respectively. The electrode layer 230 is formed as a metal layer by a screen printing method or by a deposition process using a mask pattern.

Thereafter, the reflective layer 250 is formed on the sub-mount substrate. The reflective layer 250 is formed by applying a photosensitive film on the entire structure and then performing a photolithography process using a mask. In this case, the reflective layer 250 is discontinuously formed so as not to be connected to the metal bumps 180 formed on the connection electrode 170. In addition, the reflective layer 250 is preferably formed of Al or Ag having excellent reflectivity. In other words, the reflective layer 250 is spaced apart from the metal bumps 180 so that the sub-mount substrate is not connected to the metal bumps 180 when the sub-mount substrate is flip-bonded with the metal bumps 180 of the light emitting cell 100. To be positioned.

Thereafter, as illustrated in FIG. 10, the light emitting cell 100 and the sub-mount substrate are bonded to fabricate the light emitting device. The metal bumps 180 are bonded to the submount substrate. In addition, the light emitting device is a blank space between the light emitting cells 100 and the empty space between the light emitting cells 100 and the submount substrate after being flip-bonded with the metal bumps 180 to be transparent material 190 such as an epoxy resin. Can be filled with

The flip bonded light emitting device can be removed using the substrate 110 with a laser lift-off technique, as shown in FIG. At this time, the buffer layer 120 is also removed. As a result, the patterned N-type semiconductor layers 130 on the side opposite to the sub-mount substrate are exposed. By removing the substrate 110, light loss by the substrate 110 may be prevented, thereby improving light extraction efficiency.

In addition, as shown in FIG. 12, the surface of the exposed N-type semiconductor layers 130 is etched to provide a light emitting device having a roughened surface. The etching process may be performed using dry etching using an etching mask or photoelectrochemical (PEC) etching technique. Such a light emitting device can prevent light loss due to total reflection occurring at the interface between the N-type semiconductor layer 130 and air (external) by the roughened surface of the N-type semiconductor layer 130a, so that light extraction efficiency is achieved. Can be improved.

Although not shown in the drawings, the submount substrate may be cut to provide flip bonded light emitting devices in individual chip units. The light emitting device may be manufactured as a package through a packaging process mounted on a lead frame having metal leads.

As described above, according to the present invention, the light emitting device has an advantage that the light emitting efficiency is increased by maximizing the reflectance such that the light emitted from the active layer is reflected toward the substrate by the reflective layer formed on the submount substrate.

In addition, there is an advantage in that the antireflection layer is formed on the substrate to prevent the light emitted toward the substrate from being reflected toward the submount substrate.

In addition, by mounting the above-described light emitting device, there is an advantage that can provide a package with increased luminous efficiency.

Claims (10)

A plurality of light emitting cells including a first semiconductor layer on the substrate, a second semiconductor layer formed on one region of the first semiconductor layer, and an active layer interposed between the first semiconductor layer and the second semiconductor layer; A connecting electrode is electrically connected between the first semiconductor layer of one light emitting cell and the second semiconductor layer of another adjacent light emitting cell. The light emitting cells flip bonded to a submount substrate through metal bumps; And an anti-reflection layer formed on a surface of the substrate and the light emitting cells except for the connection electrode. The method according to claim 1, The anti-reflection layer is light emitting device, characterized in that formed in a thickness of wavelength / (4 × refractive index). The method according to claim 1, The sub-mount substrate is provided with a reflective layer. The method of claim 3, And the reflective layer is discontinuously spaced apart from the metal bumps. The method according to claim 1, The plurality of light emitting cells further comprises a transparent material filling each of the light emitting cells. Forming a plurality of light emitting cells including a first semiconductor layer, a second semiconductor layer formed on one region of the first semiconductor layer, and an active layer interposed between the first semiconductor layer and the second semiconductor layer on a substrate; , Electrically connecting two adjacent light emitting cells, The anti-reflection layer is formed on the light emitting cell except for the surface electrically connected to the light emitting cell. Forming a metal bump in the light emitting cell and flip-bonding it to a submount substrate. The method of claim 6, And separating the substrate from the light emitting cells and exposing the first semiconductor layer. The method of claim 7, And partially etching the exposed surfaces of the first semiconductor layers to form a roughened surface. A lead frame having metal leads; And The package of claim 1, wherein the package includes a light emitting device of claim 1, wherein the light emitting device and the metal leads are electrically connected to each other. The method of claim 9, And a submount substrate interposed between the lead frame and the light emitting element.

Images