JP2005203471A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which prevents plasma damage to a gate oxide film at the time of forming STI by plasma CVD when the gate oxide film is already formed on a semiconductor substrate. <P>SOLUTION: The gate oxide film 12 is formed on the substrate 11, and a gate electrode 13 is formed on the gate oxide film 12. Then, isolation trenches 15 are formed in the substrate 11. An oxide film 16 for device separation is embedded in each isolation trench 15 by plasma CVD under the condition that a substrate temperature is set to 200°C or above and less than 500°C, to form the STI structure. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly, when a gate oxide film (tunnel oxide film) has already been formed on a semiconductor substrate, the formation of STI (shallow trench isolation) without plasma damage. The present invention relates to a method for manufacturing a semiconductor device.

  With reference to FIG. 4, the STI structure of the first prior art will be described.

  A separation groove 42 is formed in the Si substrate (silicon substrate) 41. A SiN (silicon nitride) 43 is formed on the Si substrate 41. Then, a plasma oxide film 44 is buried in the isolation trench 42 to form an STI structure.

  In the first prior art, since the gate oxide film (tunnel oxide film) is not yet formed when the plasma oxide film 44 is buried, plasma damage (destruction of the gate oxide film) to the gate oxide film (tunnel oxide film) is caused. There is no need to worry. Therefore, in order to secure the embedding performance and the film quality, the Si substrate 41 is set at a high temperature of 500 ° C. or higher for embedding.

  In other words, the gate oxide film (tunnel oxide film) is not formed at the time of STI formation. Therefore, the film is formed at a substrate temperature of 500 ° C. or higher in order to ensure embedding performance and film quality without worrying about plasma damage. It was.

  Next, the method for forming the STI structure of the first prior art will be specifically described with reference to FIG.

  First, SiN 62 is formed on the Si substrate 61, the photoresist 63 is patterned (see FIG. 6A), and the isolation groove 64 is formed by etching (see FIG. 6B).

  Next, an HDP oxide film (hydrogen plasma oxide film) 65 is buried in the isolation trench 64 by plasma CVD (see FIG. 6C), and a planarization process is performed (see FIG. 6D). In this way, the STI 66 is formed in the Si substrate 61.

  Thereafter, a gate oxide film 67 and a poly-Si electrode film (polysilicon electrode film) 68 are formed on the Si substrate 61 (see FIG. 6E).

  Finally, the gate oxide film 67 and the poly-Si electrode film 68 are patterned to form a gate electrode 69 on the gate oxide film 67 (see FIG. 6F).

  In the STI structure of the first prior art formed in this way, the gate oxide film 67 and the poly-Si electrode film 68 are formed after the HDP oxide film 65 is buried by plasma CVD. At the time of embedding (when forming the STI 66), it is not necessary to consider plasma damage to the gate oxide film 67.

  However, when the gate oxide film 67 and the poly-Si electrode film 68 are formed after the HDP oxide film 65 is buried (when the STI 66 is formed), the gate oxide film 67 and the poly-SI with respect to the STI 66 due to misalignment during patterning. It is difficult to dry-etch the electrode film 68 vertically.

  In order to solve such a problem of the first prior art, in the second prior art, as shown in FIG. 5, a gate oxide film (tunnel oxide film) is already formed at the time of STI formation ( Patent Document 1).

  Specifically, a separation groove 52 is formed in a Si substrate (silicon substrate) 51. On the Si substrate 51, a gate oxide film 53, poly Si (polysilicon) 54, and SiN (silicon nitride) 55 are formed. Then, a plasma oxide film 56 is buried in the isolation trench 52 to form an STI structure.

JP 2000-101052 A

  However, in the second prior art, since the gate oxide film (tunnel oxide film) has already been formed on the semiconductor substrate, the gate oxide film undergoes lateral plasma damage when the STI is formed by the plasma CVD method. .

  Therefore, the present invention has been made in view of the above-described problems of the prior art, and its purpose is to form an STI by plasma CVD when a gate oxide film has already been formed on a semiconductor substrate. An object of the present invention is to provide a method of manufacturing a semiconductor device in which a gate oxide film is not damaged by plasma.

  In the present invention, a gate oxide film is formed on a substrate, a gate electrode is formed on the gate oxide film, an isolation groove is formed in the substrate, a device isolation oxide film is formed in the isolation groove, and the substrate temperature is 200 ° C. It is characterized by being embedded by a plasma CVD method in a state set at a temperature lower than 500 ° C.

  Here, the device isolation oxide film is embedded in a state where the substrate temperature is set to 200 ° C. or more and less than 500 ° C. in order to avoid plasma damage in the lateral direction with respect to the gate oxide film.

  Preferably, the substrate is a silicon substrate, the gate insulating film is a gate oxide film, and the gate electrode is a polysilicon electrode.

  Preferably, the device isolation oxide film is a hydrogen plasma oxide film.

  The device isolation oxide film forms shallow trench isolation.

  Further, in the present invention, a gate oxide film is formed on the substrate, a gate electrode is formed on the gate oxide film, an isolation groove is formed in the substrate, and an oxide film for device isolation is formed in the isolation groove. It is characterized by being embedded by a plasma CVD method with the flow rate set to 60% or less.

  Here, the filling of the device isolation oxide film with the film forming gas flow rate set to 60% or less is performed in order to avoid plasma damage in the lateral direction with respect to the gate oxide film.

  In the present invention, when a gate oxide film (tunnel oxide film) is already formed at the time of forming the STI, the STI can be formed without generating plasma damage.

  As shown in FIG. 5, when a gate oxide film (tunnel oxide film) or an electrode poly-Si (floating gate) is already formed at the time of STI formation, in order to avoid plasma damage, at the time of STI formation. It is desirable to lower the Si substrate temperature (film formation temperature). Alternatively, it is desirable to reduce the film forming gas flow rate during STI formation.

  As shown in FIG. 2, when the Si substrate temperature (film formation temperature) is 500 ° C. or higher, the yield is significantly reduced. However, if the temperature of the Si substrate is simply lowered to avoid plasma damage, good insulating film characteristics cannot be obtained.

  Therefore, in the present invention, the Si substrate temperature is set to 200 ° C. to 500 ° C. (200 ° C. or more and less than 500 ° C.) in order to achieve both avoidance of plasma damage and insulating film characteristics.

  When the Si substrate temperature, that is, the gate oxide film is exposed to high-density plasma in an active state of 500 ° C. or higher, dielectric breakdown is caused, but if the Si substrate temperature during STI formation by HDP (hydrogen plasma) is 200 ° C. to 500 ° C. Plasma damage can be avoided.

  Also, as shown in FIG. 3, a high yield can be obtained if the film forming gas flow rate is 60% or less. Therefore, in the present invention, the deposition gas flow rate is set to 60% or less in order to avoid plasma damage.

  Next, a method for forming an STI according to the present invention will be described with reference to FIG.

  First, a gate oxide film (tunnel oxide film) 12, a poly Si electrode film (floating gate) 13, and a SiN film 14 are formed on the Si substrate 11 (see FIG. 1A).

  Next, using the patterned SiN film 14 as a mask, the poly SI electrode film 13 and the gate oxide film 12 are simultaneously etched to form an isolation trench 15 for forming STI (see FIG. 1B).

  Next, an HDP oxide film (hydrogen plasma oxide film) 16 is buried in the isolation trench 15 for STI formation by plasma CVD (see FIG. 1C). At this time, in the present invention, the Si substrate temperature is set to 200 ° C. to 500 ° C. (200 ° C. or more and less than 500 ° C.) in order to achieve both avoidance of plasma damage and insulating film characteristics (see FIG. 2). Alternatively, in the present invention, the deposition gas flow rate is set to 60% or less in order to avoid plasma damage (see FIG. 3). Thereby, plasma damage in the lateral direction with respect to the gate oxide film 12 can be avoided.

  Finally, planarization is performed to form the STI 17 (see FIG. 1D). In this way, the STI structure of the present invention is obtained.

  Here, a method of forming a gate oxide film or a poly SI electrode film after etching and filling the STI and etching them (see FIG. 4) cannot be adopted because of a problem of deviation between the STI and the poly SI electrode.

  Further, when the Si substrate temperature is 500 ° C. or higher and exposed to high density plasma, transistor characteristics such as breakdown or deterioration of the gate oxide film (tunnel oxide film) and reliability are greatly lowered.

  In the present invention, as described above, the Si substrate temperature during STI formation is set to 200 ° C. to 500 ° C. (200 ° C. or more and less than 500 ° C.). Alternatively, the film forming gas flow rate during STI formation was set to 60% or less. Accordingly, in the present invention, even when the gate oxide film is already formed at the time of forming the STI, the STI can be formed without generating plasma damage.

It is sectional drawing which shows the formation method of the STI structure which concerns on this invention. It is a figure which shows the yield when changing Si substrate temperature (film-forming temperature). It is a figure which shows the yield when changing a gas flow rate. It is sectional drawing which shows the STI structure of the 1st prior art. It is sectional drawing which shows the 2nd prior art STI structure. It is sectional drawing which shows the formation method of the STI structure concerning a 1st prior art.

Explanation of symbols

11 Si substrate 12 Gate oxide film 13 Poly Si electrode film 14 SiN film 15 Separation groove 16 HDP oxide film 17 STI

Claims (10)

Forming a gate oxide film on the substrate,
Forming a gate electrode on the gate oxide film;
Forming separation grooves in the substrate,
A method for manufacturing a semiconductor device, wherein an oxide film for device isolation is embedded in a separation trench by a plasma CVD method in a state where a substrate temperature is set to a temperature of 200 ° C. or higher and lower than 500 ° C.   Embedding the device isolation oxide film in a state where the substrate temperature is set to 200 ° C. or more and less than 500 ° C. is performed to avoid plasma damage in the lateral direction with respect to the gate oxide film. A method for manufacturing a semiconductor device according to claim 1.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the substrate is a silicon substrate, the gate insulating film is a gate oxide film, and the gate electrode is a polysilicon electrode.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the device isolation oxide film is a hydrogen plasma oxide film.   The method of manufacturing a semiconductor device according to claim 1, wherein the device isolation oxide film forms shallow trench isolation. Forming a gate oxide film on the substrate,
Forming a gate electrode on the gate oxide film;
Forming separation grooves in the substrate,
A method of manufacturing a semiconductor device, wherein an oxide film for device isolation is embedded in a separation groove by a plasma CVD method with a deposition gas flow rate set to 60% or less.   7. The device isolation oxide film is embedded in the state where the film forming gas flow rate is set to 60% or less in order to avoid plasma damage in the lateral direction with respect to the gate oxide film. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.   7. The method of manufacturing a semiconductor device according to claim 6, wherein the substrate is a silicon substrate, the gate insulating film is a gate oxide film, and the gate electrode is a polysilicon electrode.   The method for manufacturing a semiconductor device according to claim 6, wherein the device isolation oxide film is a hydrogen plasma oxide film. The method of manufacturing a semiconductor device according to claim 6, wherein the device isolation oxide film forms shallow trench isolation.

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