JP2005191225A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problems, wherein a carrier is injected into an n-type semiconductor layer, since a Schottky barrier diode, where a p<SP>+</SP>-type semiconductor layer is provided in an n-epitaxial layer, and acts as a p-n junction diode when a prescribed VF is exceeded in a forward voltage, although a low VF can be realized, without considering any IR until now; reverse recovery time (Trr) results from a stored carrier in an off state (at application of a backward voltage); and a switching operating speed is reduced. <P>SOLUTION: In a semiconductor device, an insulating film is provided between an n<SP>-</SP>-type semiconductor layer and the p<SP>+</SP>-type semiconductor layer, thus preventing the carrier from being stored, since a Schottky barrier diode does not operate as the p-n junction diode even if the prescribed VF is exceeded, and preventing reverse recovery time (Trr) from occurring in the off state (the backward voltage is applied). As a result, the switching operation speed can be increased. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device that suppresses deterioration of IR characteristics of a Schottky barrier diode and improves low VF characteristics at high speed.

  FIG. 6 shows a cross-sectional view of conventional Schottky barrier diodes D2 and D3.

  In the Schottky barrier diode D2 of FIG. 6A, an n− type semiconductor layer 32 is stacked on an n + type semiconductor substrate 31, and a guard ring 34 that secures a breakdown voltage when a reverse voltage is applied to the Schottky barrier diode D2 is provided. A Schottky metal layer 36 such as Mo is provided around the surface and forms a Schottky junction with the surface of the semiconductor layer 32.

  An anode electrode 37 is provided on the Schottky metal layer 36, and a cathode electrode 38 is provided on the back surface of the substrate 31. Current flows when a forward voltage is applied, and no current flows due to a Schottky barrier when a reverse voltage is applied.

  The forward voltage VF that is the rising voltage of the Schottky barrier diode D2 and the leakage current IR when the reverse voltage is applied are the work function difference (hereinafter referred to as φBn) obtained at the Schottky junction between the Schottky metal layer 36 and the semiconductor layer 32 surface. To be determined). Generally, when φBn is high, VF is high and IR is in a trade-off relationship.

  Therefore, a Schottky barrier diode D3 having a structure shown in FIG. 6B is also known.

  In the Schottky barrier diode D <b> 3, an n− type semiconductor layer 22 is stacked on an n + type semiconductor substrate 21. The specific resistance of the n − type semiconductor layer 22 is, for example, about 1 Ω · cm for a 40 V system.

  A plurality of p + type regions 23 are provided in the semiconductor layer 22 by diffusing p + type impurities. The interval between the p + -type regions 23 adjacent to each other is a distance at which the depletion layer is pinched off.

  Further, in order to ensure a breakdown voltage when a reverse voltage is applied to the Schottky barrier diode D3, a guard ring 24 that surrounds the outer periphery of all the p + type regions 23 and diffuses p + type impurities is provided. All of the p + -type regions 23 arranged inside the guard ring 24 and the surface of the semiconductor layer 22 are in contact with the Schottky metal layer 26.

  The Schottky metal layer 26 is made of Mo, for example, and forms a Schottky junction with the surface of the semiconductor layer 22. For example, an Al layer or the like is provided as an anode electrode 27 on the Schottky metal layer 26, and a cathode electrode 28 is provided on the back surface of the n + type semiconductor substrate 21.

  In this case, since the Schottky metal layer 26 can be considered as a pseudo p-type region, the Schottky metal layer 26 and the p + -type region 23 can be regarded as continuous p-type regions.

  When a forward voltage is applied to the Schottky barrier diode D3, a current flows. On the other hand, when a reverse voltage is applied, a depletion layer spreads due to a pn junction between the p + type region 23 and the Schottky metal layer 26 and the n − type semiconductor layer 22. At this time, a leak current corresponding to the type of the Schottky metal layer 26 is generated at the interface between the semiconductor layer 22 and the Schottky metal layer 26.

  However, since the p + -type regions 3 are arranged at a separation distance where the depletion layer spreads and pinches off, the leakage current generated at the interface by the depletion layer is suppressed and leakage to the cathode electrode 28 side can be prevented. is there.

  That is, an increase in the leakage current (IR) due to an increase in the reverse voltage (VR) can be suppressed while maintaining a characteristic capable of obtaining a predetermined forward voltage VF (for example, Japanese Patent Application No. 2002-285651). See the description.)

Incidentally, the Schottky barrier diode D3 having a conventional p + -type region 23 as shown in FIG. 7 (A) has a Schottky barrier diode D _SBD and pn junction diode Dpn connected in parallel structure. Here, _DSBD is a Schottky barrier diode in which only the n− type semiconductor layer 22 portion of the D3 Schottky junction region is a Schottky junction region, and _Dpn is a diode of the P + type semiconductor layer 23 portion. is there.

FIG. 7B shows the VF characteristics of each diode. Thus Schottky barrier diode _D forward rising voltage VF1 (about 0.4V) of the _SBD is lower than the pn junction diode _D forward rise voltage of _pn VF2 (about 0.6V).

However, both reversed at a predetermined forward voltage VFX, who pn junction diode D _pn is the forward voltage becomes lower at the same forward current IF.

That is, in the conventional Schottky barrier diode D3, since the two diodes D _SBD and D _pn are connected in parallel, it operates as a Schottky barrier diode D _{SBD in} the region from the rising edge to VFx (arrow a). In the exceeding region, it operates as a pn junction diode _Dpn (arrow b).

  FIG. 8 shows an enlarged view of the p + type region 23 portion of the Schottky barrier diode D3.

  When the Schottky barrier diode D3 is used under the condition of exceeding VFx at the time of ON, for example, under a forward voltage greater than 0.65V, it operates as a pn junction diode as shown in FIG. Carriers (holes) are injected.

  After that, when a reverse voltage is applied to switch to the off state, the leakage current is suppressed by the spread of the depletion layer of the pn junction as shown in FIG. 8B. However, since carriers are accumulated in the semiconductor layer 22 at this time, the depletion layer expands after the carriers accumulated in the semiconductor layer 22 are discharged or recombined. In other words, a time for the carrier outflow or recombination (reverse recovery time: Trr) occurs before turning off.

  By the way, when the same Schottky barrier diode D3 is operated at a forward voltage VF lower than VFx (or when the Schottky barrier diode D2 is used), it does not operate as a pn diode Dpn. That is, when the Schottky barrier diode D3 is operated at a voltage exceeding VFx, there is a problem that the switching operation is delayed as compared with them.

  The present invention has been made in view of such a problem, and includes a one-conductivity-type semiconductor substrate, a one-conductivity-type semiconductor layer provided on the substrate, a plurality of trenches provided in the semiconductor layer, and an insulation covering the inner wall of the trench. A film, a reverse conductivity type semiconductor layer buried in each trench, and a surface of the reverse conductivity type semiconductor layer and the one conductivity type semiconductor layer, and at least forms a Schottky junction with the surface of the one conductivity type semiconductor layer The problem is solved by providing a metal layer.

  The insulating film may prevent carriers from flowing out of the reverse conductivity type semiconductor layer when a voltage is applied between the reverse conductivity type semiconductor layer and the one conductivity type semiconductor layer. .

  The trench is provided shallower than the one-conductivity type semiconductor layer.

  Further, the opposite conductivity type semiconductor layers adjacent to each other are spaced apart by a distance that pinches off a depletion layer extending from the opposite conductivity type semiconductor layer to the one conductivity type semiconductor layer when a voltage in a reverse direction is applied. It is what.

  In addition, the opposite conductivity type semiconductor layers adjacent to each other are spaced apart at equal intervals.

  The insulating film has a thickness of about 500 mm.

  According to the present embodiment, in the junction Schottky barrier diode in which the p + type semiconductor layer is provided in the n − type semiconductor layer, the forward direction is provided by providing the insulating film between the p + type semiconductor layer and the n − type semiconductor layer. It is not operated as a pn junction diode when a voltage is applied. Thereby, carrier injection from the p + type semiconductor region to the n − type semiconductor layer can be prevented. Therefore, the reverse recovery time (Trr) before the depletion layer expands does not occur during the off operation (when reverse voltage is applied). Therefore, the switching operation speed can be improved. This makes it possible to reduce noise and improve set efficiency.

  In addition, it is possible to suppress an increase in leakage current IR accompanying an increase in reverse voltage while maintaining a VF characteristic comparable to that in the past. When a reverse voltage is applied, a leakage current corresponding to the Schottky metal layer is generated at the interface between the epitaxial layer and the Schottky metal layer. According to the structure of the present invention, this leakage current is caused by the depletion layer filling the epitaxial layer. Is suppressed, and leakage to the back electrode side can be prevented.

  Second, a Schottky metal layer having a low VF φBn can be adopted without considering the leakage current IR. Since the pn junction diode does not operate when the forward voltage is applied, the VF increases in a region exceeding VFx where the VF characteristics of the pn junction diode and the Schottky barrier diode are reversed. However, in the present embodiment, since a large leakage current generated at the interface of the Schottky junction can be suppressed by the depletion layer, this can be dealt with by adopting a Schottky metal layer having a low VF φBn.

  Embodiments of the present invention will be described in detail with reference to FIGS.

  FIG. 1 shows a Schottky barrier diode D1 of the present invention. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along the line AA in FIG. In FIG. 1A, the surface Schottky metal layer and the anode electrode are omitted.

  The Schottky barrier diode D1 of the present invention includes a one-conductivity-type semiconductor substrate 1, a one-conductivity-type semiconductor layer 2, a reverse-conductivity-type semiconductor layer 3, a trench 5, an insulating film 6, and a Schottky metal layer 9. Composed.

  The substrate is obtained by stacking an n− type semiconductor layer 2 on an n + type silicon semiconductor substrate 1 by, for example, epitaxial growth, and a plurality of trenches 5 are provided in the n− type semiconductor layer 2 so as to be shallower than the n− type semiconductor layer 2. .

  An insulating film 6 of about 500 mm is provided on the inner wall of each trench 5. As the insulating film, the oxide film 6 is employed in this embodiment. Further, an insulating film such as a nitride film may be used instead of the oxide film 6.

  In the trench 5, polysilicon containing a p + type impurity is buried to provide a p + type semiconductor layer 3. As shown in FIG. 1A, the trench 5 has a regular hexagonal shape with an opening width (diagonal width) of 1 μm, for example, and is separated by a predetermined distance (about 1 μm to 10 μm). This distance is a distance at which the depletion layer is pinched off when a reverse voltage is applied to the Schottky barrier diode D1. Since the p + type semiconductor layers 3 adjacent to each other need to be arranged at equal intervals, the shape is preferably a regular hexagon.

  The guard ring 4 is a p + type high-concentration impurity region provided so as to surround the outer periphery of all the p + type semiconductor layers 3 in order to ensure a breakdown voltage when a reverse voltage is applied to the Schottky barrier diode. The guard ring 4 is provided with a width of about 20 μm in consideration of misalignment of the mask because a part of the guard ring 4 needs to be in contact with the Schottky metal layer 9. The surface of the n − type semiconductor layer 2 inside the guard ring 4 forms a Schottky junction with the Schottky metal layer 9.

  The guard ring 4 is provided equal to or deeper than the p + type semiconductor layer 3 according to the breakdown voltage. In this embodiment, in order to ensure a high breakdown voltage, p + type impurities are provided by ion implantation and diffusion deeper than the p + type semiconductor layer 3 and shallower than the n− type semiconductor layer 2. Further, the guard ring 4 may be a region in which p + type polysilicon is buried in a trench, like the p + type semiconductor layer 3.

  The Schottky metal layer 9 is made of, for example, Mo and is in contact with the n − type semiconductor layer 2 and all the p + type semiconductor layers 3, and forms a Schottky junction with the n − type semiconductor layer 2. For example, an Al layer or the like is provided as an anode electrode 10 on the Schottky metal layer 9, and a cathode electrode 11 is provided on the back surface of the n + type semiconductor substrate 1.

  FIG. 2 shows an enlarged cross-sectional view of the p + type semiconductor layer 3 portion. FIG. 2A shows a state when a forward voltage is applied, and FIG. 2B shows a state when a reverse voltage is applied.

As shown in FIG. 2A, since the oxide film 6 is provided on the inner wall of the trench 5, the p + type semiconductor layer 3 and the n − type semiconductor layer 2 are insulated and separated. Therefore, when a forward voltage lower than VFx is applied, it operates as a Schottky barrier diode D _SBD as in the prior art, and the forward voltage exceeds the forward voltage VFx at which the VF characteristics of the pn junction diode D _pn and the Schottky barrier diode D _SBD are reversed. Even if (see FIG. 7B) is applied, it does not operate as a pn junction diode Dpn. That is, since it continues to operate as a Schottky barrier diode _DSBD , carriers are not injected into the n − type semiconductor layer 2.

  On the other hand, as shown in FIG. 2B, when a reverse voltage is applied to the Schottky barrier diode D1, the p + type semiconductor layer 3 is formed by a pn junction between the p + type semiconductor layer 3 and the Schottky metal layer 9 and the n − type semiconductor layer 2. A depletion layer 50 spreads as shown by a broken line in the n − type semiconductor layer 2 therebetween.

  As described above, the p + -type semiconductor layers 3 are equally spaced at a predetermined interval. The predetermined distance is a distance at which the depletion layer 50 extending from the p + type semiconductor layer 3 is pinched off when a reverse voltage is applied. That is, the n − type semiconductor layer 2 between the p + type semiconductor layers 3 is filled with the depletion layer 50.

  In the Schottky barrier diode D1, a leakage current corresponding to the type of the Schottky metal layer 9 is generated at the interface between the n − type semiconductor layer 2 and the Schottky metal layer 9 when a reverse voltage is applied. However, even if a leakage current is generated at the interface, it is suppressed by the depletion layer 50 and leakage to the cathode electrode 11 side can be prevented.

  That is, it is possible to suppress an increase in leakage current (IR) due to an increase in reverse voltage (VR) while maintaining the same characteristics that can obtain the same forward voltage VF as in the past.

  At this time, in the case where carriers are accumulated in the n − type semiconductor layer 2 as in the conventional Schottky barrier diode D3, the depletion layer 50 is formed after the reverse recovery time (Trr) for carrier outflow or recombination has elapsed. spread. However, since there is no carrier accumulation in this embodiment, there is no need for hole outflow or recombination. Therefore, the reverse recovery time (Trr) does not occur, and the switching operation speed can be improved. Specifically, the switching operation speed, which was several hundred ns in the past, can be improved to several tens ns.

In the region beyond the VFX, but towards the pn junction diode D _pn is low VF, generation of reverse recovery time Trr as already mentioned can not be avoided. On the other hand, in this embodiment, the reverse recovery time Trr does not occur, and the VF characteristics can be improved by appropriately optimizing the Schottky junction area and the Schottky metal layer as follows.

  In the Schottky barrier diode, it is desirable that the junction area between the Schottky metal layer 9 and the semiconductor layer 2 is large because the forward voltage (VF) can be lowered. Since the p + type semiconductor layer 3 becomes an ineffective region when a forward voltage is applied to the Schottky barrier diode, the area occupied by the p + type semiconductor layer 3 may be reduced as much as possible within the range where the depletion layer 50 is pinched off.

  The forward voltage can also be lowered by changing the Schottky metal layer 9 to a metal having a lower φBn (for example, Ti, W, etc.). Although the metal layer with low φBn can reduce the forward voltage (VF), the leakage current (IR) increases. However, in this embodiment, even if the leakage current IR at the interface of the Schottky junction increases, the depletion layer 50.

  Even if the leakage current at the Schottky junction region interface increases, after the depletion layer is pinched off, it does not leak to the cathode electrode side, so that an increase in leakage current as a Schottky barrier diode can be suppressed. That is, it is possible to employ a metal layer having φBn from which a predetermined forward voltage VF can be obtained without considering the leakage current IR.

  Here, the shape of the p + type semiconductor layer 3 is required to be arranged at an equal distance from each other so that the depletion layer 50 spreads out evenly when the reverse voltage is applied so that the semiconductor layer 2 can be filled up. A hexagonal shape is optimal (see FIG. 1A). If there is a portion where the depletion layer is insufficiently spread even at one place, current leaks to the cathode electrode 11 side, and therefore, the p + type semiconductor layer 3 is filled with the spread of the depletion layer 50 when a reverse voltage is applied. As long as a sufficient distance can be secured, the shape of the p + type semiconductor layer 3 is not limited to a regular hexagonal shape.

  Next, an example of the manufacturing method of the Schottky barrier diode of this invention is demonstrated using FIGS. 3-5.

  As shown in FIG. 3A, an oxide film (not shown) is formed on the entire surface by, for example, laminating an n − type semiconductor layer 2 by epitaxial growth or the like on the n + type semiconductor substrate 1. Although not shown, the outermost periphery of the substrate is opened with an oxide film and diffused after n + type impurities are deposited to form an annular ring.

  As shown in FIG. 3B, the guard ring 4 for ensuring a withstand voltage is formed, for example, deeper than the p + type semiconductor layer 3 by ion implantation and diffusion of p + type impurities. The guard ring 4 is formed so as to surround the periphery of the p + type semiconductor layer 3, and the depth thereof is equal to or deeper than that of the p + type semiconductor layer 3 according to the breakdown voltage.

  Since the guard ring 4 also needs to be in contact with the Schottky metal layer, a certain width (for example, about 20 μm) is required in consideration of misalignment of the mask. Since it is a diffusion region, the curvature in the vicinity of the bottom can be relaxed in terms of the cross-sectional shape, electric field concentration in this portion can be suppressed, and it is suitable for high breakdown voltage models.

  Next, in FIG. 3C, a plurality of trenches 5 are formed in the n− semiconductor layer 2 using a mask opened in a hexagonal shape with an opening width (diagonal width) of about 1 μm. The trench is formed shallower than the n − type semiconductor layer 2.

  Next, in FIG. 4A, an insulating film is formed on the inner wall of the trench 5 to a thickness of about 500 mm. The insulating film is an oxide film or a nitride film such as a thermal oxide film or an NSG film, and the oxide film 6 is employed in this embodiment. As a result, the forward operation of the pn junction diode can be prevented.

  In FIG. 4B, polysilicon into which p + type impurities are introduced is buried in all the trenches 5. That is, after depositing non-doped polysilicon on the entire surface, p + type impurities are introduced (or polysilicon on which p + type impurities are introduced is deposited), and then the entire surface is etched back to bury polysilicon in the trench 5. Thus, the p + type semiconductor layer 3 is formed. The p + -type semiconductor layers 3 are arranged equally spaced apart so that the depletion layer is pinched off when a reverse voltage is applied, and the semiconductor layer 2 is completely filled with the depletion layer 50.

  If the p + type semiconductor layer 3 is too deep, the forward voltage VF is high, and if it is too shallow, the leakage current increases. Therefore, the trench 5 and the p + type semiconductor layer 3 are formed to a depth where a desired value can be obtained. .

  In FIG. 4C, the oxide film adhering to the entire surface is removed by the diffusion process so far, and the surfaces of all the p + type semiconductor layer 3 and the n − type semiconductor layer 2 are exposed. In addition, a CVD oxide film is formed, and the guard ring 4 also contacts the Schottky metal layer, so that a part of the CVD oxide film is exposed. That is, the oxide film 8 inside the guard ring 4 including part of the guard ring 4 is removed by etching, and the contact region with the Schottky metal layer 9 is exposed.

  Then, for example, a Schottky metal layer 9 such as Mo is deposited. After patterning into a desired shape covering at least the Schottky junction region, annealing is performed at 500 to 600 ° C. for silicidation. Here, for example, when a predetermined VF cannot be obtained, Ni, Cr, Ti or the like having a low φBn is used instead of Mo.

  Thereafter, an Al layer to be the anode electrode 10 is vapor-deposited on the entire surface, patterned into a desired shape, and a cathode electrode 11 such as Ti / Ni / Au is formed on the back surface to obtain the final structure shown in FIG.

  As shown in FIG. 5, the guard ring 4 may be formed by burying polysilicon in the trench, similarly to the p + -type semiconductor layer 3. That is, a plurality of trenches 15 are formed in the area of the guard ring 4 with a line and space of about 1 μm, for example (FIG. 5A), and polysilicon containing p + type impurities is buried. Thereafter, a small amount of p + -type impurities are diffused from adjacent trenches by heat treatment, so that the impurity regions are integrated, and a guard ring 4 having a width of about 20 μm can be formed (FIG. 5B).

If a predetermined breakdown voltage can be ensured at a depth equivalent to that of the p + type semiconductor layer 3, the guard ring 4 may be formed in the same process as the trench 5 formation and the polysilicon burying of the p + type semiconductor layer 3. In this case, when the trench 15 is covered with the oxide film 6, the p + type semiconductor layer 3 is buried after the oxide film 6 is removed.

1A is a plan view and FIG. 1B is a cross-sectional view for explaining a semiconductor device of the present invention. It is sectional drawing for demonstrating the semiconductor device of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device of this invention. It is sectional drawing for demonstrating the conventional semiconductor device. It is (A) a circuit schematic diagram and (B) a characteristic diagram for explaining a conventional semiconductor device. It is sectional drawing for demonstrating the conventional semiconductor device.

Explanation of symbols

1 n + type semiconductor substrate 2 n− type semiconductor layer 3 p + type semiconductor layer 4 guard ring 5 trench 6 insulating film 8 oxide film 9 Schottky metal layer 10 anode electrode 11 cathode electrode 15 trench 21 n + type semiconductor substrate 22 n− type semiconductor Layer 23 p + type region 26 Schottky metal layer 27 anode electrode 28 cathode electrode 31 n + type semiconductor substrate 32 n− type semiconductor layer 34 p + type region 36 Schottky metal layer 37 anode electrode 38 cathode electrode 50 depletion layer

Claims (6)

One conductivity type semiconductor substrate;
A one-conductivity-type semiconductor layer provided on the substrate;
A plurality of trenches provided in the semiconductor layer;
An insulating film covering the inner wall of the trench;
A reverse conductivity type semiconductor layer embedded in each of the trenches;
A semiconductor device comprising: a metal layer that is provided on surfaces of the reverse conductivity type semiconductor layer and the one conductivity type semiconductor layer and forms at least a surface of the one conductivity type semiconductor layer and a Schottky junction.   2. The carrier according to claim 1, wherein the insulating film prevents carriers from flowing out of the reverse conductivity type semiconductor layer when a voltage is applied between the reverse conductivity type semiconductor layer and the one conductivity type semiconductor layer. Semiconductor device.   The semiconductor device according to claim 1, wherein the trench is provided shallower than the one-conductivity-type semiconductor layer.   The opposite conductivity type semiconductor layers adjacent to each other are spaced apart by a distance that pinches off a depletion layer extending from the opposite conductivity type semiconductor layer to the one conductivity type semiconductor layer when a voltage in a reverse direction is applied. The semiconductor device according to claim 1.   The semiconductor device according to claim 1, wherein the opposite conductivity type semiconductor layers adjacent to each other are spaced apart at equal intervals.   The semiconductor device according to claim 1, wherein the insulating film has a thickness of about 500 mm.

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