JP2005166764A - 多層プリント配線板および多層プリント配線板の製造方法 - Google Patents

多層プリント配線板および多層プリント配線板の製造方法 Download PDF

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Publication number
JP2005166764A
JP2005166764A JP2003400905A JP2003400905A JP2005166764A JP 2005166764 A JP2005166764 A JP 2005166764A JP 2003400905 A JP2003400905 A JP 2003400905A JP 2003400905 A JP2003400905 A JP 2003400905A JP 2005166764 A JP2005166764 A JP 2005166764A
Authority
JP
Japan
Prior art keywords
land
layer
wiring board
core
blind via
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003400905A
Other languages
English (en)
Japanese (ja)
Inventor
Akihiko Happoya
明彦 八甫谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2003400905A priority Critical patent/JP2005166764A/ja
Priority to TW093124206A priority patent/TWI293015B/zh
Priority to KR1020040068426A priority patent/KR100654283B1/ko
Priority to CNB2004100683724A priority patent/CN100428873C/zh
Publication of JP2005166764A publication Critical patent/JP2005166764A/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/421—Blind plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0047—Drilling of holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09454—Inner lands, i.e. lands around via or plated through-hole in internal layer of multilayer PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2003400905A 2003-11-28 2003-11-28 多層プリント配線板および多層プリント配線板の製造方法 Pending JP2005166764A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2003400905A JP2005166764A (ja) 2003-11-28 2003-11-28 多層プリント配線板および多層プリント配線板の製造方法
TW093124206A TWI293015B (en) 2003-11-28 2004-08-12 Multilayered printed wiring board and method for manufacturing the multilayered printed wiring board
KR1020040068426A KR100654283B1 (ko) 2003-11-28 2004-08-30 다층 프린트 배선판 및 다층 프린트 배선판의 제조방법
CNB2004100683724A CN100428873C (zh) 2003-11-28 2004-08-31 多层印刷线路板以及用于制造该多层印刷线路板的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003400905A JP2005166764A (ja) 2003-11-28 2003-11-28 多層プリント配線板および多層プリント配線板の製造方法

Publications (1)

Publication Number Publication Date
JP2005166764A true JP2005166764A (ja) 2005-06-23

Family

ID=34724989

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003400905A Pending JP2005166764A (ja) 2003-11-28 2003-11-28 多層プリント配線板および多層プリント配線板の製造方法

Country Status (4)

Country Link
JP (1) JP2005166764A (zh)
KR (1) KR100654283B1 (zh)
CN (1) CN100428873C (zh)
TW (1) TWI293015B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7767914B2 (en) 2007-11-27 2010-08-03 Kabushiki Kaisha Toshiba Multilayer printed wiring board, method for manufacturing buildup printed wiring board, and electronic apparatus

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4527045B2 (ja) * 2005-11-01 2010-08-18 日本メクトロン株式会社 ケーブル部を有する多層配線基板の製造方法
KR100745520B1 (ko) * 2006-01-20 2007-08-02 삼성전기주식회사 다층 인쇄회로기판 및 그 제조방법
JP5165265B2 (ja) * 2007-03-23 2013-03-21 日本メクトロン株式会社 多層プリント配線板の製造方法
CN101772279B (zh) * 2009-12-21 2013-03-06 艾默生网络能源有限公司 一种带盲孔的pcb板的制造方法
CN105246254B (zh) * 2015-10-14 2018-08-03 江门崇达电路技术有限公司 一种在pcb上制作pth平台的方法
CN114205991B (zh) * 2020-09-18 2024-05-03 重庆方正高密电子有限公司 Pcb板

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3724468B2 (ja) * 1995-04-28 2005-12-07 日本ビクター株式会社 多層印刷配線板
JP3234757B2 (ja) * 1995-12-05 2001-12-04 インターナショナル・ビジネス・マシーンズ・コーポレーション 多層配線基板及びその製造方法
JP2000031644A (ja) * 1998-07-14 2000-01-28 Hitachi Aic Inc 回路基板
KR100346400B1 (ko) * 1999-12-16 2002-08-01 엘지전자주식회사 다층 인쇄회로기판 및 그 제조방법
JP2003179351A (ja) * 2001-12-11 2003-06-27 Cmk Corp ビルドアップ多層配線基板及びその製造方法
JP2003283127A (ja) * 2002-03-22 2003-10-03 Ibiden Co Ltd プリント配線板およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7767914B2 (en) 2007-11-27 2010-08-03 Kabushiki Kaisha Toshiba Multilayer printed wiring board, method for manufacturing buildup printed wiring board, and electronic apparatus

Also Published As

Publication number Publication date
CN100428873C (zh) 2008-10-22
TW200520659A (en) 2005-06-16
TWI293015B (en) 2008-01-21
KR20050052327A (ko) 2005-06-02
KR100654283B1 (ko) 2006-12-08
CN1622740A (zh) 2005-06-01

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