JP2005150658A - Substrate packaging method - Google Patents

Substrate packaging method Download PDF

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JP2005150658A
JP2005150658A JP2003390296A JP2003390296A JP2005150658A JP 2005150658 A JP2005150658 A JP 2005150658A JP 2003390296 A JP2003390296 A JP 2003390296A JP 2003390296 A JP2003390296 A JP 2003390296A JP 2005150658 A JP2005150658 A JP 2005150658A
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mounting
wiring boards
line
wiring
board
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Tatsuo Horiuchi
辰夫 堀内
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Shinko Electric Co Ltd
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Shinko Electric Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To decrease the number of use times of necessaries as to packaging work such as a packaging program, a metal mask for solder printing, etc. to facilitate the management of them, and to clearly define the criteria for arranging multiple wiring substrates onto a framework to efficiently perform the packaging steps. <P>SOLUTION: This is a method to mount onto a framework 1 each of four wiring substrates T<SB>1</SB>to T<SB>4</SB>to perform both-sides packaging of a first surface A and a second surface B, thus simultaneously doing packaging, wherein a packaging operation is carried out while each of the four wiring substrates T<SB>1</SB>to T<SB>4</SB>are line symmetrical to a virtual symmetrical line S<SB>0</SB>, and the two wiring substrates T<SB>1</SB>and T<SB>3</SB>and the two wiring substrates T<SB>2</SB>and T<SB>4</SB>, which are line symmetrical to the virtual symmetrical line S<SB>0</SB>, are alternately reversed, and mounted onto the framework 1 in this fashion. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、表裏両面実装を行う複数枚の基板を枠体に取付けて、複数枚同時に電子部品を実装する方法に関するものである。   The present invention relates to a method of mounting a plurality of substrates to be mounted on a front and back both sides on a frame and mounting a plurality of electronic components simultaneously.

従来、複数枚の配線基板への実装効率を上げるために、同一の複数枚の配線基板を適宜配置して、これらに同時に電子部品を実装する方法がある。そして、個々の配線基板の表裏両面に電子部品を実装するためには、複数の前記基板を取付け可能な枠体を用いて基板組立体を構成し、その片面側又は他方の面側に、配線基板の複数枚全ての表面か、又は裏面かいずれか一方の回路パターンが表れるように、それぞれの配線基板を前記枠体に配置して行っていた。この配置方法では、例えば、複数枚の配線基板の全ての表面が表れるように取付けた基板組立体の片面を上向きにして載置し、個々の配線基板の表面の回路パターンを、前記複数の配線基板の配置に対応させた全体パターンに対応した表面用はんだ印刷メタルマスクでマスキングして、必要部位にはんだを印刷する。こうして基板組立体の片面側に表れる全ての配線基板の表面へのはんだ印刷が完了すると、実装機に所定の電子部品を供給する等の段取りの後に、前記基板組立体を電子部品挿入具に対向させて実装機に載置し、実装用の前記全体パターンを反映した表面用の実装プログラムを読込み、基板組立体の片面側に表れた全ての配線基板の表面に電子部品を実装する工程を実行する。このようにして基板組立体の片面側に配置された複数枚の配線基板の表面への電子部品の実装が終了した後に、該基板組立体を表裏反転させ、前記他方の面側について、片面側と同様の工程を再度繰返して配線基板の裏面用のはんだ印刷及び電子部品実装を行っていた。   Conventionally, in order to increase the mounting efficiency on a plurality of wiring boards, there is a method in which the same plurality of wiring boards are appropriately arranged and electronic components are simultaneously mounted on them. In order to mount electronic components on both the front and back sides of each wiring board, a board assembly is configured using a frame body to which a plurality of boards can be attached, and wiring is provided on one side or the other side. Each of the wiring boards is arranged on the frame so that any one of the circuit patterns on the front surface or the back surface of all the plurality of substrates appears. In this arrangement method, for example, one side of a board assembly mounted so that all the surfaces of a plurality of wiring boards are exposed faces upward, and the circuit pattern on the surface of each wiring board is placed on the plurality of wiring boards. Masking is performed with a surface solder printing metal mask corresponding to the entire pattern corresponding to the arrangement of the substrate, and solder is printed on a necessary portion. When solder printing on the surfaces of all the wiring boards appearing on one side of the board assembly is completed, the board assembly is opposed to the electronic component insertion tool after setting up such as supplying predetermined electronic parts to the mounting machine. And mount it on the mounting machine, read the mounting program for the surface reflecting the entire pattern for mounting, and execute the process of mounting electronic components on the surface of all the wiring boards that appear on one side of the board assembly To do. After mounting electronic components on the surface of the plurality of wiring boards arranged on one side of the board assembly in this way, the board assembly is turned upside down, and the other side is turned on the one side. The same process was repeated again to perform solder printing and electronic component mounting for the back surface of the wiring board.

従って、従来の電子部品両面実装方法によれば、個々の配線基板の表面及び裏面の各回路パターンを反映した基板組立体の片面用及び他方の面用のはんだ印刷用メタルマスクを2種類用意したり、はんだ印刷した後に電子部品を実装するためには、同じく2種類の電子部品実装プログラムを準備する等の必要があった。よって、例えば配線基板の回路パターンの新規設計や設計変更の際には、前記マスクやプログラムに対して2種類分の対応を要するので、これらを管理する負担が大きかった。また、電子部品を実装する工程においては、生産設備の稼働を中断して、電子部品を表面用から裏面用にセットし直したり、基板組立体の片面及び他方の面に対応した個別の実装プログラムを読込んだりする等の段取りが増えるので、生産効率を悪化させていた。   Therefore, according to the conventional electronic component double-side mounting method, two types of solder printing metal masks for one side and the other side of the board assembly reflecting the circuit patterns on the front and back sides of each wiring board are prepared. In order to mount electronic components after solder printing, it is necessary to prepare two types of electronic component mounting programs. Therefore, for example, when a circuit pattern of a wiring board is newly designed or changed, it is necessary to deal with two types of masks and programs, so that the burden of managing these is large. Also, in the process of mounting electronic components, the operation of the production facility is interrupted and the electronic components are reset from the front side to the back side, or individual mounting programs corresponding to one side and the other side of the board assembly As the number of setups such as reading in increased, production efficiency deteriorated.

本発明の課題は、実装プログラムやはんだ印刷用のメタルマスク等の実装作業に係る必要品の使用数を減らしてこれらの管理を容易化したり、複数枚の配線基板の枠体への配置基準を明確に定めて実装工程を効率的に行うことである。   It is an object of the present invention to reduce the number of necessary products related to mounting work such as mounting programs and solder printing metal masks, thereby facilitating the management of these, and to determine the placement criteria for a plurality of wiring boards on the frame. It is to define clearly and perform the mounting process efficiently.

上記の課題を解決するために請求項1の発明は、表裏両面実装を行う複数枚の基板を枠体に取付けて同時に実装する方法であって、偶数枚の基板を仮想対称線に対して線対称であって、しかも前記仮想対称線に対して線対称の関係にある2枚の基板を相互に表裏反転させて配置した状態で前記枠体に取付けて、実装作業を行うことを特徴としている。   In order to solve the above-mentioned problem, the invention of claim 1 is a method of mounting a plurality of substrates to be mounted on both sides of the front and back sides simultaneously to a frame, and mounting the even number of substrates with respect to a virtual symmetry line. Two substrates that are symmetrical and symmetrical with respect to the virtual symmetric line are mounted on the frame body in a state where the two substrates are reversed with respect to each other. .

請求項1の発明によれば、偶数枚の基板を上記のようにして配置すると、仮想対称線の左右に配置された2群の各基板の配置を左右に仮想反転させて、各基板を表裏反転させると、複数(偶数)の基板の各実装パターン(電子部品の実装位置)の組合せである全体パターンは、反転前後において同一となる。その結果、複数枚の基板を同時に実装する場合における表裏両面の「実装パターン」は1つですむので、「はんだ印刷用メタルマスク等の実装に係る必要品が1つですむ」、「実装プログラム等の前記必要品の設計及び設計変更が容易となる」、「反転前後の各実装時における基板の位置合せが同一で行える」等の効果が奏される。   According to the first aspect of the present invention, when an even number of substrates are arranged as described above, the arrangement of each of the two groups of substrates arranged on the left and right of the virtual symmetry line is virtually reversed left and right, and each substrate is turned upside down. When reversed, the overall pattern, which is a combination of the mounting patterns (mounting positions of electronic components) on a plurality of (even) substrates, is the same before and after the reversal. As a result, when mounting multiple boards at the same time, only one “mounting pattern” is required for both the front and back sides. Thus, it is possible to easily design and change the necessary products such as “and the same positioning of the substrate in each mounting before and after reversal”.

請求項2の発明は、請求項1の発明において、前記仮想対称線に対して同一側に配置された複数枚の基板は、全て同一側を向いていることを特徴としている。   The invention of claim 2 is characterized in that, in the invention of claim 1, the plurality of substrates arranged on the same side with respect to the virtual symmetry line all face the same side.

請求項2の発明によれば、請求項1に記載の作用効果に加えて、枠体に基板を取付ける際、及び枠体から基板を取外して保管する際の双方において、基板の表裏を誤ることが少ない。   According to the invention of claim 2, in addition to the operation and effect of claim 1, the front and back of the substrate are mistaken both when attaching the substrate to the frame and when removing the substrate from the frame and storing it. Less is.

本発明によれば、電子部品を実装するのに必要な実装プログラム等のソフトウェアを含む各種の部品数を減らしてこれらの管理を容易化したり、実装作業を効率的に行うことができる。   According to the present invention, it is possible to reduce the number of various components including software such as a mounting program necessary for mounting electronic components, thereby facilitating management of these components, or to efficiently perform mounting operations.

本発明の第1の実施形態について、まず、4枚の配線基板への電子部品両面実装方法について、枠体への個々の配線基板の配置方法を中心に以下に説明する。図中の「X」及び「Y」は、それぞれ同一平面内で互いに直交する横方向及び縦方向を、「Z」は、前記平面と直交する上下方向を示しており、白抜きの「A」及び「B」は、それぞれ配線基板を横方向Xに沿って裏返した状態の表面及び裏面を示している。4枚の各配線基板T(T1〜T4)の表面A及び裏面Bには、それぞれ表面用と裏面用の個別の回路パターンが形成されていて、基板組立体Q1に組立てられた状態で各配線基板T1〜T4の表裏両面A,Bへの電子部品実装を終了して適宜枠体1から取り外された後には、4枚の同一の配線基板Tを得ることができる。以下の説明では、配線基板の符号として「T」を使用し、この「T」に付記する各種の添字は、配置の違いを明確に表現するためのものである。図1の(イ)は、4枚の各配線基板T1〜T4が、横縦に2枚づつ配置された状態の基板組立体Q1を示す平面概略図である。図示されるとおり、基板組立体Q1は、4枚の各配線基板T1〜T4を4つの基板取付空間に1枚づつ取付ける略「田」の字形の枠体1と、該枠体1の外形と略相似小形の方形をなし、後工程で容易に取外し可能に、それぞれほぼ等間隔をおいて横方向X及び縦方向Yに沿って2枚づつ平行に配置された各配線基板T1〜T4とで形成されている。 Regarding the first embodiment of the present invention, first, an electronic component double-sided mounting method on four wiring boards will be described below with a focus on a method for arranging individual wiring boards on a frame. In the figure, “X” and “Y” indicate the horizontal direction and the vertical direction orthogonal to each other in the same plane, and “Z” indicates the vertical direction orthogonal to the plane. And “B” indicate the front surface and the back surface in a state where the wiring board is turned over along the horizontal direction X, respectively. Individual circuit patterns for the front surface and the back surface are formed on the front surface A and the back surface B of each of the four wiring boards T (T 1 to T 4 ), and are assembled in the substrate assembly Q 1. Thus, after the mounting of the electronic components on the front and back surfaces A and B of the respective wiring boards T 1 to T 4 is finished and appropriately removed from the frame 1, four identical wiring boards T can be obtained. In the following description, “T” is used as the reference numeral of the wiring board, and various subscripts added to “T” are for clearly expressing the difference in arrangement. FIG. 1A is a schematic plan view showing a board assembly Q 1 in a state where four wiring boards T 1 to T 4 are arranged two by two horizontally and vertically. As shown in the drawing, the board assembly Q 1 includes a frame body 1 having a substantially “field” shape for mounting four wiring boards T 1 to T 4 one by one in four board mounting spaces, and the frame body 1. Each of the wiring boards T 1 is formed in a rectangular shape substantially similar to the outer shape of the wiring board 2 and arranged in parallel along the horizontal direction X and the vertical direction Y at approximately equal intervals so that they can be easily removed in a subsequent process. ~ T 4 .

次に、基板組立体Q1の構成、即ち枠体1への各配線基板T1〜T4の配置方法について更に詳しく説明する。ここで、横方向Xに沿って配置される2枚の基板をそれぞれ線対称の関係に配置させる対称線を仮想して、これを仮想対称線S0と定める。実施形態の場合は、前記横方向Xと直交する線であって、後述する左側第1群G1(L)に属する各配線基板T1,T3と、右側第2群G1(R)に属する各配線基板T2,T4との横方向Xの配置間隔を縦方向Yに沿って2分する中心線が該対称線S0に該当する。また、図1の(イ)で示される基板組立体Q1の方形面を、上下方向Zに沿って上方側と対面する上面Uと定める。図示されるとおり、前記基板組立体Q1の前記対称線S0より紙面左側には、左側第1群G1(L)に属する2枚の配線基板T1,T3が縦方向Yに沿って紙面の上方と下方とにそれぞれ配置され、紙面右側には、右側第2群G1(R)に属する2枚の配線基板T2,T4が同様に配置され、該左側第1群G1(L)の両配線基板T1,T3は、表面Aを上面Uに、右側第2群G1(R)の両配線基板T2,T4は裏面Bを上面Uに表して枠体1に取付けられている。よって、基板組立体Q1の上面Uには、「紙面左上−右上−左下−右下」の順に、4枚の配線基板T1〜T4の回路パターンを反映した「表面A−裏面B−表面A−裏面B」の組合せを有する全体パターンPaが形成されている。 Next, the configuration of the board assembly Q 1 , that is, the method for arranging the wiring boards T 1 to T 4 on the frame 1 will be described in more detail. Here, a symmetric line that places the two substrates arranged along the horizontal direction X in a line-symmetrical relationship is assumed to be a virtual symmetric line S 0 . In the case of the embodiment, the wiring boards T 1 and T 3 that are lines perpendicular to the lateral direction X and belong to the left first group G 1 (L) described later, and the right second group G 1 (R). A center line that bisects the arrangement interval in the horizontal direction X with each of the wiring boards T 2 and T 4 belonging to 1 corresponds to the symmetry line S 0 . Further, the rectangular surface of the substrate assembly Q 1 shown in FIG. 1A is defined as the upper surface U facing the upper side along the vertical direction Z. As shown in the drawing, two wiring boards T 1 and T 3 belonging to the left first group G 1 (L) are arranged along the vertical direction Y on the left side of the plane of symmetry of the board assembly Q 1 from the symmetry line S 0. The two wiring boards T 2 and T 4 belonging to the right second group G 1 (R) are similarly arranged on the right side and the right side of the drawing, and the left first group G Both ( 1 ) (L) wiring boards T 1 and T 3 are framed with the front surface A on the upper surface U and the right second group G 1 (R) both wiring boards T 2 and T 4 with the back surface B on the upper surface U. It is attached to the body 1. Therefore, on the upper surface U of the board assembly Q 1 , “front surface A—back surface B— reflecting the circuit patterns of the four wiring boards T 1 to T 4 in the order of“ upper left-upper right-lower left-lower right ”. An overall pattern Pa having a combination of “front surface A−back surface B” is formed.

そして、左側第1群G1(L)と右側第2群G1(R)との配置が左右反転するように、上記した基板組立体Q1を仮想対称線S0を中心にして180°回転させると〔図1(ロ)参照〕、図1の(ハ)に示されるように、基板組立体Q1の下面Dが上下方向Zの上方側に対面して表裏反転される。ここで、白抜きの破線の「B」と「A」は、それぞれ反転前の上面Uに表れていた白抜き実線の「A」と「B」と対をなす各配線基板の裏面と表面とを示している。即ち、表裏反転した結果、前記対称線S0より紙面左側には、前記右側第2群G1(R)に属する2枚の配線基板T2,T4が表面Aを上方に対面させて配置され、紙面右側には、前記左側第1群G1(L)に属する2枚の配線基板T1,T3が裏面Bを上方に対面させて同様に配置されるので、下面Dには、前記上面Uの全体パターンPaと同一の全体パターンPaが形成される。なお、図1では、基板組立体Q1の表裏反転前後の各配線基板Tの表面A及び裏面Bの配置を解易く図示するために、仮想対称線S0を回転軸として仮想したが、実際の作業工程で回転軸の所在を問う必要はない。要は、前記左側第1及び右側第2の各群G1(L),G1(R)の各基板の配置が左右に反転するように、基板組立体Q1が表裏反転されれば、反転前後の両全体パターンPaは同一となるので問題ない。 Then, the substrate assembly Q 1 described above is 180 ° about the virtual symmetry line S 0 so that the arrangement of the left first group G 1 (L) and the right second group G 1 (R) is horizontally reversed. rotation [see FIG. 1 (b)], as shown in (c) of FIG. 1, the lower surface of the substrate, D assembly Q 1 is are reversed to face the upper side in the vertical direction Z. Here, the white broken lines “B” and “A” are the back and front surfaces of the respective wiring boards that are paired with the solid white lines “A” and “B” appearing on the upper surface U before inversion. Is shown. That is, as a result of reversing the front and back, two wiring boards T 2 and T 4 belonging to the second group G 1 (R) on the right side of the plane of symmetry S 0 are arranged with the surface A facing upward. On the right side of the paper, the two wiring boards T 1 and T 3 belonging to the left first group G 1 (L) are arranged in the same manner with the back surface B facing upward. An overall pattern Pa identical to the overall pattern Pa on the upper surface U is formed. In FIG. 1, the virtual symmetry line S 0 is assumed as the rotation axis in order to illustrate the arrangement of the front surface A and the rear surface B of each wiring board T before and after the front and back inversion of the board assembly Q 1 in an easy-to-understand manner. There is no need to ask where the rotary shaft is in the work process. In short, if the board assembly Q 1 is turned upside down so that the arrangement of the boards in the left first and right second groups G 1 (L), G 1 (R) is reversed left and right, There is no problem because the entire pattern Pa before and after inversion is the same.

よって、従来方法通りに、前記基板組立体Q1の上面Uに表れる各配線基板T1〜T4〔図1の(イ)参照〕への電子部品実装を行った後に、引き続いて、図1の(ハ)に示される基板組立体Q1の下面D側に電子部品を実装するためには、まず、上述したように基板組立体Q1を表裏反転して前記上面Uの場合と同様に下面Dを上方に対面させてこれを作業台等に載置し、前記上面Uの全体パターンPaが反映されたメタルマスク(図示せず)で下面Dをマスクしてはんだを印刷する。下面Dの全体パターンPaは、上面Uと同じ「表面A−裏面B−表面A−裏面B」順の組合せを有しており、同一のメタルマスクを使用可能である。そして、はんだを印刷した後に、基板組立体Q1の下面D側に表れる各配線基板T1〜T4のはんだ印刷位置に電子部品を実装する際には、実装機への電子部品セット状態、及び冶具で定められた基板組立体Q1の載置位置を上面Uの場合と変更せずにそのまま維持して、しかも上面Uの側と同一の実装プログラムを読込んで行えるので、段取りに係る工数が削減される。また、前記マスクやプログラムのような電子部品実装に係る必要品の数をも減らせるので、これらを管理する負担が軽減され、回路パターンや電子部品変更等の設計変更への対応も容易になる。また、基板組立体Q1は、仮想対称線S0より左側に配置される左側第1群G1(L)に属する両配線基板T1,T3が、表面A又は裏面Bのいずれか一方の同一面を、上面U又は下面Dに表すように枠体1に取付けられているので、枠体に基板を取付ける際や、電子部品実装後に枠体から基板を取外して保管する際の双方において、各配線基板Tの表裏を誤ることが少なくなっている。 Therefore, after mounting electronic components on each of the wiring boards T 1 to T 4 [see FIG. 1 (a)] appearing on the upper surface U of the board assembly Q 1 as in the conventional method, In order to mount an electronic component on the lower surface D side of the board assembly Q 1 shown in (c), first, as described above, the board assembly Q 1 is turned upside down as in the case of the upper face U. The lower surface D is faced upward and placed on a work table or the like, and solder is printed by masking the lower surface D with a metal mask (not shown) reflecting the entire pattern Pa of the upper surface U. The entire pattern Pa on the lower surface D has the same combination as the upper surface U in the order of “front surface A−back surface B−front surface A−back surface B”, and the same metal mask can be used. Then, after printing the solder when mounting the electronic components on the solder printing position of each wiring board T 1 through T 4 appearing on the lower surface D of the substrate assembly Q 1 is, the electronic components set state to the mounting machine, Since the mounting position of the board assembly Q 1 determined by the jig is maintained as it is on the upper surface U, and the same mounting program as that on the upper surface U can be read and the man-hours related to the setup can be performed. Is reduced. In addition, since the number of necessary parts related to electronic component mounting such as the mask and the program can be reduced, the burden of managing these is reduced, and it becomes easy to cope with design changes such as circuit pattern and electronic component changes. . Further, in the board assembly Q 1 , both the wiring boards T 1 and T 3 belonging to the left first group G 1 (L) arranged on the left side of the virtual symmetry line S 0 are either the front surface A or the back surface B. Since the same surface is attached to the frame 1 so as to represent the upper surface U or the lower surface D, both when mounting the substrate on the frame and when removing and storing the substrate from the frame after mounting the electronic component In this case, the front and back of each wiring board T is less likely to be mistaken.

上述した作用効果を奏する配線基板の配置方法について、上記した配線基板Tを横方向Xに沿って直線状に配置させる場合を例示して総括する。図2の(イ)と(ロ)は、前記仮想対称線S0の左右にそれぞれ配置される配線基板Tが1枚の場合の横方向Xに沿った1行の回路パターンの配置を示す説明図である。本発明を実施するためには、1行をなす合計2枚の配線基板T1(L),T1(R)が、それぞれ仮想対称線S0に対して左右に線対称に配置され、しかも相互に表裏反転させて配置されていなければならない。そして、仮想対称線S0の左側の1枚の配線基板T1(L)の回路パターンの表れ方の「場合の数」は、表面Aか裏面Bかいずれか一方の2通りであって、仮想対称線S0の右側の配線基板T1(R)は、左側に表れる回路パターンに対応して、これを表裏反転させた面を表して配置されればよい。図2に示されるように、合計2枚の配線基板T1(L),T1(R)の個々の回路パターンによって形成される1行パターンには、2通りの1行パターンP11,P12がある。 The above-described wiring board placement method that provides the above-described effects will be summarized by exemplifying a case where the wiring board T described above is arranged linearly along the lateral direction X. FIGS. 2A and 2B show the arrangement of circuit patterns in one row along the horizontal direction X when the number of wiring boards T arranged on the left and right of the virtual symmetry line S 0 is one. FIG. In order to implement the present invention, a total of two wiring boards T 1 (L) and T 1 (R) forming one row are arranged symmetrically to the left and right with respect to the virtual symmetry line S 0 . They must be placed upside down with respect to each other. And, the “number of cases” of the appearance of the circuit pattern of one wiring board T 1 (L) on the left side of the virtual symmetry line S 0 is either one of the front surface A and the back surface B, and The wiring board T 1 (R) on the right side of the virtual symmetric line S 0 may be arranged so as to represent a surface obtained by inverting the front and back corresponding to the circuit pattern appearing on the left side. As shown in FIG. 2, there are two one-row patterns P 11 , P 11 in one row pattern formed by the individual circuit patterns of a total of two wiring boards T 1 (L), T 1 (R). There are twelve .

そして、図3の(イ)〜(ニ)は、仮想対称線S0の左側及び右側にそれぞれ配置される配線基板Tが2枚の場合について示した図2と同様の説明図である。仮想対称線S0の左側及び右側には、それぞれ2枚の配線基板T2(L),T1(L)と、配線基板T1(R),T2(R)との合計4枚の配線基板Tが1行をなして配置されている。この場合には、仮想対称線S0間近の左側と右側とに配置される2枚1組の配線基板T1(L),T1(R)と、それらの外側に配置される他の2枚1組の配線基板T2(L),T2(R)とが、1組内でそれぞれ線対称に配置され、しかも相互に表裏反転させて配置されなければならない。そして、仮想対称線S0の間近の左側の配線基板T1(L)と、その外側に配置される配線基板T2(L)との個々の回路パターンの表れ方の「場合の数」は、合計4(=22)通りである。従って、仮想対称線S0の右側の両配線基板T1(R),T2(R)は、左側に表れる4通りの回路パターンに対応して、これらを表裏反転させた面を表して、上記したように線対称に配置されればよい。図3に、1行をなす合計4枚の配線基板T2(L)〜T2(R)の個々の回路パターンによって形成される4通りの1行パターンP21〜P24を示す。また、図4に示されるとおり、仮想対称線S0の左右に配置される配線基板Tが、それぞれ左側の3枚の配線基板T3(L)〜T1(L)と、右側の3枚の配線基板T1(R)〜T3(R)との合計6枚で1行をなして配置される場合も同様であって、2枚1組で線対称に配置された前記配線基板T1(L),T1(R)と、それらの外側の1組の配線基板T2(L),T2(R)と、更にその外側に配置された1組の配線基板T3(L),T3(R)とが、同じ1組内で互いに表裏反転して配置されていればよい。この時の仮想対称線S0の左側に配置される3枚の配線基板T3(L)〜T1(L)の回路パターンの表れ方の「場合の数」は、合計8(=23)通りである。図4の(イ)〜(チ)に、1行をなす合計6枚の配線基板T3(L)〜T3(R)の個々の回路パターンによって形成される8通りの1行パターンP31〜P38を示す。 Then, the (a) to 3 (d) is an explanatory view similar to FIG. 2 shows the case wiring board T which are respectively disposed on left and right virtual symmetry line S 0 is two. On the left and right sides of the virtual symmetry line S 0 , a total of four wiring boards T 2 (L) and T 1 (L) and four wiring boards T 1 (R) and T 2 (R), respectively. The wiring board T is arranged in one row. In this case, a set of two wiring boards T 1 (L) and T 1 (R) arranged on the left and right sides near the virtual symmetric line S 0 and the other two arranged outside them. A set of wiring boards T 2 (L) and T 2 (R) must be arranged symmetrically with respect to each other within the set, and arranged so as to be reversed from each other. And, the “number of cases” of the appearance of individual circuit patterns of the left wiring board T 1 (L) near the virtual symmetric line S 0 and the wiring board T 2 (L) arranged outside the virtual wiring line T 0 is The total is 4 (= 2 2 ). Accordingly, the two wiring boards T 1 (R) and T 2 (R) on the right side of the virtual symmetric line S 0 represent the surfaces obtained by reversing the front and back in correspondence with the four circuit patterns appearing on the left side. What is necessary is just to arrange | position symmetrically as mentioned above. FIG. 3 shows four one-row patterns P 21 to P 24 formed by individual circuit patterns of a total of four wiring boards T 2 (L) to T 2 (R) forming one row. Further, as shown in FIG. 4, the wiring boards T arranged on the left and right sides of the virtual symmetry line S 0 are respectively the left three wiring boards T 3 (L) to T 1 (L) and the right three boards. The same applies to the case where a total of six wiring boards T 1 (R) to T 3 (R) are arranged in one row, and the wiring boards T are arranged symmetrically in pairs. 1 (L), T 1 (R), a set of wiring boards T 2 (L), T 2 (R) outside them, and a set of wiring boards T 3 (L ), T 3 (R) are only required to be reversed in the same set. At this time, the “number of cases” in the appearance of the circuit patterns of the three wiring boards T 3 (L) to T 1 (L) arranged on the left side of the virtual symmetry line S 0 is a total of 8 (= 2 3 ) That's right. 4A to 4H, eight one-row patterns P 31 formed by individual circuit patterns of a total of six wiring boards T 3 (L) to T 3 (R) forming one row. shows the ~P 38.

そして、基板組立体を構成するために、上述した1行パターンを元にした全体パターンを形成すべく偶数枚の配線基板Tを配置するには、1つの仮想対称線S0を基準にして、前記1行パターンを任意に組み合わせて縦方向Yに沿って配置すればよい。図5の(イ)と(ロ)に、第2及び第3の各実施形態の基板組立体Q2,Q3の図1の(イ)に対応する平面概略図を示す。第2及び第3の各実施形態の基板組立体Q2,Q3は、第1実施形態と同じく、それぞれ横方向Xに沿って配置される2枚の配線基板Tで1行が形成される組立体の実施形態である。第1実施形態の基板組立体Q1が、同一の2つの前記1行パターンP11が縦方向Yに沿って配置された組立体であるのに対して、第2実施形態の基板組立体Q2では、該1行パターンP11の紙面下方には、同一の仮想対称線S0を基準にして、別の1行パターンP12が配置されており、両1行パターンP11,P12が縦方向Yに沿って配置された全体パターンPbが形成されている。そして、前記左側第1群G2(L)と右側第2群G2(R)との各配線基板Tの配置が左右反転するように、該基板組立体Q2を表裏反転させると、反転前の全体パターンPbと同一の全体パターンPbが反転後にも形成され、第1実施形態と同様に効率的に電子部品の両面実装を行える。 Then, in order to arrange the even number of wiring boards T so as to form an overall pattern based on the above-described one-row pattern in order to configure the board assembly, one virtual symmetric line S 0 is used as a reference. What is necessary is just to arrange | position along the vertical direction Y combining the said 1 line pattern arbitrarily. FIGS. 5A and 5B are schematic plan views corresponding to FIG. 1A of the board assemblies Q 2 and Q 3 of the second and third embodiments. In the substrate assemblies Q 2 and Q 3 of the second and third embodiments, one row is formed by two wiring boards T arranged along the lateral direction X, respectively, as in the first embodiment. 2 is an embodiment of an assembly. The substrate assembly Q 1 of the first embodiment is an assembly in which the same two one-line patterns P 11 are arranged along the vertical direction Y, whereas the substrate assembly Q of the second embodiment. in 2, the paper below the first line pattern P 11, the same virtual symmetry line S 0 as a reference, and another one-line pattern P 12 is disposed, both a line pattern P 11, P 12 is An overall pattern Pb arranged along the vertical direction Y is formed. When the board assembly Q 2 is turned upside down so that the arrangement of the wiring boards T in the left first group G 2 (L) and the right second group G 2 (R) is reversed left and right, The same overall pattern Pb as the previous overall pattern Pb is formed even after inversion, and electronic parts can be efficiently mounted on both sides as in the first embodiment.

第3実施形態の基板組立体Q3は、合計3行の1行パターンP11,P12,P11が、同様に縦方向Yに沿って順に配置され、6個の回路パターンよりなる全体パターンPcが形成されるように、これらを構成する合計6枚の配線基板T1〜T6を同様に枠体2に取付けた組立体である。前記1行パターンを3行組合せた場合にも、他の実施形態と同等の作用効果が奏されることは、図示より明らかであって、4行以上の組合せについても同様である。また、横方向Xに沿って直線状に配置された2枚の配線基板Tで、1行パターンが構成される場合について説明したが、1行の基板の枚数は、任意の偶数枚について同様に実施可能である。 In the board assembly Q 3 of the third embodiment, a total of three line patterns P 11 , P 12 , P 11 are similarly arranged in order along the vertical direction Y, and an overall pattern composed of six circuit patterns. This is an assembly in which a total of six wiring boards T 1 to T 6 constituting these are similarly attached to the frame body 2 so that Pc is formed. It is clear from the drawing that the same effect as that of the other embodiments can be obtained when the above-mentioned one-line pattern is combined in three lines, and the same applies to combinations of four or more lines. Moreover, although the case where one line pattern was comprised with the two wiring boards T arrange | positioned linearly along the horizontal direction X was demonstrated, the number of the board | substrates of one line is the same about arbitrary even numbers of sheets. It can be implemented.

上述した各実施形態では、方形状の配線基板Tが直線状に配置される例について説明したが、本発明は、必ずしもこの形状に限定されない。2枚1組の配線基板が、仮想対称線S0に対して左右線対称に表裏反転して配置されれば、不定な形状の基板でも実施可能である。 In each of the above-described embodiments, the example in which the rectangular wiring board T is arranged in a straight line has been described. However, the present invention is not necessarily limited to this shape. If a set of two wiring boards is arranged so as to be reversed in the left-right direction symmetrically with respect to the virtual symmetry line S 0 , a board having an indefinite shape can be implemented.

(イ)は、4枚の各配線基板T1〜T4が、横縦に2枚づつ配置された状態の基板組立体Q1を示す平面概略図であって、(ロ)は、該基板組立体Q1を仮想対称線S0を中心にして180°左右反転させる状態を示す図であって、(ハ)は、該基板組立体Q1の下面Dが上下方向Zの上方側に対面して表裏反転された状態を示す平面概略図である。(A) is a schematic plan view showing a board assembly Q 1 in a state where four wiring boards T 1 to T 4 are arranged two by two horizontally and vertically, and (B) shows the boards. a diagram showing a state to to 180 ° mirror-reversed about a the assembly Q 1 imaginary symmetry line S 0, (c) is a bottom D of the substrate assembly Q 1 is facing upward in the vertical direction Z It is a schematic plan view showing a state where the front and back are reversed. (イ)と(ロ)は、仮想対称線S0の左右にそれぞれ配置される配線基板Tが1枚の場合の横方向Xに沿った1行の回路パターンの配置を示す説明図である。(A) and (B) are explanatory diagrams showing the arrangement of circuit patterns in one row along the horizontal direction X when there is one wiring board T arranged on the left and right sides of the virtual symmetry line S 0 . (イ)〜(ニ)は、仮想対称線S0の左右にそれぞれ配置される配線基板Tが2枚の場合の図2と同様の説明図である。(A) to (d) is an explanatory view similar to FIG. 2 when the wiring board T arranged respectively two on the left and right virtual symmetry line S 0. (イ)〜(チ)は、仮想対称線S0の左右にそれぞれ配置される配線基板Tが3枚の場合の図2と同様の説明図である。(A) to (h) are explanatory views similar to FIG. 2 when the wiring board T which are arranged on left and right virtual symmetry line S 0 is three. (イ)と(ロ)は、第2及び第3の各実施形態の基板組立体Q2,Q3の図1の(イ)に対応する平面概略図を示す。FIGS. 2A and 2B are schematic plan views corresponding to FIG. 1A of the substrate assemblies Q 2 and Q 3 of the second and third embodiments.

符号の説明Explanation of symbols

1〜Q3:基板組立体
T,T1〜T6:配線基板
0:仮想対称線
1,2:枠体
Q 1 to Q 3 : Board assembly T, T 1 to T 6 : Wiring board
S 0 : Virtual symmetry line 1, 2: Frame

Claims (2)

表裏両面実装を行う複数枚の基板を枠体に取付けて同時に実装する方法であって、
偶数枚の基板を仮想対称線に対して線対称であって、しかも前記仮想対称線に対して線対称の関係にある2枚の基板を相互に表裏反転させて配置した状態で前記枠体に取付けて、実装作業を行うことを特徴とする基板の実装方法。
A method of mounting a plurality of substrates to be mounted on both sides of the front and back sides and mounting them simultaneously on a frame,
An even number of substrates are line-symmetric with respect to the virtual symmetry line and the two substrates having a line-symmetrical relationship with respect to the virtual symmetry line are arranged in the frame body in a state where the substrates are reversed with respect to each other. A method of mounting a board, characterized by mounting and performing a mounting operation.
前記仮想対称線に対して同一側に配置された複数枚の基板は、全て同一側を向いていることを特徴とする請求項1に記載の基板の実装方法。
The substrate mounting method according to claim 1, wherein all of the plurality of substrates arranged on the same side with respect to the virtual symmetry line face the same side.
JP2003390296A 2003-11-20 2003-11-20 Substrate packaging method Pending JP2005150658A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003390296A JP2005150658A (en) 2003-11-20 2003-11-20 Substrate packaging method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003390296A JP2005150658A (en) 2003-11-20 2003-11-20 Substrate packaging method

Publications (1)

Publication Number Publication Date
JP2005150658A true JP2005150658A (en) 2005-06-09

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003390296A Pending JP2005150658A (en) 2003-11-20 2003-11-20 Substrate packaging method

Country Status (1)

Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7153195B2 (en) 2018-12-26 2022-10-14 トヨタ紡織株式会社 Mother board, mother board manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7153195B2 (en) 2018-12-26 2022-10-14 トヨタ紡織株式会社 Mother board, mother board manufacturing method

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