JPH0952227A - Cutting method - Google Patents

Cutting method

Info

Publication number
JPH0952227A
JPH0952227A JP22455495A JP22455495A JPH0952227A JP H0952227 A JPH0952227 A JP H0952227A JP 22455495 A JP22455495 A JP 22455495A JP 22455495 A JP22455495 A JP 22455495A JP H0952227 A JPH0952227 A JP H0952227A
Authority
JP
Japan
Prior art keywords
cutting
pattern
ceramic substrate
cpu
cut
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22455495A
Other languages
Japanese (ja)
Other versions
JP3666068B2 (en
Inventor
Masahiro Yoshii
政弘 吉井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Disco Corp
Original Assignee
Disco Abrasive Systems Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Disco Abrasive Systems Ltd filed Critical Disco Abrasive Systems Ltd
Priority to JP22455495A priority Critical patent/JP3666068B2/en
Publication of JPH0952227A publication Critical patent/JPH0952227A/en
Application granted granted Critical
Publication of JP3666068B2 publication Critical patent/JP3666068B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a method for so cutting a ceramic board that a pattern of a reference of a cutting line is deviated due to sintering strain as to divide it into individual chips without cutting a chip. SOLUTION: The method for cutting a plurality of piezoelectric elements formed on a ceramic board S into individual chips P comprises the steps of recording alignment information in a CPU by aligning a pattern as the reference of all cutting lines L, and calling and referring the information in the case of cutting the lines to be cut.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、特にセラミックス
基板に形成された複数の圧電素子等を個々のチップに分
割する切削方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cutting method for dividing a plurality of piezoelectric elements or the like formed on a ceramic substrate into individual chips.

【0002】[0002]

【従来の技術】セラミックス基板は焼結によって歪みが
生じてしまうため、焼結前に付けておいた切削ラインの
基準となるパターン(目印)の位置がずれてしまい、シ
リコン基板のように1本の切削ラインをアライメントし
てインデックス送りで切削を遂行する方法は馴染まな
い。前記パターンは通常セラミックス基板の対向辺に対
設されるが、焼結によるパターンの位置ずれが2mm前
後の場合には許容範囲内と見做し、ずれの真ん中を切削
ラインと定めて切削し、且つこの切削ラインを基準線と
して平行にインデックス送り(ピッチ送り)してブライ
ンド切削をしていた。
2. Description of the Related Art Since a ceramic substrate is distorted due to sintering, the position of a pattern (mark), which is a reference of a cutting line attached before sintering, is displaced, and one substrate like a silicon substrate is displaced. The method of aligning the cutting line and performing cutting by index feed is not familiar. The pattern is usually provided on the opposite side of the ceramic substrate, but when the positional deviation of the pattern due to sintering is about 2 mm, it is considered to be within the allowable range, and the center of the deviation is set as a cutting line to perform cutting. In addition, blind cutting was performed by index feed (pitch feed) in parallel with this cutting line as a reference line.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、上記従
来の切削方法によれば各パターン間のずれが全て許容範
囲内にあるとは限らず、許容範囲を超えて位置ずれが生
じている場合には、圧電素子等のチップを切断して損傷
させるという問題があった。本発明は、このような従来
の問題を解決するためになされ、全ての切削ラインの基
準となるパターンのアライメントを遂行し、その結果を
座標値でCPUにアライメント情報として記憶させ、切
削する度毎にCPUからの当該アライメント情報を呼び
出し、これに基づいて精密位置合わせを行いながら切削
を遂行する切削方法を提供することを目的とする。
However, according to the above-mentioned conventional cutting method, the deviation between the respective patterns is not always within the allowable range, and when the positional deviation occurs beyond the allowable range. However, there is a problem that a chip such as a piezoelectric element is cut and damaged. The present invention has been made to solve such a conventional problem, performs alignment of a pattern serving as a reference for all cutting lines, stores the result as coordinate information in the CPU as coordinate information, and every time cutting is performed. It is an object of the present invention to provide a cutting method in which the CPU executes the alignment information from the CPU and performs cutting while performing precision alignment based on the information.

【0004】[0004]

【課題を解決するための手段】前記課題を技術的に解決
するための手段として、本発明は、セラミックス基板に
形成された複数の圧電素子等を個々のチップに分割する
切削方法において、全ての切削ラインの基準となるパタ
ーンをアライメントしてそのアライメント情報をCPU
に記録する工程と、切削すべきラインを切削する際に該
当するアライメント情報を呼び出して参照する工程とを
少なくとも含む切削方法を要旨とする。
As a means for technically solving the above-mentioned problems, the present invention provides a cutting method for dividing a plurality of piezoelectric elements or the like formed on a ceramic substrate into individual chips. The reference pattern of the cutting line is aligned and the alignment information is stored in the CPU.
The gist of the cutting method is to include at least a step of recording and a step of calling and referring to corresponding alignment information when cutting a line to be cut.

【0005】[0005]

【発明の実施の形態】以下、本発明の実施の形態を添付
図面に基づいて詳説する。図2は切削装置の一例を示す
もので、チャックテーブルTの上に例えば図3に示すよ
うな長方形のセラミックス基板Sを載せて吸引保持さ
せ、又はワックスダウンで保持させ、チャックテーブル
Tを移動してアライメント手段Aに位置付け、アライメ
ント後に回転ブレードBを有する切削手段Cにてセラミ
ックス基板Sを切削する。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 2 shows an example of a cutting device. For example, a rectangular ceramic substrate S as shown in FIG. 3 is placed on a chuck table T and suction-held, or wax-down is held to move the chuck table T. And the ceramic substrate S is cut by the cutting means C having the rotary blade B after the alignment.

【0006】前記セラミックス基板Sは、図1に示すよ
うに圧電素子等のチップPが一定のピッチで縦横に複数
個並設され、各チップPを個々に分割するための切削ラ
インL(実際には設けられていない)の基準となるパタ
ーン(目印)1、2……、1′、2′……、a、b…
…、a′、b′……がセラミックス基板の対向辺にそれ
ぞれ対設されている。図示の例ではパターンは1〜4、
a〜i迄であるが数はこれに限定されるわけではない。
As shown in FIG. 1, the ceramic substrate S has a plurality of chips P such as piezoelectric elements arranged vertically and horizontally at a fixed pitch, and a cutting line L (actually, for dividing each chip P individually). Pattern (mark) 1, 2 ... 1 ', 2' ..., a, b ...
, A ', b' ... are respectively provided on opposite sides of the ceramic substrate. In the illustrated example, the patterns are 1 to 4,
The number is from a to i, but the number is not limited to this.

【0007】前記パターンはセラミックス基板Sの焼結
前に正確な位置に付けられるが、焼結後はセラミックス
基板Sの歪みによって位置ずれが生じており、本発明で
は、CCDから構成される前記アライメント手段Aによ
って、焼結後切削前に全てのパターン1、2……、
1′、2′……、a、b……、a′、b′……について
座標値を検出し、アライメント情報としてCPUに記録
する工程を行う。即ち、〔「1」(x1 ,y1 ),
「1′」(x1 ′,y1 ′)〕、〔「2」(x2 ,y
2 ),「2′」(x2 ′,y2 ′)〕、…… 〔「a」(xa ,ya ),「a′」(xa ′,y
a ′)〕、〔「b」(xb ,yb ),「b′」(x
b ′,yb ′)〕、……等である。
The pattern is placed at an accurate position before the ceramic substrate S is sintered, but the position of the pattern is displaced due to the distortion of the ceramic substrate S after the sintering. By the means A, all patterns 1, 2, ...
The steps of detecting coordinate values of 1 ', 2' ..., a, b ..., a ', b' ... And recording them as alignment information in the CPU are performed. That is, [“1” (x 1 , y 1 ),
“1 ′” (x 1 ′, y 1 ′)], [“2” (x 2 , y
2), "2 '" (x 2', y 2 ' ) ], ... [ "a" (x a, y a), "a'" (x a ', y
a ′)], [“b” (x b , y b ), “b ′” (x
b ′, y b ′)], and so on.

【0008】セラミックス基板Sを切削するには、例え
ばパターン「1」、「1′」を結ぶラインを切削する場
合は、前記CPUから〔「1」(x1 ,y1 ),
「1′」(x1 ′,y1 ′)〕のアライメント情報を呼
び出して参照する工程、即ちこの座標値に基づいてアラ
イメント手段Aにて精密位置合わせ工程を行う。
In order to cut the ceramic substrate S, for example, when cutting a line connecting the patterns "1" and "1 '", from the CPU, "[1] (x 1 , y 1 ),
Performing fine alignment process by "1 '" (x 1', y 1 ') a step of referring to call the alignment information], i.e. the alignment means A on the basis of the coordinate values.

【0009】前記「1」(x1 ,y1 )、「1′」(x
1 ′,y1 ′)の座標のうち、y座標値yとy′とが同
じか否かを確認する。同じであれば前記回転ブレードB
をy座標値に位置付けて切削を遂行し、同じでない場合
は補正を行う。即ち、 tan-1Δθ=(y1 ′−y)/(x1 ′−x1 ) でΔθを算出し、前記チャックテーブルTを回転してΔ
θ補正を行うと共にy座標値の補正を行う。例えばパタ
ーン「1」の座標がチャックテーブルTの回転中心を中
心とした極座標で(r,θ)である場合、補正値Δy
は、 Δy=r〔sin(θ+Δθ)−sinθ〕 となり、(y1 +Δy)の座標値に回転ブレードBを位
置付ければ良いことになる。以後これを繰り返す。
The above "1" (x 1 , y 1 ) and "1 '" (x
Among the coordinates of 1 ', y 1 '), it is confirmed whether or not the y coordinate values y and y'are the same. If the same, the rotating blade B
Is positioned at the y-coordinate value and cutting is performed. If they are not the same, correction is performed. That is, Δθ is calculated by tan −1 Δθ = (y 1 ′ −y) / (x 1 ′ −x 1 ), and the chuck table T is rotated to obtain Δ.
The θ correction is performed and the y coordinate value is also corrected. For example, if the coordinates of the pattern “1” are polar coordinates (r, θ) around the center of rotation of the chuck table T, the correction value Δy
Becomes Δy = r [sin (θ + Δθ) −sin θ], and the rotary blade B should be positioned at the coordinate value of (y 1 + Δy). Thereafter, this is repeated.

【0010】このようにして、X軸方向の切削ライン毎
にCPUからアライメント情報を呼び出し、このアライ
メント情報に基づいて精密位置合わせを行いながら切削
を遂行する。パターンを結ぶ切削ラインに沿って切削す
ればチップを切断することはない。Y軸方向に沿って切
削するには、チャックテーブルを90度回転させて前記
X軸方向の場合と同じ要領にて切削を遂行することが出
来る。
In this manner, the CPU calls the alignment information for each cutting line in the X-axis direction, and the cutting is performed while performing the precise alignment based on the alignment information. The chip is not cut if it is cut along the cutting line that connects the patterns. To cut along the Y-axis direction, the chuck table can be rotated 90 degrees and the cutting can be performed in the same manner as in the case of the X-axis direction.

【0011】[0011]

【発明の効果】以上説明したように、本発明によれば、
セラミックス基板が焼結の歪みによって切削ラインの基
準となるパターンに位置ずれが生じても、予めアライメ
ント情報として記憶させたパターン座標値を切削ライン
毎にCPUから呼び出し、精密位置合わせを行いながら
切削する方法であるから、圧電素子等のチップを切断す
ることはなく、チップの損傷を未然に防止する効果を奏
する。
As described above, according to the present invention,
Even if the ceramic substrate is misaligned due to the distortion of sintering due to the distortion of the cutting line, the pattern coordinate values stored in advance as alignment information are called from the CPU for each cutting line, and cutting is performed while performing precision alignment. Since this is a method, the chip such as the piezoelectric element is not cut, and the effect of preventing damage to the chip is obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の実施の形態を示す説明図である。FIG. 1 is an explanatory diagram showing an embodiment of the present invention.

【図2】 切削装置の一例を示す斜視図である。FIG. 2 is a perspective view showing an example of a cutting device.

【図3】 セラミックス基板の切削状態を示す概略斜視
図である。
FIG. 3 is a schematic perspective view showing a cut state of a ceramic substrate.

【符号の説明】[Explanation of symbols]

A…アライメント手段 B…回転ブレード C…切削手段 L…切削ライン P…チップ S…セラミックス基板 T…チャックテーブル A ... Alignment means B ... Rotating blade C ... Cutting means L ... Cutting line P ... Chip S ... Ceramic substrate T ... Chuck table

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 セラミックス基板に形成された複数の圧
電素子等を個々のチップに分割する切削方法において、
全ての切削ラインの基準となるパターンをアライメント
してそのアライメント情報をCPUに記録する工程と、
切削すべきラインを切削する際に該当するアライメント
情報を呼び出して参照する工程とを少なくとも含む切削
方法。
1. A cutting method for dividing a plurality of piezoelectric elements or the like formed on a ceramic substrate into individual chips,
A step of aligning a reference pattern of all cutting lines and recording the alignment information in the CPU;
And a step of calling and referring to corresponding alignment information when cutting a line to be cut.
JP22455495A 1995-08-10 1995-08-10 Cutting method Expired - Lifetime JP3666068B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22455495A JP3666068B2 (en) 1995-08-10 1995-08-10 Cutting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22455495A JP3666068B2 (en) 1995-08-10 1995-08-10 Cutting method

Publications (2)

Publication Number Publication Date
JPH0952227A true JPH0952227A (en) 1997-02-25
JP3666068B2 JP3666068B2 (en) 2005-06-29

Family

ID=16815608

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22455495A Expired - Lifetime JP3666068B2 (en) 1995-08-10 1995-08-10 Cutting method

Country Status (1)

Country Link
JP (1) JP3666068B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002033295A (en) * 2000-07-14 2002-01-31 Disco Abrasive Syst Ltd Alignment method and aligner
JP2009044054A (en) * 2007-08-10 2009-02-26 Disco Abrasive Syst Ltd Method of dividing package substrate
JP2009049303A (en) * 2007-08-22 2009-03-05 Disco Abrasive Syst Ltd Method for dividing package substrate

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002033295A (en) * 2000-07-14 2002-01-31 Disco Abrasive Syst Ltd Alignment method and aligner
US6494122B2 (en) 2000-07-14 2002-12-17 Disco Corporation Alignment method and apparatus for aligning cutting blade
JP4640715B2 (en) * 2000-07-14 2011-03-02 株式会社ディスコ Alignment method and alignment apparatus
DE10133448B4 (en) * 2000-07-14 2012-08-30 Disco Corp. Alignment method and apparatus for aligning a cutting knife in a dicing machine
JP2009044054A (en) * 2007-08-10 2009-02-26 Disco Abrasive Syst Ltd Method of dividing package substrate
JP2009049303A (en) * 2007-08-22 2009-03-05 Disco Abrasive Syst Ltd Method for dividing package substrate

Also Published As

Publication number Publication date
JP3666068B2 (en) 2005-06-29

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