JP2757349B2 - Hybrid integrated circuit substrate and method of manufacturing hybrid integrated circuit device using the same - Google Patents

Hybrid integrated circuit substrate and method of manufacturing hybrid integrated circuit device using the same

Info

Publication number
JP2757349B2
JP2757349B2 JP4358090A JP4358090A JP2757349B2 JP 2757349 B2 JP2757349 B2 JP 2757349B2 JP 4358090 A JP4358090 A JP 4358090A JP 4358090 A JP4358090 A JP 4358090A JP 2757349 B2 JP2757349 B2 JP 2757349B2
Authority
JP
Japan
Prior art keywords
substrate
integrated circuit
hybrid integrated
green sheet
bare chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP4358090A
Other languages
Japanese (ja)
Other versions
JPH03246960A (en
Inventor
一高 鈴木
崇 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP4358090A priority Critical patent/JP2757349B2/en
Publication of JPH03246960A publication Critical patent/JPH03246960A/en
Application granted granted Critical
Publication of JP2757349B2 publication Critical patent/JP2757349B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/141One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters

Landscapes

  • Die Bonding (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To mount an electronic component on a board with high accuracy by a method wherein a hole for position recognition use is made in a part near a part where the electronic component is to be mounted in a ceramic green sheet and, after that, a conductor layer is formed. CONSTITUTION:A part 2 on which an electronic component is to be mounted and on which a bare chip 5 is mounted is formed of a conductor on a green sheet of a board 1 composed of an insulating ceramics or the like; holes 3, 3 for position recognition use are made near it by referring to the reference face of the board 1, e.g. its edge or its cut wire. Then, the green sheet is baked. When the bare chip 5 is mounted, the holes 3, 3 for position recognition use are pattern-recognized. The bare chip 5 is mounted by referring to them and is wire-bonded. Thereby, the electronic component can be mounted on the board with high accuracy.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、回路基板上にベアチップ等の電子部品を搭
載して構成される混成集積回路用の基板と、それを用い
た混成集積回路装置の製造方法に関する。
Description: TECHNICAL FIELD The present invention relates to a substrate for a hybrid integrated circuit configured by mounting an electronic component such as a bare chip on a circuit board, and a hybrid integrated circuit device using the same. And a method for producing the same.

[従来の技術] 従来の混成集積回路用セラミック基板を製造する場
合、一般に次の方法により製造される。まず、例えばド
クターブレード法と呼ばれる方法により、セラミックグ
リーンシート(以下、単に「グリーンシート」と呼ぶ)
を形成し、これを複数枚分の回路基板の大きさの板状に
打ち抜く。このとき、後の焼成工程でのグリーンシート
の縮みなどを考慮し、焼成されたグリーンシートから所
定のサイズを有する個々の回路基板が切り離せるよう
に、グリーンシートにスリットを入れておく。この状態
でグリーンシートを焼成する。こうして出来上がったも
のが混成集積回路用のセラミック基板(以下、単に「基
板」と呼ぶ)である。
[Prior Art] A conventional ceramic substrate for a hybrid integrated circuit is generally manufactured by the following method. First, for example, by a method called a doctor blade method, a ceramic green sheet (hereinafter, simply referred to as a “green sheet”)
Is formed, and this is punched into a plate having a size of a plurality of circuit boards. At this time, slits are formed in the green sheet so that individual circuit boards having a predetermined size can be separated from the fired green sheet in consideration of shrinkage of the green sheet in a subsequent firing step. The green sheet is fired in this state. The result is a ceramic substrate for a hybrid integrated circuit (hereinafter simply referred to as a “substrate”).

混成集積回路装置では、まず、このようにして形成さ
れた基板上に導体パターンが形成される。これと同時
に、第3図(a)で示すように、同じ導体でマーカー
4、4が基板1の所定の位置に形成される。
In the hybrid integrated circuit device, first, a conductor pattern is formed on the substrate thus formed. At the same time, as shown in FIG. 3 (a), the markers 4, 4 are formed at predetermined positions on the substrate 1 with the same conductor.

さらに、第3図(b)で示されたように、導体パター
ンの上にピン転写等で接着剤を塗布してから、プラスチ
ックやセラミック等で外装保護が施されてない回路がむ
き出しのままの集積回路、いわゆるベアチップ5が自動
搭載機により前記基板1の導体パターン上に搭載され
る。このベアチップ5を搭載する際、基板1上に形成し
た前記導体パターンと、前記基板1に搭載しようとする
ベアチップ5の端子電極とを電気的に接続するため、導
体パターンの正確な位置を確定する必要がある。そこで
従来では、導体により形成された前述のマーカー4、4
をパターン認識し、その位置を基準としてベアチップ5
が基板1の上の所定の導体パターン上に正確に載るよう
に、同じベアチップ5の搭載位置の補正を行いながら、
自動搭載機がベアチップ5を搭載している。
Further, as shown in FIG. 3 (b), after an adhesive is applied to the conductor pattern by pin transfer or the like, a circuit which is not protected by a plastic or ceramic or the like is exposed. An integrated circuit, a so-called bare chip 5, is mounted on the conductor pattern of the substrate 1 by an automatic mounting machine. When the bare chip 5 is mounted, an accurate position of the conductive pattern is determined in order to electrically connect the conductor pattern formed on the substrate 1 and the terminal electrodes of the bare chip 5 to be mounted on the substrate 1. There is a need. Therefore, conventionally, the above-described markers 4, 4 formed of conductors are used.
Is recognized, and the bare chip 5
So that the mounting position of the same bare chip 5 is corrected so that the mounting position is accurately placed on a predetermined conductor pattern on the substrate 1.
The automatic mounting machine mounts the bare chip 5.

[発明が解決しようとする課題] 混成集積回路に搭載されるベアチップの中には、フロ
ッピーディスクドライブに組み込まれる磁気センサーや
ロータリーエンコーダー等のように、基板の所定の基準
面からの位置出しを行わないと、機能的に働かないもの
がある。例えば、ロータリーエンコーダーは、ターンテ
ーブルのような回転する検体の回転数を検知するが、基
板の端面を基準として位置出しを行なわないと、装置へ
の組込位置が変動し、検体に対する相対位置が異なるた
め、その回転数を正確に計測できない。
[Problems to be Solved by the Invention] Some bare chips mounted on a hybrid integrated circuit perform positioning from a predetermined reference surface of a substrate, such as a magnetic sensor or a rotary encoder incorporated in a floppy disk drive. Without it, some will not work functionally. For example, a rotary encoder detects the number of rotations of a rotating sample such as a turntable, but if the position is not determined with reference to the end surface of the substrate, the mounting position in the apparatus changes, and the relative position with respect to the sample is changed. Due to the difference, the rotation speed cannot be measured accurately.

ところが、前記従来のように、基板1の上に導体で印
刷されたマーカー4、4でベアチップ5の搭載位置を決
定すると、ベアチップ5の基板1上での位置の誤差が大
きくなる。これは、次のような理由による。すなわち、
基板1への前記マーカー4、4の印刷は、スクリーン印
刷法により行なわれるが、前記ベアチップ5の基板1上
での絶対位置の誤差には、このときのマーカー4、4の
印刷誤差に加え、さらにマーカー4、4を基準としてベ
アチップ5を基板に搭載するときの搭載誤差が加わるか
らである。通常、前記印刷誤差と搭載誤差は、各々±20
0μm〜300μm程度であり、基板1の端面からのベアチ
ップ5の位置誤差は総体的に±600μmにもなる。これ
だけの搭載位置の誤差が生じると、前述したロータリー
エンコーダーのようなベアチップでは、機能上支障が生
じる。
However, when the mounting position of the bare chip 5 is determined by the markers 4 and 4 printed on the substrate 1 with conductors as in the conventional case, the error of the position of the bare chip 5 on the substrate 1 increases. This is for the following reasons. That is,
The printing of the markers 4 and 4 on the substrate 1 is performed by a screen printing method. In addition to the printing error of the markers 4 and 4 at this time, the error of the absolute position of the bare chip 5 on the substrate 1 is This is because a mounting error when mounting the bare chip 5 on the substrate with reference to the markers 4 and 4 is added. Usually, the printing error and the mounting error are each ± 20.
It is about 0 μm to 300 μm, and the position error of the bare chip 5 from the end face of the substrate 1 is generally ± 600 μm. If such an error in the mounting position occurs, a bare chip such as the rotary encoder described above causes a functional problem.

そこで本発明は、以上の問題を解決し、電子部品を基
板上へ搭載する時に、その電子部品の基板上での絶対位
置を容易に高精度で位置決めできる基板と、その基板を
用いた混成集積回路の製造方法を提供することを目的と
する。
Therefore, the present invention solves the above problems, and when mounting an electronic component on a substrate, a substrate that can easily and highly accurately position the absolute position of the electronic component on the substrate, and a hybrid integration using the substrate. An object of the present invention is to provide a method for manufacturing a circuit.

[課題を解決するための手段] すなわち、前記目的を達成するために、本発明におい
て採用した手段の要旨は、セラミックグリーンシートを
焼成したセラミック基板に導体層を形成してなる混成集
積回路用基板において、セラミックグリーンシートの回
路形成領域の電子部品搭載予定部の近傍に、位置認識用
の孔を設けてから焼成してセラミック基板を形成し、そ
の後に導体層を形成してなる混成集積回路用基板であ
る。
Means for Solving the Problems In order to achieve the above object, the gist of the means adopted in the present invention is that a substrate for a hybrid integrated circuit is formed by forming a conductor layer on a ceramic substrate obtained by firing a ceramic green sheet. A hole for position recognition is provided in the circuit forming area of the ceramic green sheet in the vicinity of the electronic component mounting portion, and then fired to form a ceramic substrate, and thereafter a conductive layer is formed. It is a substrate.

さらに、セラミックグリーンシートを所定の板状に打
ち抜きまたは切り出して焼成して形成してなるセラミッ
ク基板上に回路パターンを形成し、さらに電子部品を搭
載して、混成集積回路を製造する方法において、セラミ
ックグリーンシートを所定の板状に打ち抜きまたは切り
出す際に、セラミックグリーンシートの回路形成領域の
電子部品搭載予定部の近傍に位置認識用の孔を開け、こ
のセラミックグリーンシートを焼成してセラミック基板
を形成し、このセラミック基板に回路パターンを形成し
た混成集積回路用基板に電子部品を搭載するに当り、前
記位置確認用の孔を認識して電子部品の位置補正をする
混成集積回路装置の製造方法である。
Further, a method for manufacturing a hybrid integrated circuit by forming a circuit pattern on a ceramic substrate formed by punching or cutting a ceramic green sheet into a predetermined plate shape and firing the ceramic green sheet, and further mounting electronic components, When the green sheet is punched or cut into a predetermined plate shape, a hole for position recognition is opened near the electronic component mounting portion in the circuit forming area of the ceramic green sheet, and the ceramic green sheet is fired to form a ceramic substrate. When mounting electronic components on a substrate for a hybrid integrated circuit in which a circuit pattern is formed on the ceramic substrate, a method for manufacturing a hybrid integrated circuit device for recognizing the position confirmation holes and correcting the position of the electronic components. is there.

[作用] 上記位置認識用の孔は、集合基板の場合は基板分割用
スリットと同時に同一の金型で形成された後、焼成され
る。このときグリーンシートは1cmに付きおよそ40μm
の割合で収縮する。この収縮が孔の位置精度に与える影
響は、基板に導体でマーカーをスクリーン印刷したとき
の印刷誤差(約±200μm〜300μm)に比べてはるかに
小さい。このため、この孔を認識してベアチップの搭載
位置を補正し、基板上に搭載すると、従来方法よりも基
板上での絶対位置精度が向上する。
[Operation] In the case of a collective substrate, the hole for position recognition is formed in the same mold at the same time as the slit for dividing the substrate, and then fired. At this time, the green sheet is about 40μm per 1cm
Shrink at the rate of The effect of this shrinkage on the positional accuracy of the holes is much smaller than the printing error (about ± 200 μm to 300 μm) when a marker is screen-printed with a conductor on a substrate. Therefore, when the hole is recognized and the mounting position of the bare chip is corrected and mounted on the substrate, the absolute position accuracy on the substrate is improved as compared with the conventional method.

一般の電子部品は導体層と電気的に接続するために導
体層との位置関係が正確であることが要求されるが、前
述のベアチップは電気的な接続がワイヤボンディングを
用いて行なわれる。この接続法では、ベアチップの端子
電極と導体層の前記ベアチップの端子電極との位置関係
を一つ一つ調整しながら電気的接続が行われるので、導
体層と前記ベアチップとの位置関係の誤差はこの調整で
吸収される。従って導体層と前記ベアチップとの位置関
係を正確にすることよりも基板端面からの前記ベアチッ
プの位置を正確にすることがより重要である。
A general electronic component is required to have an accurate positional relationship with the conductor layer in order to be electrically connected to the conductor layer. However, in the above-described bare chip, the electrical connection is performed using wire bonding. In this connection method, electrical connection is performed while adjusting the positional relationship between the terminal electrode of the bare chip and the terminal electrode of the bare chip of the conductive layer one by one, so that the error in the positional relationship between the conductive layer and the bare chip is reduced. It is absorbed by this adjustment. Therefore, it is more important to make the position of the bare chip accurate from the end face of the substrate than to make the positional relationship between the conductor layer and the bare chip accurate.

[実施例] 以下、本発明の実施例について、詳細に説明する。[Example] Hereinafter, an example of the present invention will be described in detail.

第1図(a)に、本発明による混成集積回路用基板が
示されている。これは、絶縁性のセラミック等からなる
基板1の上に導体でベアチップ5が搭載される電子部品
搭載予定部2を形成し、その近傍に、基板の基準面、例
えばその端面や切断線を基準として、位置認識用の孔
3、3を開設したものである。この基板1の上の前記搭
載予定部2には、第1図(b)及び第2図で示すよう
に、ベアチップ5が搭載されるが、この際、前記位置認
識用の孔3、3をパターン認識し、これを基準としてベ
アチップ5の搭載位置を補正し、それを前記搭載予定部
2に搭載する。そして、第2図で示すように、ベアチッ
プ5をワイヤーボンディングする。
FIG. 1 (a) shows a substrate for a hybrid integrated circuit according to the present invention. In this method, an electronic component mounting portion 2 on which a bare chip 5 is to be mounted by a conductor is formed on a substrate 1 made of an insulating ceramic or the like, and a reference surface of the substrate, for example, an end surface or a cutting line, is formed near the portion. The holes 3, 3 for position recognition are opened. As shown in FIGS. 1 (b) and 2, a bare chip 5 is mounted on the mounting portion 2 on the substrate 1, and at this time, the holes 3 and 3 for position recognition are formed. The pattern is recognized, the mounting position of the bare chip 5 is corrected based on the pattern recognition, and the corrected position is mounted on the planned mounting section 2. Then, as shown in FIG. 2, the bare chip 5 is wire-bonded.

次に本発明の具体例について説明すると、アルミナを
主原料とするセラミックグリーンシートから、焼成後60
mm×60mmになるようにグリーンシートを打ち抜くと同時
に、位置認識用の0.3mmφの孔をグリーンシートの所定
の2か所に開けた後、このグリーンシートを焼成し、位
置認識用の孔3、3…を有する基板1を形成した。この
基板1上にスクリーン印刷法により、導体パターンを形
成した。この導体パターンの一部は、ベアチップの搭載
予定部2として形成されている。また、この導体パター
ンの形成と同時に、同じ導電材料で位置認識用のマーカ
ー4、4(第3図参照)を形成した。このマーカーは前
記位置認識用の孔3、3とは別の位置に設置した。ただ
し、導体パターン、マーカー及び位置認識用の孔3、3
との相対的位置関係は実質的に概ね同等となるように形
成した。
Next, a specific example of the present invention will be described.
At the same time as punching a green sheet so as to have a size of 60 mm, a hole of 0.3 mmφ for position recognition is opened in two predetermined places of the green sheet, and then the green sheet is fired to obtain a hole 3 for position recognition. 3 were formed. A conductor pattern was formed on the substrate 1 by a screen printing method. A part of this conductor pattern is formed as a portion 2 for mounting a bare chip. Simultaneously with the formation of the conductor pattern, markers 4 and 4 for position recognition (see FIG. 3) were formed of the same conductive material. This marker was installed at a position different from the holes 3 for position recognition. However, holes 3, 3 for the conductor pattern, the marker and the position recognition
Are formed so that the relative positional relationship with the above is substantially the same.

この基板1を複数用意し、その上にベアチップ5を搭
載した。この場合、その半数は、前記位置認識用の孔
3、3をパターン認識することにより、これを基準にし
てベアチップ5の搭載位置の補正をし、残り半数は、導
体で形成された前記位置認識マークをパターン認識する
ことにより、このマーカーの位置を基準としてベアチッ
プ5の搭載位置の補正をした。
A plurality of the substrates 1 were prepared, and a bare chip 5 was mounted thereon. In this case, half of the patterns are used to correct the mounting position of the bare chip 5 based on the pattern recognition of the holes 3 for position recognition, and the other half are used for the position recognition formed of conductors. By recognizing the pattern of the mark, the mounting position of the bare chip 5 was corrected based on the position of the marker.

この場合の基準1上でのベアチップ5の絶対位置の誤
差を測定し比較したところ、導体のマーカーをパターン
認識してベアチップ5を搭載した後者の基板1では、基
板1の端面を基準とするベアチップ5の搭載位置精度が
最大±600μmであった。これに対し、位置認識用の孔
3、3をパターン認識してベアチップ5を搭載した後者
の基板1では、基板1の端面を基準とするベアチップ5
の搭載位置精度が最大±200μmに押さえられた。
In this case, the error of the absolute position of the bare chip 5 on the reference 1 was measured and compared. As a result, in the latter substrate 1 on which the conductor marker was pattern-recognized and the bare chip 5 was mounted, the bare chip based on the end face of the substrate 1 was used. 5 had a maximum mounting position accuracy of ± 600 μm. On the other hand, in the latter substrate 1 on which the bare chips 5 are mounted by pattern recognition of the holes 3, 3 for position recognition, the bare chips 5 with respect to the end face of the substrate 1
The mounting position accuracy was kept at a maximum of ± 200 μm.

なお、本実施例では位置認識の孔3、3として丸孔を
開設しているが、これはパターン認識できるものであれ
ば、四角孔や三角孔或は十字孔等、どのような形状でも
構わない。
In the present embodiment, round holes are provided as the holes 3 and 3 for position recognition, but any shape such as a square hole, a triangular hole, or a cross hole may be used as long as it can recognize a pattern. Absent.

[発明の効果] 以上説明したように、本発明の混成集積回路用基板と
混成集積回路装置の製造方法では、電子部品を基板上に
高精度で搭載することができるという効果が得られる。
[Effects of the Invention] As described above, the method for manufacturing a substrate for a hybrid integrated circuit and the method of manufacturing a hybrid integrated circuit device of the present invention has an effect that an electronic component can be mounted on a substrate with high accuracy.

【図面の簡単な説明】[Brief description of the drawings]

第1図(a)、(b)は、本発明の実施例である混成集
積回路用基板の上にベアチップを搭載する前後の平面
図、第2図は、混成集積回路用基板の上にベアチップを
搭載し、それを結線した状態の斜視図、第3図(a)、
(b)は、従来例である混成集積回路用基板の上にベア
チップを搭載する前後の平面図である。 1…基板、2…電子部品搭載予定部、3…位置認識用の
孔、5…ベアチップ
1 (a) and 1 (b) are plan views before and after mounting a bare chip on a substrate for a hybrid integrated circuit according to an embodiment of the present invention, and FIG. 2 is a plan view showing a bare chip on a substrate for a hybrid integrated circuit. FIG. 3 (a) is a perspective view of a state in which
(B) is a plan view before and after mounting a bare chip on a hybrid integrated circuit substrate as a conventional example. DESCRIPTION OF SYMBOLS 1 ... board | substrate, 2 ... electronic component mounting part, 3 ... hole for position recognition, 5 ... bare chip

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】セラミックグリーンシートを焼成したセラ
ミック基板に導体層を形成してなる混成集積回路用基板
において、セラミックグリーンシートの回路形成領域の
電子部品搭載予定部の近傍に、位置確認用の孔を設けて
から焼成してセラミック基板を形成し、その後に導体層
を形成してなることを特徴とする混成集積回路用基板。
1. A substrate for a hybrid integrated circuit comprising a ceramic substrate on which a ceramic green sheet is fired and a conductor layer formed thereon, wherein a hole for confirming a position is formed in a circuit forming region of the ceramic green sheet in the vicinity of an electronic component mounting portion. Wherein a substrate is formed and fired to form a ceramic substrate, and thereafter a conductor layer is formed.
【請求項2】セラミックグリーンシートを所定の板状に
打ち抜きまたは切り出して焼成して形成してなるセラミ
ック基板上に回路パターンを形成し、さらに電子部品を
搭載して、混成集積回路を製造する方法において、セラ
ミックグリーンシートを所定の板状に打ち抜きまたは切
り出す際に、セラミックグリーンシートの回路形成領域
の電子部品搭載予定部の近傍に位置認識用の孔を開け、
このセラミックグリーンシートを焼成してセラミック基
板を形成し、このセラミック基板に回路パターンが形成
してなる混成集積回路用基板に電子部品を搭載するに当
り、前記位置確認用の孔を認識して電子部品の位置補正
をすることを特徴とする混成集積回路装置の製造方法。
2. A method of manufacturing a hybrid integrated circuit by forming a circuit pattern on a ceramic substrate formed by punching or cutting a ceramic green sheet into a predetermined plate shape and firing the same, and further mounting electronic components. In punching out or cutting out a ceramic green sheet into a predetermined plate shape, a hole for position recognition is made in the vicinity of an electronic component mounting portion of a circuit forming area of the ceramic green sheet,
When the ceramic green sheet is fired to form a ceramic substrate, and the electronic component is mounted on a substrate for a hybrid integrated circuit in which a circuit pattern is formed on the ceramic substrate, the electronic component is recognized by recognizing the position confirmation hole. A method for manufacturing a hybrid integrated circuit device, comprising: correcting a position of a component.
JP4358090A 1990-02-24 1990-02-24 Hybrid integrated circuit substrate and method of manufacturing hybrid integrated circuit device using the same Expired - Lifetime JP2757349B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4358090A JP2757349B2 (en) 1990-02-24 1990-02-24 Hybrid integrated circuit substrate and method of manufacturing hybrid integrated circuit device using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4358090A JP2757349B2 (en) 1990-02-24 1990-02-24 Hybrid integrated circuit substrate and method of manufacturing hybrid integrated circuit device using the same

Publications (2)

Publication Number Publication Date
JPH03246960A JPH03246960A (en) 1991-11-05
JP2757349B2 true JP2757349B2 (en) 1998-05-25

Family

ID=12667706

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4358090A Expired - Lifetime JP2757349B2 (en) 1990-02-24 1990-02-24 Hybrid integrated circuit substrate and method of manufacturing hybrid integrated circuit device using the same

Country Status (1)

Country Link
JP (1) JP2757349B2 (en)

Also Published As

Publication number Publication date
JPH03246960A (en) 1991-11-05

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